1 /*- 2 * Copyright (c) 2011 3 * Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/conf.h> 33 #include <sys/kernel.h> 34 #include <sys/rman.h> 35 #include <sys/module.h> 36 #include <sys/proc.h> 37 #include <sys/condvar.h> 38 39 #include <dev/fdt/fdt_common.h> 40 #include <dev/fdt/simplebus.h> 41 #include <dev/ofw/ofw_bus_subr.h> 42 43 #include <dev/usb/usb.h> 44 #include <dev/usb/usbdi.h> 45 46 #include <dev/usb/usb_core.h> 47 #include <dev/usb/usb_busdma.h> 48 #include <dev/usb/usb_process.h> 49 #include <dev/usb/usb_util.h> 50 51 #include <dev/usb/usb_controller.h> 52 #include <dev/usb/usb_bus.h> 53 #include <dev/usb/controller/ehci.h> 54 #include <dev/usb/controller/ehcireg.h> 55 56 #include <machine/bus.h> 57 58 #include <arm/ti/ti_prcm.h> 59 #include <arm/ti/usb/omap_usb.h> 60 61 /* EHCI */ 62 #define OMAP_USBHOST_HCCAPBASE 0x0000 63 #define OMAP_USBHOST_HCSPARAMS 0x0004 64 #define OMAP_USBHOST_HCCPARAMS 0x0008 65 #define OMAP_USBHOST_USBCMD 0x0010 66 #define OMAP_USBHOST_USBSTS 0x0014 67 #define OMAP_USBHOST_USBINTR 0x0018 68 #define OMAP_USBHOST_FRINDEX 0x001C 69 #define OMAP_USBHOST_CTRLDSSEGMENT 0x0020 70 #define OMAP_USBHOST_PERIODICLISTBASE 0x0024 71 #define OMAP_USBHOST_ASYNCLISTADDR 0x0028 72 #define OMAP_USBHOST_CONFIGFLAG 0x0050 73 #define OMAP_USBHOST_PORTSC(i) (0x0054 + (0x04 * (i))) 74 #define OMAP_USBHOST_INSNREG00 0x0090 75 #define OMAP_USBHOST_INSNREG01 0x0094 76 #define OMAP_USBHOST_INSNREG02 0x0098 77 #define OMAP_USBHOST_INSNREG03 0x009C 78 #define OMAP_USBHOST_INSNREG04 0x00A0 79 #define OMAP_USBHOST_INSNREG05_UTMI 0x00A4 80 #define OMAP_USBHOST_INSNREG05_ULPI 0x00A4 81 #define OMAP_USBHOST_INSNREG06 0x00A8 82 #define OMAP_USBHOST_INSNREG07 0x00AC 83 #define OMAP_USBHOST_INSNREG08 0x00B0 84 85 #define OMAP_USBHOST_INSNREG04_DISABLE_UNSUSPEND (1 << 5) 86 87 #define OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT 31 88 #define OMAP_USBHOST_INSNREG05_ULPI_PORTSEL_SHIFT 24 89 #define OMAP_USBHOST_INSNREG05_ULPI_OPSEL_SHIFT 22 90 #define OMAP_USBHOST_INSNREG05_ULPI_REGADD_SHIFT 16 91 #define OMAP_USBHOST_INSNREG05_ULPI_EXTREGADD_SHIFT 8 92 #define OMAP_USBHOST_INSNREG05_ULPI_WRDATA_SHIFT 0 93 94 #define ULPI_FUNC_CTRL_RESET (1 << 5) 95 96 /*-------------------------------------------------------------------------*/ 97 98 /* 99 * Macros for Set and Clear 100 * See ULPI 1.1 specification to find the registers with Set and Clear offsets 101 */ 102 #define ULPI_SET(a) (a + 1) 103 #define ULPI_CLR(a) (a + 2) 104 105 /*-------------------------------------------------------------------------*/ 106 107 /* 108 * Register Map 109 */ 110 #define ULPI_VENDOR_ID_LOW 0x00 111 #define ULPI_VENDOR_ID_HIGH 0x01 112 #define ULPI_PRODUCT_ID_LOW 0x02 113 #define ULPI_PRODUCT_ID_HIGH 0x03 114 #define ULPI_FUNC_CTRL 0x04 115 #define ULPI_IFC_CTRL 0x07 116 #define ULPI_OTG_CTRL 0x0a 117 #define ULPI_USB_INT_EN_RISE 0x0d 118 #define ULPI_USB_INT_EN_FALL 0x10 119 #define ULPI_USB_INT_STS 0x13 120 #define ULPI_USB_INT_LATCH 0x14 121 #define ULPI_DEBUG 0x15 122 #define ULPI_SCRATCH 0x16 123 124 #define OMAP_EHCI_HC_DEVSTR "TI OMAP USB 2.0 controller" 125 126 struct omap_ehci_softc { 127 ehci_softc_t base; /* storage for EHCI code */ 128 device_t sc_dev; 129 }; 130 131 static device_attach_t omap_ehci_attach; 132 static device_detach_t omap_ehci_detach; 133 134 /** 135 * omap_ehci_read_4 - read a 32-bit value from the EHCI registers 136 * omap_ehci_write_4 - write a 32-bit value from the EHCI registers 137 * @sc: omap ehci device context 138 * @off: byte offset within the register set to read from 139 * @val: the value to write into the register 140 * 141 * 142 * LOCKING: 143 * None 144 * 145 * RETURNS: 146 * nothing in case of write function, if read function returns the value read. 147 */ 148 static inline uint32_t 149 omap_ehci_read_4(struct omap_ehci_softc *sc, bus_size_t off) 150 { 151 return (bus_read_4(sc->base.sc_io_res, off)); 152 } 153 154 static inline void 155 omap_ehci_write_4(struct omap_ehci_softc *sc, bus_size_t off, uint32_t val) 156 { 157 bus_write_4(sc->base.sc_io_res, off, val); 158 } 159 160 /** 161 * omap_ehci_soft_phy_reset - resets the phy using the reset command 162 * @isc: omap ehci device context 163 * @port: port to send the reset over 164 * 165 * 166 * LOCKING: 167 * none 168 * 169 * RETURNS: 170 * nothing 171 */ 172 static void 173 omap_ehci_soft_phy_reset(struct omap_ehci_softc *isc, unsigned int port) 174 { 175 unsigned long timeout = (hz < 10) ? 1 : ((100 * hz) / 1000); 176 uint32_t reg; 177 178 reg = ULPI_FUNC_CTRL_RESET 179 /* FUNCTION_CTRL_SET register */ 180 | (ULPI_SET(ULPI_FUNC_CTRL) << OMAP_USBHOST_INSNREG05_ULPI_REGADD_SHIFT) 181 /* Write */ 182 | (2 << OMAP_USBHOST_INSNREG05_ULPI_OPSEL_SHIFT) 183 /* PORTn */ 184 | ((port + 1) << OMAP_USBHOST_INSNREG05_ULPI_PORTSEL_SHIFT) 185 /* start ULPI access*/ 186 | (1 << OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT); 187 188 omap_ehci_write_4(isc, OMAP_USBHOST_INSNREG05_ULPI, reg); 189 190 /* Wait for ULPI access completion */ 191 while ((omap_ehci_read_4(isc, OMAP_USBHOST_INSNREG05_ULPI) 192 & (1 << OMAP_USBHOST_INSNREG05_ULPI_CONTROL_SHIFT))) { 193 194 /* Sleep for a tick */ 195 pause("USBPHY_RESET", 1); 196 197 if (timeout-- == 0) { 198 device_printf(isc->sc_dev, "PHY reset operation timed out\n"); 199 break; 200 } 201 } 202 } 203 204 /** 205 * omap_ehci_init - initialises the USB host EHCI controller 206 * @isc: omap ehci device context 207 * 208 * This initialisation routine is quite heavily based on the work done by the 209 * OMAP Linux team (for which I thank them very much). The init sequence is 210 * almost identical, diverging only for the FreeBSD specifics. 211 * 212 * LOCKING: 213 * none 214 * 215 * RETURNS: 216 * 0 on success, a negative error code on failure. 217 */ 218 static int 219 omap_ehci_init(struct omap_ehci_softc *isc) 220 { 221 uint32_t reg = 0; 222 int i; 223 device_t uhh_dev; 224 225 uhh_dev = device_get_parent(isc->sc_dev); 226 device_printf(isc->sc_dev, "Starting TI EHCI USB Controller\n"); 227 228 /* Set the interrupt threshold control, it controls the maximum rate at 229 * which the host controller issues interrupts. We set it to 1 microframe 230 * at startup - the default is 8 mircoframes (equates to 1ms). 231 */ 232 reg = omap_ehci_read_4(isc, OMAP_USBHOST_USBCMD); 233 reg &= 0xff00ffff; 234 reg |= (1 << 16); 235 omap_ehci_write_4(isc, OMAP_USBHOST_USBCMD, reg); 236 237 /* Soft reset the PHY using PHY reset command over ULPI */ 238 for (i = 0; i < OMAP_HS_USB_PORTS; i++) { 239 if (omap_usb_port_mode(uhh_dev, i) == EHCI_HCD_OMAP_MODE_PHY) 240 omap_ehci_soft_phy_reset(isc, i); 241 242 } 243 244 return(0); 245 } 246 247 /** 248 * omap_ehci_probe - starts the given command 249 * @dev: 250 * 251 * Effectively boilerplate EHCI resume code. 252 * 253 * LOCKING: 254 * Caller should be holding the OMAP3_MMC lock. 255 * 256 * RETURNS: 257 * EH_HANDLED or EH_NOT_HANDLED 258 */ 259 static int 260 omap_ehci_probe(device_t dev) 261 { 262 263 if (!ofw_bus_status_okay(dev)) 264 return (ENXIO); 265 266 if (!ofw_bus_is_compatible(dev, "ti,ehci-omap")) 267 return (ENXIO); 268 269 device_set_desc(dev, OMAP_EHCI_HC_DEVSTR); 270 271 return (BUS_PROBE_DEFAULT); 272 } 273 274 /** 275 * omap_ehci_attach - driver entry point, sets up the ECHI controller/driver 276 * @dev: the new device handle 277 * 278 * Sets up bus spaces, interrupt handles, etc for the EHCI controller. It also 279 * parses the resource hints and calls omap_ehci_init() to initialise the 280 * H/W. 281 * 282 * LOCKING: 283 * none 284 * 285 * RETURNS: 286 * 0 on success or a positive error code on failure. 287 */ 288 static int 289 omap_ehci_attach(device_t dev) 290 { 291 struct omap_ehci_softc *isc = device_get_softc(dev); 292 ehci_softc_t *sc = &isc->base; 293 int err; 294 int rid; 295 296 /* initialise some bus fields */ 297 sc->sc_bus.parent = dev; 298 sc->sc_bus.devices = sc->sc_devices; 299 sc->sc_bus.devices_max = EHCI_MAX_DEVICES; 300 sc->sc_bus.dma_bits = 32; 301 302 sprintf(sc->sc_vendor, "Texas Instruments"); 303 304 /* save the device */ 305 isc->sc_dev = dev; 306 307 /* get all DMA memory */ 308 if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev), 309 &ehci_iterate_hw_softc)) { 310 return (ENOMEM); 311 } 312 313 /* Allocate resource for the EHCI register set */ 314 rid = 0; 315 sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 316 if (!sc->sc_io_res) { 317 device_printf(dev, "Error: Could not map EHCI memory\n"); 318 goto error; 319 } 320 /* Request an interrupt resource */ 321 rid = 0; 322 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); 323 if (sc->sc_irq_res == NULL) { 324 device_printf(dev, "Error: could not allocate irq\n"); 325 goto error; 326 } 327 328 /* Add this device as a child of the USBus device */ 329 sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); 330 if (!sc->sc_bus.bdev) { 331 device_printf(dev, "Error: could not add USB device\n"); 332 goto error; 333 } 334 335 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 336 device_set_desc(sc->sc_bus.bdev, OMAP_EHCI_HC_DEVSTR); 337 338 /* Initialise the ECHI registers */ 339 err = omap_ehci_init(isc); 340 if (err) { 341 device_printf(dev, "Error: could not setup OMAP EHCI, %d\n", err); 342 goto error; 343 } 344 345 /* Set the tag and size of the register set in the EHCI context */ 346 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 347 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 348 sc->sc_io_size = rman_get_size(sc->sc_io_res); 349 350 /* Setup the interrupt */ 351 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 352 NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl); 353 if (err) { 354 device_printf(dev, "Error: could not setup irq, %d\n", err); 355 sc->sc_intr_hdl = NULL; 356 goto error; 357 } 358 359 /* Finally we are ready to kick off the ECHI host controller */ 360 err = ehci_init(sc); 361 if (err == 0) { 362 err = device_probe_and_attach(sc->sc_bus.bdev); 363 } 364 if (err) { 365 device_printf(dev, "Error: USB init failed err=%d\n", err); 366 goto error; 367 } 368 369 return (0); 370 371 error: 372 omap_ehci_detach(dev); 373 return (ENXIO); 374 } 375 376 /** 377 * omap_ehci_detach - detach the device and cleanup the driver 378 * @dev: device handle 379 * 380 * Clean-up routine where everything initialised in omap_ehci_attach is 381 * freed and cleaned up. This function calls omap_ehci_fini() to shutdown 382 * the on-chip module. 383 * 384 * LOCKING: 385 * none 386 * 387 * RETURNS: 388 * Always returns 0 (success). 389 */ 390 static int 391 omap_ehci_detach(device_t dev) 392 { 393 struct omap_ehci_softc *isc = device_get_softc(dev); 394 ehci_softc_t *sc = &isc->base; 395 device_t bdev; 396 int err; 397 398 if (sc->sc_bus.bdev) { 399 bdev = sc->sc_bus.bdev; 400 device_detach(bdev); 401 device_delete_child(dev, bdev); 402 } 403 404 /* during module unload there are lots of children leftover */ 405 device_delete_children(dev); 406 407 /* 408 * disable interrupts that might have been switched on in ehci_init 409 */ 410 if (sc->sc_io_res) { 411 EWRITE4(sc, EHCI_USBINTR, 0); 412 } 413 414 if (sc->sc_irq_res && sc->sc_intr_hdl) { 415 /* 416 * only call ehci_detach() after ehci_init() 417 */ 418 ehci_detach(sc); 419 420 err = bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr_hdl); 421 if (err) 422 device_printf(dev, "Error: could not tear down irq, %d\n", err); 423 sc->sc_intr_hdl = NULL; 424 } 425 426 /* Free the resources stored in the base EHCI handler */ 427 if (sc->sc_irq_res) { 428 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 429 sc->sc_irq_res = NULL; 430 } 431 if (sc->sc_io_res) { 432 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_io_res); 433 sc->sc_io_res = NULL; 434 } 435 436 return (0); 437 } 438 439 static device_method_t ehci_methods[] = { 440 /* Device interface */ 441 DEVMETHOD(device_probe, omap_ehci_probe), 442 DEVMETHOD(device_attach, omap_ehci_attach), 443 DEVMETHOD(device_detach, omap_ehci_detach), 444 445 DEVMETHOD(device_suspend, bus_generic_suspend), 446 DEVMETHOD(device_resume, bus_generic_resume), 447 DEVMETHOD(device_shutdown, bus_generic_shutdown), 448 449 /* Bus interface */ 450 DEVMETHOD(bus_print_child, bus_generic_print_child), 451 452 {0, 0} 453 }; 454 455 static driver_t ehci_driver = { 456 "ehci", 457 ehci_methods, 458 sizeof(struct omap_ehci_softc), 459 }; 460 461 static devclass_t ehci_devclass; 462 463 DRIVER_MODULE(ehci, omap_uhh, ehci_driver, ehci_devclass, 0, 0); 464