xref: /freebsd/sys/arm/ti/ti_wdt.c (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c)
1 /*-
2  * Copyright (c) 2014 Rui Paulo <rpaulo@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24  * POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include <sys/param.h>
28 #include <sys/systm.h>
29 #include <sys/bus.h>
30 #include <sys/conf.h>
31 #include <sys/eventhandler.h>
32 #include <sys/kernel.h>
33 #include <sys/module.h>
34 #include <sys/malloc.h>
35 #include <sys/rman.h>
36 #include <sys/event.h>
37 #include <sys/selinfo.h>
38 #include <sys/watchdog.h>
39 #include <machine/bus.h>
40 #include <machine/cpu.h>
41 #include <machine/frame.h>
42 #include <machine/intr.h>
43 
44 #include <dev/ofw/openfirm.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
47 
48 #include <machine/bus.h>
49 
50 #include <arm/ti/ti_wdt.h>
51 
52 #ifdef DEBUG
53 #define	DPRINTF(fmt, ...)	do {	\
54 	printf("%s: ", __func__);	\
55 	printf(fmt, __VA_ARGS__);	\
56 } while (0)
57 #else
58 #define	DPRINTF(fmt, ...)
59 #endif
60 
61 static device_probe_t		ti_wdt_probe;
62 static device_attach_t		ti_wdt_attach;
63 static device_detach_t		ti_wdt_detach;
64 static void			ti_wdt_intr(void *);
65 static void			ti_wdt_event(void *, unsigned int, int *);
66 
67 struct ti_wdt_softc {
68 	struct resource 	*sc_mem_res;
69 	struct resource 	*sc_irq_res;
70 	void            	*sc_intr;
71 	bus_space_tag_t		sc_bt;
72 	bus_space_handle_t	sc_bh;
73 	eventhandler_tag	sc_ev_tag;
74 };
75 
76 static device_method_t ti_wdt_methods[] = {
77 	DEVMETHOD(device_probe,		ti_wdt_probe),
78 	DEVMETHOD(device_attach,	ti_wdt_attach),
79 	DEVMETHOD(device_detach,	ti_wdt_detach),
80 
81 	DEVMETHOD_END
82 };
83 
84 static driver_t ti_wdt_driver = {
85 	"ti_wdt",
86 	ti_wdt_methods,
87 	sizeof(struct ti_wdt_softc)
88 };
89 
90 DRIVER_MODULE(ti_wdt, simplebus, ti_wdt_driver, 0, 0);
91 MODULE_DEPEND(ti_wdt, ti_sysc, 1, 1, 1);
92 
93 static __inline uint32_t
94 ti_wdt_reg_read(struct ti_wdt_softc *sc, uint32_t reg)
95 {
96 
97 	return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
98 }
99 
100 static __inline void
101 ti_wdt_reg_write(struct ti_wdt_softc *sc, uint32_t reg, uint32_t val)
102 {
103 
104 	bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
105 }
106 
107 /*
108  * Wait for the write to a specific synchronised register to complete.
109  */
110 static __inline void
111 ti_wdt_reg_wait(struct ti_wdt_softc *sc, uint32_t bit)
112 {
113 
114 	while (ti_wdt_reg_read(sc, TI_WDT_WWPS) & bit)
115 		DELAY(10);
116 }
117 
118 static __inline void
119 ti_wdt_disable(struct ti_wdt_softc *sc)
120 {
121 
122 	DPRINTF("disabling watchdog %p\n", sc);
123 	ti_wdt_reg_write(sc, TI_WDT_WSPR, 0xAAAA);
124 	ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
125 	ti_wdt_reg_write(sc, TI_WDT_WSPR, 0x5555);
126 	ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
127 }
128 
129 static __inline void
130 ti_wdt_enable(struct ti_wdt_softc *sc)
131 {
132 
133 	DPRINTF("enabling watchdog %p\n", sc);
134 	ti_wdt_reg_write(sc, TI_WDT_WSPR, 0xBBBB);
135 	ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
136 	ti_wdt_reg_write(sc, TI_WDT_WSPR, 0x4444);
137 	ti_wdt_reg_wait(sc, TI_W_PEND_WSPR);
138 }
139 
140 static int
141 ti_wdt_probe(device_t dev)
142 {
143 
144 	if (!ofw_bus_status_okay(dev))
145 		return (ENXIO);
146 	if (ofw_bus_is_compatible(dev, "ti,omap3-wdt")) {
147 		device_set_desc(dev, "TI Watchdog Timer");
148 		return (BUS_PROBE_DEFAULT);
149 	}
150 
151 	return (ENXIO);
152 }
153 
154 static int
155 ti_wdt_attach(device_t dev)
156 {
157 	struct ti_wdt_softc *sc;
158 	int rid;
159 
160 	sc = device_get_softc(dev);
161 	rid = 0;
162 	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
163 	    RF_ACTIVE);
164 	if (sc->sc_mem_res == NULL) {
165 		device_printf(dev, "could not allocate memory resource\n");
166 		return (ENXIO);
167 	}
168 	sc->sc_bt = rman_get_bustag(sc->sc_mem_res);
169 	sc->sc_bh = rman_get_bushandle(sc->sc_mem_res);
170 	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
171 	if (sc->sc_irq_res == NULL) {
172 		device_printf(dev, "could not allocate interrupt resource\n");
173 		ti_wdt_detach(dev);
174 		return (ENXIO);
175 	}
176 	if (bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE | INTR_TYPE_MISC,
177 		NULL, ti_wdt_intr, sc,  &sc->sc_intr) != 0) {
178 		device_printf(dev,
179 		    "unable to setup the interrupt handler\n");
180 		ti_wdt_detach(dev);
181 		return (ENXIO);
182 	}
183 	/* Reset, enable interrupts and stop the watchdog. */
184 	ti_wdt_reg_write(sc, TI_WDT_WDSC,
185 	    ti_wdt_reg_read(sc, TI_WDT_WDSC) | TI_WDSC_SR);
186 	while (ti_wdt_reg_read(sc, TI_WDT_WDSC) & TI_WDSC_SR)
187 		DELAY(10);
188 	ti_wdt_reg_write(sc, TI_WDT_WIRQENSET, TI_IRQ_EN_OVF | TI_IRQ_EN_DLY);
189 	ti_wdt_disable(sc);
190 	if (bootverbose)
191 		device_printf(dev, "revision: 0x%x\n",
192 		    ti_wdt_reg_read(sc, TI_WDT_WIDR));
193 	sc->sc_ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ti_wdt_event, sc,
194 	    0);
195 
196 	return (0);
197 }
198 
199 static int
200 ti_wdt_detach(device_t dev)
201 {
202 	struct ti_wdt_softc *sc;
203 
204 	sc = device_get_softc(dev);
205 	if (sc->sc_ev_tag)
206 		EVENTHANDLER_DEREGISTER(watchdog_list, sc->sc_ev_tag);
207 	if (sc->sc_intr)
208 		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr);
209 	if (sc->sc_irq_res)
210 		bus_release_resource(dev, SYS_RES_IRQ,
211 		    rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
212 	if (sc->sc_mem_res)
213 		bus_release_resource(dev, SYS_RES_MEMORY,
214 		    rman_get_rid(sc->sc_mem_res),  sc->sc_mem_res);
215 
216 	return (0);
217 }
218 
219 static void
220 ti_wdt_intr(void *arg)
221 {
222 	struct ti_wdt_softc *sc;
223 
224 	sc = arg;
225 	DPRINTF("interrupt %p", sc);
226 	ti_wdt_reg_write(sc, TI_WDT_WIRQSTAT, TI_IRQ_EV_OVF | TI_IRQ_EV_DLY);
227 	/* TODO: handle interrupt */
228 }
229 
230 static void
231 ti_wdt_event(void *arg, unsigned int cmd, int *error)
232 {
233 	struct ti_wdt_softc *sc;
234 	uint8_t s;
235 	uint32_t wldr;
236 	uint32_t ptv;
237 
238 	sc = arg;
239 	ti_wdt_disable(sc);
240 	if (cmd == WD_TO_NEVER) {
241 		*error = 0;
242 		return;
243 	}
244 	DPRINTF("cmd 0x%x\n", cmd);
245 	cmd &= WD_INTERVAL;
246 	if (cmd < WD_TO_1SEC) {
247 		*error = EINVAL;
248 		return;
249 	}
250 	s = 1 << (cmd - WD_TO_1SEC);
251 	DPRINTF("seconds %u\n", s);
252 	/*
253 	 * Leave the pre-scaler with its default values:
254 	 * PTV = 0 == 2**0 == 1
255 	 * PRE = 1 (enabled)
256 	 *
257 	 * Compute the load register value assuming a 32kHz clock.
258 	 * See OVF_Rate in the WDT section of the AM335x TRM.
259 	 */
260 	ptv = 0;
261 	wldr = 0xffffffff - (s * (32768 / (1 << ptv))) + 1;
262 	DPRINTF("wldr 0x%x\n", wldr);
263 	ti_wdt_reg_write(sc, TI_WDT_WLDR, wldr);
264 	/*
265 	 * Trigger a timer reload.
266 	 */
267 	ti_wdt_reg_write(sc, TI_WDT_WTGR,
268 	    ti_wdt_reg_read(sc, TI_WDT_WTGR) + 1);
269 	ti_wdt_reg_wait(sc, TI_W_PEND_WTGR);
270 	ti_wdt_enable(sc);
271 	*error = 0;
272 }
273