1 /*- 2 * Copyright (c) 2019 Emmanuel Vadot <manu@FreeBSD.org> 3 * 4 * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/fbio.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/queue.h> 38 #include <sys/rman.h> 39 #include <sys/resource.h> 40 #include <machine/bus.h> 41 #include <vm/vm.h> 42 #include <vm/vm_extern.h> 43 #include <vm/vm_kern.h> 44 #include <vm/pmap.h> 45 46 #include <dev/fdt/simplebus.h> 47 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <dev/extres/clk/clk.h> 52 53 #include <arm/ti/ti_sysc.h> 54 #include <arm/ti/clk/clock_common.h> 55 56 #define DEBUG_SYSC 0 57 58 #if DEBUG_SYSC 59 #define DPRINTF(dev, msg...) device_printf(dev, msg) 60 #else 61 #define DPRINTF(dev, msg...) 62 #endif 63 64 /* Documentation/devicetree/bindings/bus/ti-sysc.txt 65 * 66 * Documentation/devicetree/clock/clock-bindings.txt 67 * Defines phandle + optional pair 68 * Documentation/devicetree/clock/ti-clkctl.txt 69 */ 70 71 static int ti_sysc_probe(device_t dev); 72 static int ti_sysc_attach(device_t dev); 73 static int ti_sysc_detach(device_t dev); 74 75 #define TI_SYSC_DRA7_MCAN 15 76 #define TI_SYSC_USB_HOST_FS 14 77 #define TI_SYSC_DRA7_MCASP 13 78 #define TI_SYSC_MCASP 12 79 #define TI_SYSC_OMAP_AES 11 80 #define TI_SYSC_OMAP3_SHAM 10 81 #define TI_SYSC_OMAP4_SR 9 82 #define TI_SYSC_OMAP3630_SR 8 83 #define TI_SYSC_OMAP3430_SR 7 84 #define TI_SYSC_OMAP4_TIMER 6 85 #define TI_SYSC_OMAP2_TIMER 5 86 /* Above needs special workarounds */ 87 #define TI_SYSC_OMAP4_SIMPLE 4 88 #define TI_SYSC_OMAP4 3 89 #define TI_SYSC_OMAP2 2 90 #define TI_SYSC 1 91 #define TI_SYSC_END 0 92 93 static struct ofw_compat_data compat_data[] = { 94 { "ti,sysc-dra7-mcan", TI_SYSC_DRA7_MCAN }, 95 { "ti,sysc-usb-host-fs", TI_SYSC_USB_HOST_FS }, 96 { "ti,sysc-dra7-mcasp", TI_SYSC_DRA7_MCASP }, 97 { "ti,sysc-mcasp", TI_SYSC_MCASP }, 98 { "ti,sysc-omap-aes", TI_SYSC_OMAP_AES }, 99 { "ti,sysc-omap3-sham", TI_SYSC_OMAP3_SHAM }, 100 { "ti,sysc-omap4-sr", TI_SYSC_OMAP4_SR }, 101 { "ti,sysc-omap3630-sr", TI_SYSC_OMAP3630_SR }, 102 { "ti,sysc-omap3430-sr", TI_SYSC_OMAP3430_SR }, 103 { "ti,sysc-omap4-timer", TI_SYSC_OMAP4_TIMER }, 104 { "ti,sysc-omap2-timer", TI_SYSC_OMAP2_TIMER }, 105 /* Above needs special workarounds */ 106 { "ti,sysc-omap4-simple", TI_SYSC_OMAP4_SIMPLE }, 107 { "ti,sysc-omap4", TI_SYSC_OMAP4 }, 108 { "ti,sysc-omap2", TI_SYSC_OMAP2 }, 109 { "ti,sysc", TI_SYSC }, 110 { NULL, TI_SYSC_END } 111 }; 112 113 /* reg-names can be "rev", "sysc" and "syss" */ 114 static const char * reg_names[] = { "rev", "sysc", "syss" }; 115 #define REG_REV 0 116 #define REG_SYSC 1 117 #define REG_SYSS 2 118 #define REG_MAX 3 119 120 /* master idle / slave idle mode defined in 8.1.3.2.1 / 8.1.3.2.2 */ 121 #include <dt-bindings/bus/ti-sysc.h> 122 #define SYSC_IDLE_MAX 4 123 124 struct sysc_reg { 125 uint64_t address; 126 uint64_t size; 127 }; 128 129 struct clk_list { 130 TAILQ_ENTRY(clk_list) next; 131 clk_t clk; 132 }; 133 134 struct ti_sysc_softc { 135 struct simplebus_softc sc; 136 bool attach_done; 137 138 device_t dev; 139 int device_type; 140 141 struct sysc_reg reg[REG_MAX]; 142 /* Offset from host base address */ 143 uint64_t offset_reg[REG_MAX]; 144 145 uint32_t ti_sysc_mask; 146 int32_t ti_sysc_midle[SYSC_IDLE_MAX]; 147 int32_t ti_sysc_sidle[SYSC_IDLE_MAX]; 148 uint32_t ti_sysc_delay_us; 149 uint32_t ti_syss_mask; 150 151 int num_clocks; 152 TAILQ_HEAD(, clk_list) clk_list; 153 154 /* deprecated ti_hwmods */ 155 bool ti_no_reset_on_init; 156 bool ti_no_idle_on_init; 157 bool ti_no_idle; 158 }; 159 160 /* 161 * All sysc seems to have a reg["rev"] register. 162 * Lets use that for identification of which module the driver are connected to. 163 */ 164 uint64_t 165 ti_sysc_get_rev_address(device_t dev) { 166 struct ti_sysc_softc *sc = device_get_softc(dev); 167 168 return (sc->reg[REG_REV].address); 169 } 170 171 uint64_t 172 ti_sysc_get_rev_address_offset_host(device_t dev) { 173 struct ti_sysc_softc *sc = device_get_softc(dev); 174 175 return (sc->offset_reg[REG_REV]); 176 } 177 178 uint64_t 179 ti_sysc_get_sysc_address(device_t dev) { 180 struct ti_sysc_softc *sc = device_get_softc(dev); 181 182 return (sc->reg[REG_SYSC].address); 183 } 184 185 uint64_t 186 ti_sysc_get_sysc_address_offset_host(device_t dev) { 187 struct ti_sysc_softc *sc = device_get_softc(dev); 188 189 return (sc->offset_reg[REG_SYSC]); 190 } 191 192 uint64_t 193 ti_sysc_get_syss_address(device_t dev) { 194 struct ti_sysc_softc *sc = device_get_softc(dev); 195 196 return (sc->reg[REG_SYSS].address); 197 } 198 199 uint64_t 200 ti_sysc_get_syss_address_offset_host(device_t dev) { 201 struct ti_sysc_softc *sc = device_get_softc(dev); 202 203 return (sc->offset_reg[REG_SYSS]); 204 } 205 206 /* 207 * Due no memory region is assigned the sysc driver the children needs to 208 * handle the practical read/writes to the registers. 209 * Check if sysc has reset bit. 210 */ 211 uint32_t 212 ti_sysc_get_soft_reset_bit(device_t dev) { 213 struct ti_sysc_softc *sc = device_get_softc(dev); 214 switch (sc->device_type) { 215 case TI_SYSC_OMAP4_TIMER: 216 case TI_SYSC_OMAP4_SIMPLE: 217 case TI_SYSC_OMAP4: 218 if (sc->ti_sysc_mask & SYSC_OMAP4_SOFTRESET) { 219 return (SYSC_OMAP4_SOFTRESET); 220 } 221 break; 222 223 case TI_SYSC_OMAP2_TIMER: 224 case TI_SYSC_OMAP2: 225 case TI_SYSC: 226 if (sc->ti_sysc_mask & SYSC_OMAP2_SOFTRESET) { 227 return (SYSC_OMAP2_SOFTRESET); 228 } 229 break; 230 default: 231 break; 232 } 233 234 return (0); 235 } 236 237 int 238 ti_sysc_clock_enable(device_t dev) { 239 struct clk_list *clkp, *clkp_tmp; 240 struct ti_sysc_softc *sc = device_get_softc(dev); 241 int err; 242 243 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) { 244 err = clk_enable(clkp->clk); 245 246 if (err) { 247 DPRINTF(sc->dev, "clk_enable %s failed %d\n", 248 clk_get_name(clkp->clk), err); 249 break; 250 } 251 } 252 return (err); 253 } 254 255 int 256 ti_sysc_clock_disable(device_t dev) { 257 struct clk_list *clkp, *clkp_tmp; 258 struct ti_sysc_softc *sc = device_get_softc(dev); 259 int err = 0; 260 261 TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) { 262 err = clk_disable(clkp->clk); 263 264 if (err) { 265 DPRINTF(sc->dev, "clk_enable %s failed %d\n", 266 clk_get_name(clkp->clk), err); 267 break; 268 } 269 } 270 return (err); 271 } 272 273 static int 274 parse_regfields(struct ti_sysc_softc *sc) { 275 phandle_t node; 276 uint32_t parent_address_cells; 277 uint32_t parent_size_cells; 278 cell_t *reg; 279 ssize_t nreg; 280 int err, k, reg_i, prop_idx; 281 uint32_t idx; 282 283 node = ofw_bus_get_node(sc->dev); 284 285 /* Get parents address and size properties */ 286 err = OF_searchencprop(OF_parent(node), "#address-cells", 287 &parent_address_cells, sizeof(parent_address_cells)); 288 if (err == -1) 289 return (ENXIO); 290 if (!(parent_address_cells == 1 || parent_address_cells == 2)) { 291 DPRINTF(sc->dev, "Expect parent #address-cells=[1||2]\n"); 292 return (ENXIO); 293 } 294 295 err = OF_searchencprop(OF_parent(node), "#size-cells", 296 &parent_size_cells, sizeof(parent_size_cells)); 297 if (err == -1) 298 return (ENXIO); 299 300 if (!(parent_size_cells == 1 || parent_size_cells == 2)) { 301 DPRINTF(sc->dev, "Expect parent #size-cells = [1||2]\n"); 302 return (ENXIO); 303 } 304 305 /* Grab the content of reg properties */ 306 nreg = OF_getproplen(node, "reg"); 307 if (nreg <= 0) 308 return (ENXIO); 309 310 reg = malloc(nreg, M_DEVBUF, M_WAITOK); 311 OF_getencprop(node, "reg", reg, nreg); 312 313 /* Make sure address & size are 0 */ 314 for (idx = 0; idx < REG_MAX; idx++) { 315 sc->reg[idx].address = 0; 316 sc->reg[idx].size = 0; 317 } 318 319 /* Loop through reg-names and figure out which reg-name corresponds to 320 * index populate the values into the reg array. 321 */ 322 for (idx = 0, reg_i = 0; idx < REG_MAX && reg_i < nreg; idx++) { 323 err = ofw_bus_find_string_index(node, "reg-names", 324 reg_names[idx], &prop_idx); 325 if (err != 0) 326 continue; 327 328 for (k = 0; k < parent_address_cells; k++) { 329 sc->reg[prop_idx].address <<= 32; 330 sc->reg[prop_idx].address |= reg[reg_i++]; 331 } 332 333 for (k = 0; k < parent_size_cells; k++) { 334 sc->reg[prop_idx].size <<= 32; 335 sc->reg[prop_idx].size |= reg[reg_i++]; 336 } 337 338 if (sc->sc.nranges == 0) 339 sc->offset_reg[prop_idx] = sc->reg[prop_idx].address; 340 else 341 sc->offset_reg[prop_idx] = sc->reg[prop_idx].address - 342 sc->sc.ranges[REG_REV].host; 343 344 DPRINTF(sc->dev, "reg[%s] address %#jx size %#jx\n", 345 reg_names[idx], 346 sc->reg[prop_idx].address, 347 sc->reg[prop_idx].size); 348 } 349 free(reg, M_DEVBUF); 350 return (0); 351 } 352 353 static void 354 parse_idle(struct ti_sysc_softc *sc, const char *name, uint32_t *idle) { 355 phandle_t node; 356 cell_t value[SYSC_IDLE_MAX]; 357 int len, no, i; 358 359 node = ofw_bus_get_node(sc->dev); 360 361 if (!OF_hasprop(node, name)) { 362 return; 363 } 364 365 len = OF_getproplen(node, name); 366 no = len / sizeof(cell_t); 367 if (no >= SYSC_IDLE_MAX) { 368 DPRINTF(sc->dev, "Limit %s\n", name); 369 no = SYSC_IDLE_MAX-1; 370 len = no * sizeof(cell_t); 371 } 372 373 OF_getencprop(node, name, value, len); 374 for (i = 0; i < no; i++) { 375 idle[i] = value[i]; 376 #if DEBUG_SYSC 377 DPRINTF(sc->dev, "%s[%d] = %d ", 378 name, i, value[i]); 379 switch(value[i]) { 380 case SYSC_IDLE_FORCE: 381 DPRINTF(sc->dev, "SYSC_IDLE_FORCE\n"); 382 break; 383 case SYSC_IDLE_NO: 384 DPRINTF(sc->dev, "SYSC_IDLE_NO\n"); 385 break; 386 case SYSC_IDLE_SMART: 387 DPRINTF(sc->dev, "SYSC_IDLE_SMART\n"); 388 break; 389 case SYSC_IDLE_SMART_WKUP: 390 DPRINTF(sc->dev, "SYSC_IDLE_SMART_WKUP\n"); 391 break; 392 } 393 #endif 394 } 395 for ( ; i < SYSC_IDLE_MAX; i++) 396 idle[i] = -1; 397 } 398 399 static int 400 ti_sysc_attach_clocks(struct ti_sysc_softc *sc) { 401 clk_t *clk; 402 struct clk_list *clkp; 403 int index, err; 404 405 clk = malloc(sc->num_clocks*sizeof(clk_t), M_DEVBUF, M_WAITOK | M_ZERO); 406 407 /* Check if all clocks can be found */ 408 for (index = 0; index < sc->num_clocks; index++) { 409 err = clk_get_by_ofw_index(sc->dev, 0, index, &clk[index]); 410 411 if (err != 0) { 412 free(clk, M_DEVBUF); 413 return (1); 414 } 415 } 416 417 /* All clocks are found, add to list */ 418 for (index = 0; index < sc->num_clocks; index++) { 419 clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO); 420 clkp->clk = clk[index]; 421 TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next); 422 } 423 424 /* Release the clk array */ 425 free(clk, M_DEVBUF); 426 return (0); 427 } 428 429 static int 430 ti_sysc_simplebus_attach_child(device_t dev) { 431 device_t cdev; 432 phandle_t node, child; 433 struct ti_sysc_softc *sc = device_get_softc(dev); 434 435 node = ofw_bus_get_node(sc->dev); 436 437 for (child = OF_child(node); child > 0; child = OF_peer(child)) { 438 cdev = simplebus_add_device(sc->dev, child, 0, NULL, -1, NULL); 439 if (cdev != NULL) 440 device_probe_and_attach(cdev); 441 } 442 return (0); 443 } 444 445 /* Device interface */ 446 static int 447 ti_sysc_probe(device_t dev) 448 { 449 if (!ofw_bus_status_okay(dev)) 450 return (ENXIO); 451 452 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 453 return (ENXIO); 454 455 device_set_desc(dev, "TI SYSC Interconnect"); 456 457 return (BUS_PROBE_DEFAULT); 458 } 459 460 static int 461 ti_sysc_attach(device_t dev) 462 { 463 struct ti_sysc_softc *sc; 464 phandle_t node; 465 int err; 466 cell_t value; 467 468 sc = device_get_softc(dev); 469 sc->dev = dev; 470 sc->device_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 471 472 node = ofw_bus_get_node(sc->dev); 473 /* ranges - use simplebus */ 474 simplebus_init(sc->dev, node); 475 if (simplebus_fill_ranges(node, &sc->sc) < 0) { 476 DPRINTF(sc->dev, "could not get ranges\n"); 477 return (ENXIO); 478 } 479 480 if (sc->sc.nranges == 0) { 481 DPRINTF(sc->dev, "nranges == 0\n"); 482 return (ENXIO); 483 } 484 485 /* Required field reg & reg-names - assume at least "rev" exists */ 486 err = parse_regfields(sc); 487 if (err) { 488 DPRINTF(sc->dev, "parse_regfields failed %d\n", err); 489 return (ENXIO); 490 } 491 492 /* Optional */ 493 if (OF_hasprop(node, "ti,sysc-mask")) { 494 OF_getencprop(node, "ti,sysc-mask", &value, sizeof(cell_t)); 495 sc->ti_sysc_mask = value; 496 } 497 if (OF_hasprop(node, "ti,syss-mask")) { 498 OF_getencprop(node, "ti,syss-mask", &value, sizeof(cell_t)); 499 sc->ti_syss_mask = value; 500 } 501 if (OF_hasprop(node, "ti,sysc-delay-us")) { 502 OF_getencprop(node, "ti,sysc-delay-us", &value, sizeof(cell_t)); 503 sc->ti_sysc_delay_us = value; 504 } 505 506 DPRINTF(sc->dev, "sysc_mask %x syss_mask %x delay_us %x\n", 507 sc->ti_sysc_mask, sc->ti_syss_mask, sc->ti_sysc_delay_us); 508 509 parse_idle(sc, "ti,sysc-midle", sc->ti_sysc_midle); 510 parse_idle(sc, "ti,sysc-sidle", sc->ti_sysc_sidle); 511 512 if (OF_hasprop(node, "ti,no-reset-on-init")) 513 sc->ti_no_reset_on_init = true; 514 else 515 sc->ti_no_reset_on_init = false; 516 517 if (OF_hasprop(node, "ti,no-idle-on-init")) 518 sc->ti_no_idle_on_init = true; 519 else 520 sc->ti_no_idle_on_init = false; 521 522 if (OF_hasprop(node, "ti,no-idle")) 523 sc->ti_no_idle = true; 524 else 525 sc->ti_no_idle = false; 526 527 DPRINTF(sc->dev, 528 "no-reset-on-init %d, no-idle-on-init %d, no-idle %d\n", 529 sc->ti_no_reset_on_init, 530 sc->ti_no_idle_on_init, 531 sc->ti_no_idle); 532 533 if (OF_hasprop(node, "clocks")) { 534 struct clock_cell_info cell_info; 535 read_clock_cells(sc->dev, &cell_info); 536 free(cell_info.clock_cells, M_DEVBUF); 537 free(cell_info.clock_cells_ncells, M_DEVBUF); 538 539 sc->num_clocks = cell_info.num_real_clocks; 540 TAILQ_INIT(&sc->clk_list); 541 542 err = ti_sysc_attach_clocks(sc); 543 if (err) { 544 DPRINTF(sc->dev, "Failed to attach clocks\n"); 545 return (bus_generic_attach(sc->dev)); 546 } 547 } 548 549 err = ti_sysc_simplebus_attach_child(sc->dev); 550 if (err) { 551 DPRINTF(sc->dev, "ti_sysc_simplebus_attach_child %d\n", 552 err); 553 return (err); 554 } 555 556 sc->attach_done = true; 557 558 return (bus_generic_attach(sc->dev)); 559 } 560 561 static int 562 ti_sysc_detach(device_t dev) 563 { 564 return (EBUSY); 565 } 566 567 /* Bus interface */ 568 static void 569 ti_sysc_new_pass(device_t dev) 570 { 571 struct ti_sysc_softc *sc; 572 int err; 573 phandle_t node; 574 575 sc = device_get_softc(dev); 576 577 if (sc->attach_done) { 578 bus_generic_new_pass(sc->dev); 579 return; 580 } 581 582 node = ofw_bus_get_node(sc->dev); 583 if (OF_hasprop(node, "clocks")) { 584 err = ti_sysc_attach_clocks(sc); 585 if (err) { 586 DPRINTF(sc->dev, "Failed to attach clocks\n"); 587 return; 588 } 589 } 590 591 err = ti_sysc_simplebus_attach_child(sc->dev); 592 if (err) { 593 DPRINTF(sc->dev, 594 "ti_sysc_simplebus_attach_child failed %d\n", err); 595 return; 596 } 597 sc->attach_done = true; 598 599 bus_generic_attach(sc->dev); 600 } 601 602 static device_method_t ti_sysc_methods[] = { 603 /* Device interface */ 604 DEVMETHOD(device_probe, ti_sysc_probe), 605 DEVMETHOD(device_attach, ti_sysc_attach), 606 DEVMETHOD(device_detach, ti_sysc_detach), 607 608 /* Bus interface */ 609 DEVMETHOD(bus_new_pass, ti_sysc_new_pass), 610 611 DEVMETHOD_END 612 }; 613 614 DEFINE_CLASS_1(ti_sysc, ti_sysc_driver, ti_sysc_methods, 615 sizeof(struct ti_sysc_softc), simplebus_driver); 616 617 EARLY_DRIVER_MODULE(ti_sysc, simplebus, ti_sysc_driver, 0, 0, 618 BUS_PASS_BUS + BUS_PASS_ORDER_FIRST); 619