1 /*- 2 * Copyright (c) 2016 Rubicon Communications, LLC (Netgate) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _TI_SPIREG_H_ 30 #define _TI_SPIREG_H_ 31 32 #define TI_SPI_GCLK 48000000U 33 #define TI_SPI_FIFOSZ 32 34 #define MCSPI_REVISION 0x0 35 #define MCSPI_REVISION_SCHEME_SHIFT 30 36 #define MCSPI_REVISION_SCHEME_MSK 0x3 37 #define MCSPI_REVISION_FUNC_SHIFT 16 38 #define MCSPI_REVISION_FUNC_MSK 0xfff 39 #define MCSPI_REVISION_RTL_SHIFT 11 40 #define MCSPI_REVISION_RTL_MSK 0x1f 41 #define MCSPI_REVISION_MAJOR_SHIFT 8 42 #define MCSPI_REVISION_MAJOR_MSK 0x7 43 #define MCSPI_REVISION_CUSTOM_SHIFT 6 44 #define MCSPI_REVISION_CUSTOM_MSK 0x3 45 #define MCSPI_REVISION_MINOR_SHIFT 0 46 #define MCSPI_REVISION_MINOR_MSK 0x3f 47 #define MCSPI_SYSCONFIG 0x110 48 #define MCSPI_SYSCONFIG_SOFTRESET (1 << 1) 49 #define MCSPI_SYSSTATUS 0x114 50 #define MCSPI_SYSSTATUS_RESETDONE (1 << 0) 51 #define MCSPI_MODULCTRL 0x128 52 #define MCSPI_MODULCTRL_SLAVE (1 << 2) 53 #define MCSPI_MODULCTRL_SINGLE (1 << 0) 54 #define MCSPI_IRQSTATUS 0x118 55 #define MCSPI_IRQENABLE 0x11c 56 #define MCSPI_IRQ_EOW (1 << 17) 57 #define MCSPI_IRQ_RX0_OVERFLOW (1 << 3) 58 #define MCSPI_IRQ_RX0_FULL (1 << 2) 59 #define MCSPI_IRQ_TX0_UNDERFLOW (1 << 1) 60 #define MCSPI_IRQ_TX0_EMPTY (1 << 0) 61 #define MCSPI_CONF_CH(_c) (0x12c + 0x14 * (_c)) 62 #define MCSPI_CONF_CLKG (1 << 29) 63 #define MCSPI_CONF_FFER (1 << 28) 64 #define MCSPI_CONF_FFEW (1 << 27) 65 #define MCSPI_CONF_SBPOL (1 << 24) 66 #define MCSPI_CONF_SBE (1 << 23) 67 #define MCSPI_CONF_FORCE (1 << 20) 68 #define MCSPI_CONF_TURBO (1 << 19) 69 #define MCSPI_CONF_IS (1 << 18) 70 #define MCSPI_CONF_DPE1 (1 << 17) 71 #define MCSPI_CONF_DPE0 (1 << 16) 72 #define MCSPI_CONF_DMAR (1 << 15) 73 #define MCSPI_CONF_DMAW (1 << 14) 74 #define MCSPI_CONF_WL_MSK 0x1f 75 #define MCSPI_CONF_WL_SHIFT 7 76 #define MCSPI_CONF_WL8BITS (7 << MCSPI_CONF_WL_SHIFT) 77 #define MCSPI_CONF_EPOL (1 << 6) 78 #define MCSPI_CONF_CLK_MSK 0xf 79 #define MCSPI_CONF_CLK_SHIFT 2 80 #define MCSPI_CONF_POL (1 << 1) 81 #define MCSPI_CONF_PHA (1 << 0) 82 #define MCSPI_STAT_CH(_c) (0x130 + 0x14 * (_c)) 83 #define MCSPI_STAT_TXFFF (1 << 4) 84 #define MCSPI_STAT_TXS (1 << 1) 85 #define MCSPI_STAT_RXS (1 << 0) 86 #define MCSPI_CTRL_CH(_c) (0x134 + 0x14 * (_c)) 87 #define MCSPI_EXTCLK_MSK 0xfff 88 #define MCSPI_CTRL_EXTCLK_MSK 0xff 89 #define MCSPI_CTRL_EXTCLK_SHIFT 8 90 #define MCSPI_CTRL_ENABLE (1 << 0) 91 #define MCSPI_TX_CH(_c) (0x138 + 0x14 * (_c)) 92 #define MCSPI_RX_CH(_c) (0x13c + 0x14 * (_c)) 93 #define MCSPI_XFERLEVEL 0x17c 94 #define MCSPI_XFERLEVEL_AFL(_a) (((_a) >> 8) & 0xff) 95 #define MCSPI_XFERLEVEL_AEL(_a) (((_a) >> 0) & 0xff) 96 97 #endif /* _TI_SPIREG_H_ */ 98