1 /*- 2 * Copyright (c) 2016 Rubicon Communications, LLC (Netgate) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/rman.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/sysctl.h> 40 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 #include <machine/intr.h> 44 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <dev/spibus/spi.h> 49 #include <dev/spibus/spibusvar.h> 50 51 #include <arm/ti/ti_prcm.h> 52 #include <arm/ti/ti_hwmods.h> 53 #include <arm/ti/ti_spireg.h> 54 #include <arm/ti/ti_spivar.h> 55 56 #include "spibus_if.h" 57 58 static void ti_spi_intr(void *); 59 static int ti_spi_detach(device_t); 60 61 #undef TI_SPI_DEBUG 62 #ifdef TI_SPI_DEBUG 63 #define IRQSTATUSBITS \ 64 "\020\1TX0_EMPTY\2TX0_UNDERFLOW\3RX0_FULL\4RX0_OVERFLOW" \ 65 "\5TX1_EMPTY\6TX1_UNDERFLOW\7RX1_FULL\11TX2_EMPTY" \ 66 "\12TX1_UNDERFLOW\13RX2_FULL\15TX3_EMPTY\16TX3_UNDERFLOW" \ 67 "\17RX3_FULL\22EOW" 68 #define CONFBITS \ 69 "\020\1PHA\2POL\7EPOL\17DMAW\20DMAR\21DPE0\22DPE1\23IS" \ 70 "\24TURBO\25FORCE\30SBE\31SBPOL\34FFEW\35FFER\36CLKG" 71 #define STATBITS \ 72 "\020\1RXS\2TXS\3EOT\4TXFFE\5TXFFF\6RXFFE\7RXFFFF" 73 #define MODULCTRLBITS \ 74 "\020\1SINGLE\2NOSPIEN\3SLAVE\4SYST\10MOA\11FDAA" 75 #define CTRLBITS \ 76 "\020\1ENABLED" 77 78 static void 79 ti_spi_printr(device_t dev) 80 { 81 int clk, conf, ctrl, div, i, j, wl; 82 struct ti_spi_softc *sc; 83 uint32_t reg; 84 85 sc = device_get_softc(dev); 86 reg = TI_SPI_READ(sc, MCSPI_SYSCONFIG); 87 device_printf(dev, "SYSCONFIG: %#x\n", reg); 88 reg = TI_SPI_READ(sc, MCSPI_SYSSTATUS); 89 device_printf(dev, "SYSSTATUS: %#x\n", reg); 90 reg = TI_SPI_READ(sc, MCSPI_IRQSTATUS); 91 device_printf(dev, "IRQSTATUS: 0x%b\n", reg, IRQSTATUSBITS); 92 reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); 93 device_printf(dev, "IRQENABLE: 0x%b\n", reg, IRQSTATUSBITS); 94 reg = TI_SPI_READ(sc, MCSPI_MODULCTRL); 95 device_printf(dev, "MODULCTRL: 0x%b\n", reg, MODULCTRLBITS); 96 for (i = 0; i < sc->sc_numcs; i++) { 97 ctrl = TI_SPI_READ(sc, MCSPI_CTRL_CH(i)); 98 conf = TI_SPI_READ(sc, MCSPI_CONF_CH(i)); 99 device_printf(dev, "CH%dCONF: 0x%b\n", i, conf, CONFBITS); 100 if (conf & MCSPI_CONF_CLKG) { 101 div = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK; 102 div |= ((ctrl >> MCSPI_CTRL_EXTCLK_SHIFT) & MCSPI_CTRL_EXTCLK_MSK) << 4; 103 } else { 104 div = 1; 105 j = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK; 106 while (j-- > 0) 107 div <<= 1; 108 } 109 clk = TI_SPI_GCLK / div; 110 wl = ((conf >> MCSPI_CONF_WL_SHIFT) & MCSPI_CONF_WL_MSK) + 1; 111 device_printf(dev, "wordlen: %-2d clock: %d\n", wl, clk); 112 reg = TI_SPI_READ(sc, MCSPI_STAT_CH(i)); 113 device_printf(dev, "CH%dSTAT: 0x%b\n", i, reg, STATBITS); 114 device_printf(dev, "CH%dCTRL: 0x%b\n", i, ctrl, CTRLBITS); 115 } 116 reg = TI_SPI_READ(sc, MCSPI_XFERLEVEL); 117 device_printf(dev, "XFERLEVEL: %#x\n", reg); 118 } 119 #endif 120 121 static void 122 ti_spi_set_clock(struct ti_spi_softc *sc, int ch, int freq) 123 { 124 uint32_t clkdiv, conf, div, extclk, reg; 125 126 clkdiv = TI_SPI_GCLK / freq; 127 if (clkdiv > MCSPI_EXTCLK_MSK) { 128 extclk = 0; 129 clkdiv = 0; 130 div = 1; 131 while (TI_SPI_GCLK / div > freq && clkdiv <= 0xf) { 132 clkdiv++; 133 div <<= 1; 134 } 135 conf = clkdiv << MCSPI_CONF_CLK_SHIFT; 136 } else { 137 extclk = clkdiv >> 4; 138 clkdiv &= MCSPI_CONF_CLK_MSK; 139 conf = MCSPI_CONF_CLKG | clkdiv << MCSPI_CONF_CLK_SHIFT; 140 } 141 142 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(ch)); 143 reg &= ~(MCSPI_CTRL_EXTCLK_MSK << MCSPI_CTRL_EXTCLK_SHIFT); 144 reg |= extclk << MCSPI_CTRL_EXTCLK_SHIFT; 145 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(ch), reg); 146 147 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(ch)); 148 reg &= ~(MCSPI_CONF_CLKG | MCSPI_CONF_CLK_MSK << MCSPI_CONF_CLK_SHIFT); 149 TI_SPI_WRITE(sc, MCSPI_CONF_CH(ch), reg | conf); 150 } 151 152 static int 153 ti_spi_probe(device_t dev) 154 { 155 156 if (!ofw_bus_status_okay(dev)) 157 return (ENXIO); 158 if (!ofw_bus_is_compatible(dev, "ti,omap4-mcspi")) 159 return (ENXIO); 160 161 device_set_desc(dev, "TI McSPI controller"); 162 163 return (BUS_PROBE_DEFAULT); 164 } 165 166 static int 167 ti_spi_attach(device_t dev) 168 { 169 int clk_id, err, i, rid, timeout; 170 struct ti_spi_softc *sc; 171 uint32_t rev; 172 173 sc = device_get_softc(dev); 174 sc->sc_dev = dev; 175 176 /* 177 * Get the MMCHS device id from FDT. If it's not there use the newbus 178 * unit number (which will work as long as the devices are in order and 179 * none are skipped in the fdt). Note that this is a property we made 180 * up and added in freebsd, it doesn't exist in the published bindings. 181 */ 182 clk_id = ti_hwmods_get_clock(dev); 183 if (clk_id == INVALID_CLK_IDENT) { 184 device_printf(dev, 185 "failed to get clock based on hwmods property\n"); 186 return (EINVAL); 187 } 188 189 /* Activate the McSPI module. */ 190 err = ti_prcm_clk_enable(clk_id); 191 if (err) { 192 device_printf(dev, "Error: failed to activate source clock\n"); 193 return (err); 194 } 195 196 /* Get the number of available channels. */ 197 if ((OF_getencprop(ofw_bus_get_node(dev), "ti,spi-num-cs", 198 &sc->sc_numcs, sizeof(sc->sc_numcs))) <= 0) { 199 sc->sc_numcs = 2; 200 } 201 202 rid = 0; 203 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 204 RF_ACTIVE); 205 if (!sc->sc_mem_res) { 206 device_printf(dev, "cannot allocate memory window\n"); 207 return (ENXIO); 208 } 209 210 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 211 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 212 213 rid = 0; 214 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 215 RF_ACTIVE); 216 if (!sc->sc_irq_res) { 217 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 218 device_printf(dev, "cannot allocate interrupt\n"); 219 return (ENXIO); 220 } 221 222 /* Hook up our interrupt handler. */ 223 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 224 NULL, ti_spi_intr, sc, &sc->sc_intrhand)) { 225 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 226 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 227 device_printf(dev, "cannot setup the interrupt handler\n"); 228 return (ENXIO); 229 } 230 231 mtx_init(&sc->sc_mtx, "ti_spi", NULL, MTX_DEF); 232 233 /* Issue a softreset to the controller */ 234 TI_SPI_WRITE(sc, MCSPI_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET); 235 timeout = 1000; 236 while (!(TI_SPI_READ(sc, MCSPI_SYSSTATUS) & 237 MCSPI_SYSSTATUS_RESETDONE)) { 238 if (--timeout == 0) { 239 device_printf(dev, 240 "Error: Controller reset operation timed out\n"); 241 ti_spi_detach(dev); 242 return (ENXIO); 243 } 244 DELAY(100); 245 } 246 247 /* Print the McSPI module revision. */ 248 rev = TI_SPI_READ(sc, MCSPI_REVISION); 249 device_printf(dev, 250 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n", 251 (rev >> MCSPI_REVISION_SCHEME_SHIFT) & MCSPI_REVISION_SCHEME_MSK, 252 (rev >> MCSPI_REVISION_FUNC_SHIFT) & MCSPI_REVISION_FUNC_MSK, 253 (rev >> MCSPI_REVISION_RTL_SHIFT) & MCSPI_REVISION_RTL_MSK, 254 (rev >> MCSPI_REVISION_MAJOR_SHIFT) & MCSPI_REVISION_MAJOR_MSK, 255 (rev >> MCSPI_REVISION_MINOR_SHIFT) & MCSPI_REVISION_MINOR_MSK, 256 (rev >> MCSPI_REVISION_CUSTOM_SHIFT) & MCSPI_REVISION_CUSTOM_MSK); 257 258 /* Set Master mode, single channel. */ 259 TI_SPI_WRITE(sc, MCSPI_MODULCTRL, MCSPI_MODULCTRL_SINGLE); 260 261 /* Clear pending interrupts and disable interrupts. */ 262 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, 0x0); 263 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xffff); 264 265 for (i = 0; i < sc->sc_numcs; i++) { 266 /* 267 * Default to SPI mode 0, CS active low, 8 bits word length and 268 * 500kHz clock. 269 */ 270 TI_SPI_WRITE(sc, MCSPI_CONF_CH(i), 271 MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | 272 (8 - 1) << MCSPI_CONF_WL_SHIFT); 273 /* Set initial clock - 500kHz. */ 274 ti_spi_set_clock(sc, i, 500000); 275 } 276 277 #ifdef TI_SPI_DEBUG 278 ti_spi_printr(dev); 279 #endif 280 281 device_add_child(dev, "spibus", -1); 282 283 return (bus_generic_attach(dev)); 284 } 285 286 static int 287 ti_spi_detach(device_t dev) 288 { 289 struct ti_spi_softc *sc; 290 291 sc = device_get_softc(dev); 292 293 /* Clear pending interrupts and disable interrupts. */ 294 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, 0); 295 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xffff); 296 297 /* Reset controller. */ 298 TI_SPI_WRITE(sc, MCSPI_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET); 299 300 bus_generic_detach(dev); 301 302 mtx_destroy(&sc->sc_mtx); 303 if (sc->sc_intrhand) 304 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 305 if (sc->sc_irq_res) 306 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 307 if (sc->sc_mem_res) 308 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 309 310 return (0); 311 } 312 313 static int 314 ti_spi_fill_fifo(struct ti_spi_softc *sc) 315 { 316 int bytes, timeout; 317 struct spi_command *cmd; 318 uint32_t written; 319 uint8_t *data; 320 321 cmd = sc->sc_cmd; 322 bytes = min(sc->sc_len - sc->sc_written, sc->sc_fifolvl); 323 while (bytes-- > 0) { 324 data = (uint8_t *)cmd->tx_cmd; 325 written = sc->sc_written++; 326 if (written >= cmd->tx_cmd_sz) { 327 data = (uint8_t *)cmd->tx_data; 328 written -= cmd->tx_cmd_sz; 329 } 330 if (sc->sc_fifolvl == 1) { 331 /* FIFO disabled. */ 332 timeout = 1000; 333 while (--timeout > 0 && (TI_SPI_READ(sc, 334 MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_TXS) == 0) { 335 DELAY(100); 336 } 337 if (timeout == 0) 338 return (-1); 339 } 340 TI_SPI_WRITE(sc, MCSPI_TX_CH(sc->sc_cs), data[written]); 341 } 342 343 return (0); 344 } 345 346 static int 347 ti_spi_drain_fifo(struct ti_spi_softc *sc) 348 { 349 int bytes, timeout; 350 struct spi_command *cmd; 351 uint32_t read; 352 uint8_t *data; 353 354 cmd = sc->sc_cmd; 355 bytes = min(sc->sc_len - sc->sc_read, sc->sc_fifolvl); 356 while (bytes-- > 0) { 357 data = (uint8_t *)cmd->rx_cmd; 358 read = sc->sc_read++; 359 if (read >= cmd->rx_cmd_sz) { 360 data = (uint8_t *)cmd->rx_data; 361 read -= cmd->rx_cmd_sz; 362 } 363 if (sc->sc_fifolvl == 1) { 364 /* FIFO disabled. */ 365 timeout = 1000; 366 while (--timeout > 0 && (TI_SPI_READ(sc, 367 MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_RXS) == 0) { 368 DELAY(100); 369 } 370 if (timeout == 0) 371 return (-1); 372 } 373 data[read] = TI_SPI_READ(sc, MCSPI_RX_CH(sc->sc_cs)); 374 } 375 376 return (0); 377 } 378 379 static void 380 ti_spi_intr(void *arg) 381 { 382 int eow; 383 struct ti_spi_softc *sc; 384 uint32_t status; 385 386 eow = 0; 387 sc = (struct ti_spi_softc *)arg; 388 TI_SPI_LOCK(sc); 389 status = TI_SPI_READ(sc, MCSPI_IRQSTATUS); 390 391 /* 392 * No new TX_empty or RX_full event will be asserted while the CPU has 393 * not performed the number of writes or reads defined by 394 * MCSPI_XFERLEVEL[AEL] and MCSPI_XFERLEVEL[AFL]. It is responsibility 395 * of CPU perform the right number of writes and reads. 396 */ 397 if (status & MCSPI_IRQ_TX0_EMPTY) 398 ti_spi_fill_fifo(sc); 399 if (status & MCSPI_IRQ_RX0_FULL) 400 ti_spi_drain_fifo(sc); 401 402 if (status & MCSPI_IRQ_EOW) 403 eow = 1; 404 405 /* Clear interrupt status. */ 406 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, status); 407 408 /* Check for end of transfer. */ 409 if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) { 410 sc->sc_flags |= TI_SPI_DONE; 411 wakeup(sc->sc_dev); 412 } 413 414 TI_SPI_UNLOCK(sc); 415 } 416 417 static int 418 ti_spi_pio_transfer(struct ti_spi_softc *sc) 419 { 420 421 while (sc->sc_len - sc->sc_written > 0) { 422 if (ti_spi_fill_fifo(sc) == -1) 423 return (EIO); 424 if (ti_spi_drain_fifo(sc) == -1) 425 return (EIO); 426 } 427 428 return (0); 429 } 430 431 static int 432 ti_spi_gcd(int a, int b) 433 { 434 int m; 435 436 while ((m = a % b) != 0) { 437 a = b; 438 b = m; 439 } 440 441 return (b); 442 } 443 444 static int 445 ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 446 { 447 int err; 448 struct ti_spi_softc *sc; 449 uint32_t reg, cs; 450 451 sc = device_get_softc(dev); 452 453 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, 454 ("TX/RX command sizes should be equal")); 455 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, 456 ("TX/RX data sizes should be equal")); 457 458 /* Get the proper chip select for this child. */ 459 spibus_get_cs(child, &cs); 460 461 cs &= ~SPIBUS_CS_HIGH; 462 463 if (cs > sc->sc_numcs) { 464 device_printf(dev, "Invalid chip select %d requested by %s\n", 465 cs, device_get_nameunit(child)); 466 return (EINVAL); 467 } 468 469 TI_SPI_LOCK(sc); 470 471 /* If the controller is in use wait until it is available. */ 472 while (sc->sc_flags & TI_SPI_BUSY) 473 mtx_sleep(dev, &sc->sc_mtx, 0, "ti_spi", 0); 474 475 /* Now we have control over SPI controller. */ 476 sc->sc_flags = TI_SPI_BUSY; 477 478 /* Save the SPI command data. */ 479 sc->sc_cs = cs; 480 sc->sc_cmd = cmd; 481 sc->sc_read = 0; 482 sc->sc_written = 0; 483 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; 484 sc->sc_fifolvl = ti_spi_gcd(sc->sc_len, TI_SPI_FIFOSZ); 485 if (sc->sc_fifolvl < 2 || sc->sc_len > 0xffff) 486 sc->sc_fifolvl = 1; /* FIFO disabled. */ 487 /* Disable FIFO for now. */ 488 sc->sc_fifolvl = 1; 489 490 /* Use a safe clock - 500kHz. */ 491 ti_spi_set_clock(sc, sc->sc_cs, 500000); 492 493 /* Disable the FIFO. */ 494 TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0); 495 496 /* 8 bits word, d0 miso, d1 mosi, mode 0 and CS active low. */ 497 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); 498 reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW | MCSPI_CONF_SBPOL | 499 MCSPI_CONF_SBE | MCSPI_CONF_TURBO | MCSPI_CONF_IS | 500 MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR | 501 MCSPI_CONF_DMAW | MCSPI_CONF_EPOL); 502 reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS; 503 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); 504 505 #if 0 506 /* Enable channel interrupts. */ 507 reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); 508 reg |= 0xf; 509 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg); 510 #endif 511 512 /* Start the transfer. */ 513 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs)); 514 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg | MCSPI_CTRL_ENABLE); 515 516 /* Force CS on. */ 517 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); 518 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg |= MCSPI_CONF_FORCE); 519 520 err = 0; 521 if (sc->sc_fifolvl == 1) 522 err = ti_spi_pio_transfer(sc); 523 524 /* Force CS off. */ 525 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); 526 reg &= ~MCSPI_CONF_FORCE; 527 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); 528 529 /* Disable IRQs. */ 530 reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); 531 reg &= ~0xf; 532 TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg); 533 TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xf); 534 535 /* Disable the SPI channel. */ 536 reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs)); 537 reg &= ~MCSPI_CTRL_ENABLE; 538 TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg); 539 540 /* Disable FIFO. */ 541 reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); 542 reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW); 543 TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); 544 545 /* Release the controller and wakeup the next thread waiting for it. */ 546 sc->sc_flags = 0; 547 wakeup_one(dev); 548 TI_SPI_UNLOCK(sc); 549 550 return (err); 551 } 552 553 static phandle_t 554 ti_spi_get_node(device_t bus, device_t dev) 555 { 556 557 /* Share controller node with spibus. */ 558 return (ofw_bus_get_node(bus)); 559 } 560 561 static device_method_t ti_spi_methods[] = { 562 /* Device interface */ 563 DEVMETHOD(device_probe, ti_spi_probe), 564 DEVMETHOD(device_attach, ti_spi_attach), 565 DEVMETHOD(device_detach, ti_spi_detach), 566 567 /* SPI interface */ 568 DEVMETHOD(spibus_transfer, ti_spi_transfer), 569 570 /* ofw_bus interface */ 571 DEVMETHOD(ofw_bus_get_node, ti_spi_get_node), 572 573 DEVMETHOD_END 574 }; 575 576 static devclass_t ti_spi_devclass; 577 578 static driver_t ti_spi_driver = { 579 "spi", 580 ti_spi_methods, 581 sizeof(struct ti_spi_softc), 582 }; 583 584 DRIVER_MODULE(ti_spi, simplebus, ti_spi_driver, ti_spi_devclass, 0, 0); 585