1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 5 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/gpio.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/resource.h> 41 #include <sys/rman.h> 42 #include <sys/sysctl.h> 43 #include <sys/taskqueue.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 47 #include <arm/ti/ti_cpuid.h> 48 #include <arm/ti/ti_sysc.h> 49 #include "gpio_if.h" 50 51 #include <dev/extres/clk/clk.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include <dev/mmc/bridge.h> 56 #include <dev/mmc/mmcreg.h> 57 #include <dev/mmc/mmcbrvar.h> 58 59 #include <dev/sdhci/sdhci.h> 60 #include <dev/sdhci/sdhci_fdt_gpio.h> 61 #include "sdhci_if.h" 62 63 #include <machine/bus.h> 64 #include <machine/resource.h> 65 #include <machine/intr.h> 66 67 68 #include "opt_mmccam.h" 69 70 struct ti_sdhci_softc { 71 device_t dev; 72 struct sdhci_fdt_gpio * gpio; 73 struct resource * mem_res; 74 struct resource * irq_res; 75 void * intr_cookie; 76 struct sdhci_slot slot; 77 uint32_t mmchs_reg_off; 78 uint32_t sdhci_reg_off; 79 uint64_t baseclk_hz; 80 uint32_t cmd_and_mode; 81 uint32_t sdhci_clkdiv; 82 boolean_t disable_highspeed; 83 boolean_t force_card_present; 84 boolean_t disable_readonly; 85 }; 86 87 /* 88 * Table of supported FDT compat strings. 89 * 90 * Note that "ti,mmchs" is our own invention, and should be phased out in favor 91 * of the documented names. 92 * 93 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x. 94 */ 95 static struct ofw_compat_data compat_data[] = { 96 {"ti,am335-sdhci", 1}, 97 {"ti,omap3-hsmmc", 1}, 98 {"ti,omap4-hsmmc", 1}, 99 {"ti,mmchs", 1}, 100 {NULL, 0}, 101 }; 102 103 /* 104 * The MMCHS hardware has a few control and status registers at the beginning of 105 * the device's memory map, followed by the standard sdhci register block. 106 * Different SoCs have the register blocks at different offsets from the 107 * beginning of the device. Define some constants to map out the registers we 108 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far 109 * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs. 110 */ 111 #define OMAP3_MMCHS_REG_OFFSET 0x000 112 #define OMAP4_MMCHS_REG_OFFSET 0x100 113 #define AM335X_MMCHS_REG_OFFSET 0x100 114 #define SDHCI_REG_OFFSET 0x100 115 116 #define MMCHS_SYSCONFIG 0x010 117 #define MMCHS_SYSCONFIG_RESET (1 << 1) 118 #define MMCHS_SYSSTATUS 0x014 119 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0) 120 #define MMCHS_CON 0x02C 121 #define MMCHS_CON_DW8 (1 << 5) 122 #define MMCHS_CON_DVAL_8_4MS (3 << 9) 123 #define MMCHS_CON_OD (1 << 0) 124 #define MMCHS_SYSCTL 0x12C 125 #define MMCHS_SYSCTL_CLKD_MASK 0x3FF 126 #define MMCHS_SYSCTL_CLKD_SHIFT 6 127 #define MMCHS_SD_CAPA 0x140 128 #define MMCHS_SD_CAPA_VS18 (1 << 26) 129 #define MMCHS_SD_CAPA_VS30 (1 << 25) 130 #define MMCHS_SD_CAPA_VS33 (1 << 24) 131 132 /* Forward declarations, CAM-relataed */ 133 // static void ti_sdhci_cam_poll(struct cam_sim *); 134 // static void ti_sdhci_cam_action(struct cam_sim *, union ccb *); 135 // static int ti_sdhci_cam_settran_settings(struct ti_sdhci_softc *sc, union ccb *); 136 137 static inline uint32_t 138 ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off) 139 { 140 141 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); 142 } 143 144 static inline void 145 ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 146 { 147 148 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); 149 } 150 151 static inline uint32_t 152 RD4(struct ti_sdhci_softc *sc, bus_size_t off) 153 { 154 155 return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off)); 156 } 157 158 static inline void 159 WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 160 { 161 162 bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val); 163 } 164 165 static uint8_t 166 ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 167 { 168 struct ti_sdhci_softc *sc = device_get_softc(dev); 169 170 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 171 } 172 173 static uint16_t 174 ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 175 { 176 struct ti_sdhci_softc *sc = device_get_softc(dev); 177 uint32_t clkdiv, val32; 178 179 /* 180 * The MMCHS hardware has a non-standard interpretation of the sdclock 181 * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6) 182 * but doesn't split them into low:high fields. Instead they're a 183 * single number in the range 0..1023 and the number is exactly the 184 * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI 185 * driver code expects a v2.0 or v3.0 divisor. The shifting and masking 186 * here extracts the MMCHS representation from the hardware word, cleans 187 * those bits out, applies the 2N adjustment, and plugs the result into 188 * the bit positions for the 2.0 or 3.0 divisor in the returned register 189 * value. The ti_sdhci_write_2() routine performs the opposite 190 * transformation when the SDHCI driver writes to the register. 191 */ 192 if (off == SDHCI_CLOCK_CONTROL) { 193 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 194 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) & 195 MMCHS_SYSCTL_CLKD_MASK) / 2; 196 val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT); 197 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 198 if (slot->version >= SDHCI_SPEC_300) 199 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) & 200 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT; 201 return (val32 & 0xffff); 202 } 203 204 /* 205 * Standard 32-bit handling of command and transfer mode. 206 */ 207 if (off == SDHCI_TRANSFER_MODE) { 208 return (sc->cmd_and_mode >> 16); 209 } else if (off == SDHCI_COMMAND_FLAGS) { 210 return (sc->cmd_and_mode & 0x0000ffff); 211 } 212 213 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 214 } 215 216 static uint32_t 217 ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 218 { 219 struct ti_sdhci_softc *sc = device_get_softc(dev); 220 uint32_t val32; 221 222 val32 = RD4(sc, off); 223 224 /* 225 * If we need to disallow highspeed mode due to the OMAP4 erratum, strip 226 * that flag from the returned capabilities. 227 */ 228 if (off == SDHCI_CAPABILITIES && sc->disable_highspeed) 229 val32 &= ~SDHCI_CAN_DO_HISPD; 230 231 /* 232 * Force the card-present state if necessary. 233 */ 234 if (off == SDHCI_PRESENT_STATE && sc->force_card_present) 235 val32 |= SDHCI_CARD_PRESENT; 236 237 return (val32); 238 } 239 240 static void 241 ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 242 uint32_t *data, bus_size_t count) 243 { 244 struct ti_sdhci_softc *sc = device_get_softc(dev); 245 246 bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 247 } 248 249 static void 250 ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 251 uint8_t val) 252 { 253 struct ti_sdhci_softc *sc = device_get_softc(dev); 254 uint32_t val32; 255 256 #ifdef MMCCAM 257 uint32_t newval32; 258 if (off == SDHCI_HOST_CONTROL) { 259 val32 = ti_mmchs_read_4(sc, MMCHS_CON); 260 newval32 = val32; 261 if (val & SDHCI_CTRL_8BITBUS) { 262 device_printf(dev, "Custom-enabling 8-bit bus\n"); 263 newval32 |= MMCHS_CON_DW8; 264 } else { 265 device_printf(dev, "Custom-disabling 8-bit bus\n"); 266 newval32 &= ~MMCHS_CON_DW8; 267 } 268 if (newval32 != val32) 269 ti_mmchs_write_4(sc, MMCHS_CON, newval32); 270 } 271 #endif 272 val32 = RD4(sc, off & ~3); 273 val32 &= ~(0xff << (off & 3) * 8); 274 val32 |= (val << (off & 3) * 8); 275 276 WR4(sc, off & ~3, val32); 277 } 278 279 static void 280 ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 281 uint16_t val) 282 { 283 struct ti_sdhci_softc *sc = device_get_softc(dev); 284 uint32_t clkdiv, val32; 285 286 /* 287 * Translate between the hardware and SDHCI 2.0 or 3.0 representations 288 * of the clock divisor. See the comments in ti_sdhci_read_2() for 289 * details. 290 */ 291 if (off == SDHCI_CLOCK_CONTROL) { 292 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 293 if (slot->version >= SDHCI_SPEC_300) 294 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) & 295 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; 296 clkdiv *= 2; 297 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK) 298 clkdiv = MMCHS_SYSCTL_CLKD_MASK; 299 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 300 val32 &= 0xffff0000; 301 val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK << 302 MMCHS_SYSCTL_CLKD_SHIFT); 303 val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT; 304 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 305 return; 306 } 307 308 /* 309 * Standard 32-bit handling of command and transfer mode. 310 */ 311 if (off == SDHCI_TRANSFER_MODE) { 312 sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) | 313 ((uint32_t)val & 0x0000ffff); 314 return; 315 } else if (off == SDHCI_COMMAND_FLAGS) { 316 sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) | 317 ((uint32_t)val << 16); 318 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 319 return; 320 } 321 322 val32 = RD4(sc, off & ~3); 323 val32 &= ~(0xffff << (off & 3) * 8); 324 val32 |= ((val & 0xffff) << (off & 3) * 8); 325 WR4(sc, off & ~3, val32); 326 } 327 328 static void 329 ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 330 uint32_t val) 331 { 332 struct ti_sdhci_softc *sc = device_get_softc(dev); 333 334 WR4(sc, off, val); 335 } 336 337 static void 338 ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 339 uint32_t *data, bus_size_t count) 340 { 341 struct ti_sdhci_softc *sc = device_get_softc(dev); 342 343 bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 344 } 345 346 static void 347 ti_sdhci_intr(void *arg) 348 { 349 struct ti_sdhci_softc *sc = arg; 350 351 sdhci_generic_intr(&sc->slot); 352 } 353 354 static int 355 ti_sdhci_update_ios(device_t brdev, device_t reqdev) 356 { 357 struct ti_sdhci_softc *sc = device_get_softc(brdev); 358 struct sdhci_slot *slot; 359 struct mmc_ios *ios; 360 uint32_t val32, newval32; 361 362 slot = device_get_ivars(reqdev); 363 ios = &slot->host.ios; 364 365 /* 366 * There is an 8-bit-bus bit in the MMCHS control register which, when 367 * set, overrides the 1 vs 4 bit setting in the standard SDHCI 368 * registers. Set that bit first according to whether an 8-bit bus is 369 * requested, then let the standard driver handle everything else. 370 */ 371 val32 = ti_mmchs_read_4(sc, MMCHS_CON); 372 newval32 = val32; 373 374 if (ios->bus_width == bus_width_8) 375 newval32 |= MMCHS_CON_DW8; 376 else 377 newval32 &= ~MMCHS_CON_DW8; 378 379 if (ios->bus_mode == opendrain) 380 newval32 |= MMCHS_CON_OD; 381 else /* if (ios->bus_mode == pushpull) */ 382 newval32 &= ~MMCHS_CON_OD; 383 384 if (newval32 != val32) 385 ti_mmchs_write_4(sc, MMCHS_CON, newval32); 386 387 return (sdhci_generic_update_ios(brdev, reqdev)); 388 } 389 390 static int 391 ti_sdhci_get_ro(device_t brdev, device_t reqdev) 392 { 393 struct ti_sdhci_softc *sc = device_get_softc(brdev); 394 395 if (sc->disable_readonly) 396 return (0); 397 398 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 399 } 400 401 static bool 402 ti_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot) 403 { 404 struct ti_sdhci_softc *sc = device_get_softc(dev); 405 406 return (sdhci_fdt_gpio_get_present(sc->gpio)); 407 } 408 409 static int 410 ti_sdhci_detach(device_t dev) 411 { 412 413 /* sdhci_fdt_gpio_teardown(sc->gpio); */ 414 415 return (EBUSY); 416 } 417 418 static int 419 ti_sdhci_hw_init(device_t dev) 420 { 421 struct ti_sdhci_softc *sc = device_get_softc(dev); 422 uint32_t regval; 423 unsigned long timeout; 424 clk_t mmc_clk; 425 int err; 426 427 /* Enable the controller and interface/functional clocks */ 428 if (ti_sysc_clock_enable(device_get_parent(dev)) != 0) { 429 device_printf(dev, "Error: failed to enable MMC clock\n"); 430 return (ENXIO); 431 } 432 433 /* FIXME: Devicetree dosent have any reference to mmc_clk */ 434 err = clk_get_by_name(dev, "mmc_clk", &mmc_clk); 435 if (err) { 436 device_printf(dev, "Can not find mmc_clk\n"); 437 return (ENXIO); 438 } 439 err = clk_get_freq(mmc_clk, &sc->baseclk_hz); 440 if (err) { 441 device_printf(dev, "Cant get mmc_clk frequency\n"); 442 /* AM335x TRM 8.1.6.8 table 8-24 96MHz @ OPP100 */ 443 sc->baseclk_hz = 96000000; 444 } 445 446 /* Issue a softreset to the controller */ 447 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET); 448 timeout = 1000; 449 while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & 450 MMCHS_SYSSTATUS_RESETDONE)) { 451 if (--timeout == 0) { 452 device_printf(dev, 453 "Error: Controller reset operation timed out\n"); 454 break; 455 } 456 DELAY(100); 457 } 458 459 /* 460 * Reset the command and data state machines and also other aspects of 461 * the controller such as bus clock and power. 462 * 463 * If we read the software reset register too fast after writing it we 464 * can get back a zero that means the reset hasn't started yet rather 465 * than that the reset is complete. Per TI recommendations, work around 466 * it by reading until we see the reset bit asserted, then read until 467 * it's clear. We also set the SDHCI_QUIRK_WAITFOR_RESET_ASSERTED quirk 468 * so that the main sdhci driver uses this same logic in its resets. 469 */ 470 ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL); 471 timeout = 10000; 472 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & 473 SDHCI_RESET_ALL) != SDHCI_RESET_ALL) { 474 if (--timeout == 0) { 475 break; 476 } 477 DELAY(1); 478 } 479 timeout = 10000; 480 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & 481 SDHCI_RESET_ALL)) { 482 if (--timeout == 0) { 483 device_printf(dev, 484 "Error: Software reset operation timed out\n"); 485 break; 486 } 487 DELAY(100); 488 } 489 490 /* 491 * The attach() routine has examined fdt data and set flags in 492 * slot.host.caps to reflect what voltages we can handle. Set those 493 * values in the CAPA register. Empirical testing shows that the 494 * values in this register can be overwritten at any time, but the 495 * manual says that these values should only be set once, "before 496 * initialization" whatever that means, and that they survive a reset. 497 */ 498 regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA); 499 if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE) 500 regval |= MMCHS_SD_CAPA_VS18; 501 if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310)) 502 regval |= MMCHS_SD_CAPA_VS30; 503 ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval); 504 505 /* Set initial host configuration (1-bit, std speed, pwr off). */ 506 ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0); 507 ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0); 508 509 /* Set the initial controller configuration. */ 510 ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS); 511 512 return (0); 513 } 514 515 static int 516 ti_sdhci_attach(device_t dev) 517 { 518 struct ti_sdhci_softc *sc = device_get_softc(dev); 519 int rid, err; 520 pcell_t prop; 521 phandle_t node; 522 523 sc->dev = dev; 524 525 /* 526 * Get the MMCHS device id from FDT. Use rev address to identify the unit. 527 */ 528 node = ofw_bus_get_node(dev); 529 530 /* 531 * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first 532 * device, and only 1p8v on other devices unless an external transceiver 533 * is used. The only way we could know about a transceiver is fdt data. 534 * Note that we have to do this before calling ti_sdhci_hw_init() so 535 * that it can set the right values in the CAPA register. 536 */ 537 sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE; 538 539 if (OF_hasprop(node, "ti,dual-volt")) { 540 sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310; 541 } 542 543 /* 544 * Set the offset from the device's memory start to the MMCHS registers. 545 * Also for OMAP4 disable high speed mode due to erratum ID i626. 546 */ 547 switch (ti_chip()) { 548 #ifdef SOC_OMAP4 549 case CHIP_OMAP_4: 550 sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET; 551 sc->disable_highspeed = true; 552 break; 553 #endif 554 #ifdef SOC_TI_AM335X 555 case CHIP_AM335X: 556 sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET; 557 break; 558 #endif 559 default: 560 panic("Unknown OMAP device\n"); 561 } 562 563 /* 564 * The standard SDHCI registers are at a fixed offset (the same on all 565 * SoCs) beyond the MMCHS registers. 566 */ 567 sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET; 568 569 /* Resource setup. */ 570 rid = 0; 571 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 572 RF_ACTIVE); 573 if (!sc->mem_res) { 574 device_printf(dev, "cannot allocate memory window\n"); 575 err = ENXIO; 576 goto fail; 577 } 578 579 rid = 0; 580 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 581 RF_ACTIVE); 582 if (!sc->irq_res) { 583 device_printf(dev, "cannot allocate interrupt\n"); 584 err = ENXIO; 585 goto fail; 586 } 587 588 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 589 NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) { 590 device_printf(dev, "cannot setup interrupt handler\n"); 591 err = ENXIO; 592 goto fail; 593 } 594 595 /* 596 * Set up handling of card-detect and write-protect gpio lines. 597 * 598 * If there is no write protect info in the fdt data, fall back to the 599 * historical practice of assuming that the card is writable. This 600 * works around bad fdt data from the upstream source. The alternative 601 * would be to trust the sdhci controller's PRESENT_STATE register WP 602 * bit, but it may say write protect is in effect when it's not if the 603 * pinmux setup doesn't route the WP signal into the sdchi block. 604 */ 605 sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot); 606 607 if (!OF_hasprop(node, "wp-gpios") && !OF_hasprop(node, "wp-disable")) 608 sc->disable_readonly = true; 609 610 /* Initialise the MMCHS hardware. */ 611 err = ti_sdhci_hw_init(dev); 612 if (err != 0) { 613 /* err should already contain ENXIO from ti_sdhci_hw_init() */ 614 goto fail; 615 } 616 617 /* 618 * The capabilities register can only express base clock frequencies in 619 * the range of 0-63MHz for a v2.0 controller. Since our clock runs 620 * faster than that, the hardware sets the frequency to zero in the 621 * register. When the register contains zero, the sdhci driver expects 622 * slot.max_clk to already have the right value in it. 623 */ 624 sc->slot.max_clk = sc->baseclk_hz; 625 626 /* 627 * The MMCHS timeout counter is based on the output sdclock. Tell the 628 * sdhci driver to recalculate the timeout clock whenever the output 629 * sdclock frequency changes. 630 */ 631 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 632 633 /* 634 * The MMCHS hardware shifts the 136-bit response data (in violation of 635 * the spec), so tell the sdhci driver not to do the same in software. 636 */ 637 sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE; 638 639 /* 640 * Reset bits are broken, have to wait to see the bits asserted 641 * before waiting to see them de-asserted. 642 */ 643 sc->slot.quirks |= SDHCI_QUIRK_WAITFOR_RESET_ASSERTED; 644 645 /* 646 * The controller waits for busy responses. 647 */ 648 sc->slot.quirks |= SDHCI_QUIRK_WAIT_WHILE_BUSY; 649 650 /* 651 * DMA is not really broken, I just haven't implemented it yet. 652 */ 653 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 654 655 /* 656 * Set up the hardware and go. Note that this sets many of the 657 * slot.host.* fields, so we have to do this before overriding any of 658 * those values based on fdt data, below. 659 */ 660 sdhci_init_slot(dev, &sc->slot, 0); 661 662 /* 663 * The SDHCI controller doesn't realize it, but we can support 8-bit 664 * even though we're not a v3.0 controller. If there's an fdt bus-width 665 * property, honor it. 666 */ 667 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) { 668 sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA | 669 MMC_CAP_8_BIT_DATA); 670 switch (prop) { 671 case 8: 672 sc->slot.host.caps |= MMC_CAP_8_BIT_DATA; 673 /* FALLTHROUGH */ 674 case 4: 675 sc->slot.host.caps |= MMC_CAP_4_BIT_DATA; 676 break; 677 case 1: 678 break; 679 default: 680 device_printf(dev, "Bad bus-width value %u\n", prop); 681 break; 682 } 683 } 684 685 /* 686 * If the slot is flagged with the non-removable property, set our flag 687 * to always force the SDHCI_CARD_PRESENT bit on. 688 */ 689 node = ofw_bus_get_node(dev); 690 if (OF_hasprop(node, "non-removable")) 691 sc->force_card_present = true; 692 693 bus_generic_probe(dev); 694 bus_generic_attach(dev); 695 696 sdhci_start_slot(&sc->slot); 697 return (0); 698 699 fail: 700 if (sc->intr_cookie) 701 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 702 if (sc->irq_res) 703 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 704 if (sc->mem_res) 705 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 706 707 return (err); 708 } 709 710 static int 711 ti_sdhci_probe(device_t dev) 712 { 713 714 if (!ofw_bus_status_okay(dev)) 715 return (ENXIO); 716 717 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 718 device_set_desc(dev, "TI MMCHS (SDHCI 2.0)"); 719 return (BUS_PROBE_DEFAULT); 720 } 721 722 return (ENXIO); 723 } 724 725 static device_method_t ti_sdhci_methods[] = { 726 /* Device interface */ 727 DEVMETHOD(device_probe, ti_sdhci_probe), 728 DEVMETHOD(device_attach, ti_sdhci_attach), 729 DEVMETHOD(device_detach, ti_sdhci_detach), 730 731 /* Bus interface */ 732 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 733 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 734 735 /* MMC bridge interface */ 736 DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios), 737 DEVMETHOD(mmcbr_request, sdhci_generic_request), 738 DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro), 739 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 740 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 741 742 /* SDHCI registers accessors */ 743 DEVMETHOD(sdhci_read_1, ti_sdhci_read_1), 744 DEVMETHOD(sdhci_read_2, ti_sdhci_read_2), 745 DEVMETHOD(sdhci_read_4, ti_sdhci_read_4), 746 DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4), 747 DEVMETHOD(sdhci_write_1, ti_sdhci_write_1), 748 DEVMETHOD(sdhci_write_2, ti_sdhci_write_2), 749 DEVMETHOD(sdhci_write_4, ti_sdhci_write_4), 750 DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4), 751 DEVMETHOD(sdhci_get_card_present, ti_sdhci_get_card_present), 752 753 DEVMETHOD_END 754 }; 755 756 static devclass_t ti_sdhci_devclass; 757 758 static driver_t ti_sdhci_driver = { 759 "sdhci_ti", 760 ti_sdhci_methods, 761 sizeof(struct ti_sdhci_softc), 762 }; 763 764 DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, NULL, 765 NULL); 766 MODULE_DEPEND(sdhci_ti, ti_sysc, 1, 1, 1); 767 SDHCI_DEPEND(sdhci_ti); 768 769 #ifndef MMCCAM 770 MMC_DECLARE_BRIDGE(sdhci_ti); 771 #endif 772