xref: /freebsd/sys/arm/ti/ti_sdhci.c (revision 8d20be1e22095c27faf8fe8b2f0d089739cc742e)
1 /*-
2  * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3  * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  */
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30 
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/gpio.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/resource.h>
39 #include <sys/rman.h>
40 #include <sys/taskqueue.h>
41 
42 #include <machine/bus.h>
43 #include <machine/resource.h>
44 #include <machine/intr.h>
45 
46 #include <dev/fdt/fdt_common.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
49 
50 #include <dev/mmc/bridge.h>
51 #include <dev/mmc/mmcreg.h>
52 #include <dev/mmc/mmcbrvar.h>
53 
54 #include <dev/sdhci/sdhci.h>
55 #include "sdhci_if.h"
56 
57 #include <arm/ti/ti_cpuid.h>
58 #include <arm/ti/ti_prcm.h>
59 #include "gpio_if.h"
60 
61 struct ti_sdhci_softc {
62 	device_t		dev;
63 	device_t		gpio_dev;
64 	struct resource *	mem_res;
65 	struct resource *	irq_res;
66 	void *			intr_cookie;
67 	struct sdhci_slot	slot;
68 	uint32_t		mmchs_device_id;
69 	uint32_t		mmchs_reg_off;
70 	uint32_t		sdhci_reg_off;
71 	uint32_t		baseclk_hz;
72 	uint32_t		wp_gpio_pin;
73 	uint32_t		cmd_and_mode;
74 	uint32_t		sdhci_clkdiv;
75 };
76 
77 /*
78  * The MMCHS hardware has a few control and status registers at the beginning of
79  * the device's memory map, followed by the standard sdhci register block.
80  * Different SoCs have the register blocks at different offsets from the
81  * beginning of the device.  Define some constants to map out the registers we
82  * access, and the various per-SoC offsets.  The SDHCI_REG_OFFSET is how far
83  * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs.
84  */
85 #define	OMAP3_MMCHS_REG_OFFSET		0x000
86 #define	OMAP4_MMCHS_REG_OFFSET		0x100
87 #define	AM335X_MMCHS_REG_OFFSET		0x100
88 #define	SDHCI_REG_OFFSET		0x100
89 
90 #define	MMCHS_SYSCONFIG			0x010
91 #define	  MMCHS_SYSCONFIG_RESET		  (1 << 1)
92 #define	MMCHS_SYSSTATUS			0x014
93 #define	MMCHS_CON			0x02C
94 #define	  MMCHS_CON_DW8			  (1 << 5)
95 #define	  MMCHS_CON_DVAL_8_4MS		  (3 << 9)
96 
97 static inline uint32_t
98 ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off)
99 {
100 
101 	return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off));
102 }
103 
104 static inline void
105 ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
106 {
107 
108 	bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val);
109 }
110 
111 static inline uint32_t
112 RD4(struct ti_sdhci_softc *sc, bus_size_t off)
113 {
114 
115 	return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off));
116 }
117 
118 static inline void
119 WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val)
120 {
121 
122 	bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val);
123 }
124 
125 static uint8_t
126 ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
127 {
128 	struct ti_sdhci_softc *sc = device_get_softc(dev);
129 
130 	return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff);
131 }
132 
133 static uint16_t
134 ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
135 {
136 	struct ti_sdhci_softc *sc = device_get_softc(dev);
137 	uint32_t clkdiv, val32;
138 
139 	/*
140 	 * The MMCHS hardware has a non-standard interpretation of the sdclock
141 	 * divisor bits.  It uses the same bit positions as SDHCI 3.0 (15..6)
142 	 * but doesn't split them into low:high fields.  Instead they're a
143 	 * single number in the range 0..1023 and the number is exactly the
144 	 * clock divisor (with 0 and 1 both meaning divide by 1).  The SDHCI
145 	 * driver code expects a v2.0 divisor (value N is power of two in the
146 	 * range 0..128 and clock is divided by 2N).  The shifting and masking
147 	 * here extracts the MMCHS representation from the hardware word, cleans
148 	 * those bits out, applies the 2N adjustment, and plugs that into the
149 	 * bit positions for the 2.0 divisor in the returned register value. The
150 	 * ti_sdhci_write_2() routine performs the opposite transformation when
151 	 * the SDHCI driver writes to the register.
152 	 */
153 	if (off == SDHCI_CLOCK_CONTROL) {
154 		val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
155 		clkdiv = (val32 >> SDHCI_DIVIDER_HI_SHIFT) & 0xff;
156 		val32 &= ~(0xff << SDHCI_DIVIDER_HI_SHIFT);
157 		val32 |= (clkdiv / 2) << SDHCI_DIVIDER_SHIFT;
158 		return (val32 & 0xffff);
159 	}
160 
161 	/*
162 	 * Standard 32-bit handling of command and transfer mode.
163 	 */
164 	if (off == SDHCI_TRANSFER_MODE) {
165 		return (sc->cmd_and_mode >> 16);
166 	} else if (off == SDHCI_COMMAND_FLAGS) {
167 		return (sc->cmd_and_mode & 0x0000ffff);
168 	}
169 
170 	return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff);
171 }
172 
173 static uint32_t
174 ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
175 {
176 	struct ti_sdhci_softc *sc = device_get_softc(dev);
177 
178 	return (RD4(sc, off));
179 }
180 
181 static void
182 ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
183     uint32_t *data, bus_size_t count)
184 {
185 	struct ti_sdhci_softc *sc = device_get_softc(dev);
186 
187 	bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
188 }
189 
190 static void
191 ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
192     uint8_t val)
193 {
194 	struct ti_sdhci_softc *sc = device_get_softc(dev);
195 	uint32_t val32;
196 
197 	val32 = RD4(sc, off & ~3);
198 	val32 &= ~(0xff << (off & 3) * 8);
199 	val32 |= (val << (off & 3) * 8);
200 
201 	WR4(sc, off & ~3, val32);
202 }
203 
204 static void
205 ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
206     uint16_t val)
207 {
208 	struct ti_sdhci_softc *sc = device_get_softc(dev);
209 	uint32_t clkdiv, val32;
210 
211 	/*
212 	 * Translate between the hardware and SDHCI 2.0 representations of the
213 	 * clock divisor.  See the comments in ti_sdhci_read_2() for details.
214 	 */
215 	if (off == SDHCI_CLOCK_CONTROL) {
216 		clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK;
217 		val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
218 		val32 &= 0xffff0000;
219 		val32 |= val & ~(SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT);
220 		val32 |= (clkdiv * 2) << SDHCI_DIVIDER_HI_SHIFT;
221 		WR4(sc, SDHCI_CLOCK_CONTROL, val32);
222 		return;
223 	}
224 
225 	/*
226 	 * Standard 32-bit handling of command and transfer mode.
227 	 */
228 	if (off == SDHCI_TRANSFER_MODE) {
229 		sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) |
230 		    ((uint32_t)val & 0x0000ffff);
231 		return;
232 	} else if (off == SDHCI_COMMAND_FLAGS) {
233 		sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) |
234 		    ((uint32_t)val << 16);
235 		WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
236 		return;
237 	}
238 
239 	val32 = RD4(sc, off & ~3);
240 	val32 &= ~(0xffff << (off & 3) * 8);
241 	val32 |= ((val & 0xffff) << (off & 3) * 8);
242 	WR4(sc, off & ~3, val32);
243 }
244 
245 static void
246 ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
247     uint32_t val)
248 {
249 	struct ti_sdhci_softc *sc = device_get_softc(dev);
250 
251 	WR4(sc, off, val);
252 }
253 
254 static void
255 ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
256     uint32_t *data, bus_size_t count)
257 {
258 	struct ti_sdhci_softc *sc = device_get_softc(dev);
259 
260 	bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count);
261 }
262 
263 static void
264 ti_sdhci_intr(void *arg)
265 {
266 	struct ti_sdhci_softc *sc = arg;
267 
268 	sdhci_generic_intr(&sc->slot);
269 }
270 
271 static int
272 ti_sdhci_update_ios(device_t brdev, device_t reqdev)
273 {
274 	struct ti_sdhci_softc *sc = device_get_softc(brdev);
275 	struct sdhci_slot *slot;
276 	struct mmc_ios *ios;
277 	uint32_t val32;
278 
279 	slot = device_get_ivars(reqdev);
280 	ios = &slot->host.ios;
281 
282 	/*
283 	 * There is an 8-bit-bus bit in the MMCHS control register which, when
284 	 * set, overrides the 1 vs 4 bit setting in the standard SDHCI
285 	 * registers.  Set that bit first according to whether an 8-bit bus is
286 	 * requested, then let the standard driver handle everything else.
287 	 */
288 	val32 = ti_mmchs_read_4(sc, MMCHS_CON);
289 	if (ios->bus_width == bus_width_8)
290 		ti_mmchs_write_4(sc, MMCHS_CON, val32 | MMCHS_CON_DW8);
291 	else
292 		ti_mmchs_write_4(sc, MMCHS_CON, val32 & ~MMCHS_CON_DW8);
293 
294 	return (sdhci_generic_update_ios(brdev, reqdev));
295 }
296 
297 static int
298 ti_sdhci_get_ro(device_t brdev, device_t reqdev)
299 {
300 	struct ti_sdhci_softc *sc = device_get_softc(brdev);
301 	unsigned int readonly = 0;
302 
303 	/* If a gpio pin is configured, read it. */
304 	if (sc->gpio_dev != NULL) {
305 		GPIO_PIN_GET(sc->gpio_dev, sc->wp_gpio_pin, &readonly);
306 	}
307 
308 	return (readonly);
309 }
310 
311 static int
312 ti_sdhci_detach(device_t dev)
313 {
314 
315 	return (EBUSY);
316 }
317 
318 static void
319 ti_sdhci_hw_init(device_t dev)
320 {
321 	struct ti_sdhci_softc *sc = device_get_softc(dev);
322 	clk_ident_t clk;
323 	unsigned long timeout;
324 
325 	/* Enable the controller and interface/functional clocks */
326 	clk = MMC0_CLK + sc->mmchs_device_id;
327 	if (ti_prcm_clk_enable(clk) != 0) {
328 		device_printf(dev, "Error: failed to enable MMC clock\n");
329 		return;
330 	}
331 
332 	/* Get the frequency of the source clock */
333 	if (ti_prcm_clk_get_source_freq(clk, &sc->baseclk_hz) != 0) {
334 		device_printf(dev, "Error: failed to get source clock freq\n");
335 		return;
336 	}
337 
338 	/* Issue a softreset to the controller */
339 	ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET);
340 	timeout = 1000;
341 	while ((ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & MMCHS_SYSCONFIG_RESET)) {
342 		if (--timeout == 0) {
343 			device_printf(dev, "Error: Controller reset operation timed out\n");
344 			break;
345 		}
346 		DELAY(100);
347 	}
348 
349 	/* Reset both the command and data state machines */
350 	ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL);
351 	timeout = 1000;
352 	while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL)) {
353 		if (--timeout == 0) {
354 			device_printf(dev, "Error: Software reset operation timed out\n");
355 			break;
356 		}
357 		DELAY(100);
358 	}
359 
360 	/* Set initial host configuration (1-bit, std speed, pwr off). */
361 	ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0);
362 	ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0);
363 
364 	/* Set the initial controller configuration. */
365 	ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS);
366 }
367 
368 static int
369 ti_sdhci_attach(device_t dev)
370 {
371 	struct ti_sdhci_softc *sc = device_get_softc(dev);
372 	int rid, err;
373 	pcell_t prop;
374 	phandle_t node;
375 
376 	sc->dev = dev;
377 
378 	/*
379 	 * Get the MMCHS device id from FDT.  If it's not there use the newbus
380 	 * unit number (which will work as long as the devices are in order and
381 	 * none are skipped in the fdt).
382 	 */
383 	node = ofw_bus_get_node(dev);
384 	if ((OF_getprop(node, "mmchs-device-id", &prop, sizeof(prop))) <= 0) {
385 		sc->mmchs_device_id = device_get_unit(dev);
386 		device_printf(dev, "missing mmchs-device-id attribute in FDT, "
387 		    "using unit number (%d)", sc->mmchs_device_id);
388 	} else
389 		sc->mmchs_device_id = fdt32_to_cpu(prop);
390 
391 	/* See if we've got a GPIO-based write detect pin. */
392 	if ((OF_getprop(node, "mmchs-wp-gpio-pin", &prop, sizeof(prop))) <= 0)
393 		sc->wp_gpio_pin = 0xffffffff;
394 	else
395 		sc->wp_gpio_pin = fdt32_to_cpu(prop);
396 
397 	if (sc->wp_gpio_pin != 0xffffffff) {
398 		sc->gpio_dev = devclass_get_device(devclass_find("gpio"), 0);
399 		if (sc->gpio_dev == NULL)
400 			device_printf(dev, "Error: No GPIO device, "
401 			    "Write Protect pin will not function\n");
402 		else
403 			GPIO_PIN_SETFLAGS(sc->gpio_dev, sc->wp_gpio_pin,
404 			                  GPIO_PIN_INPUT);
405 	}
406 
407 	/*
408 	 * Set the offset from the device's memory start to the MMCHS registers.
409 	 *
410 	 * XXX A better way to handle this would be to have separate memory
411 	 * resources for the sdhci registers and the mmchs registers.  That
412 	 * requires changing everyone's DTS files.
413 	 */
414 	if (ti_chip() == CHIP_OMAP_3)
415 		sc->mmchs_reg_off = OMAP3_MMCHS_REG_OFFSET;
416 	else if (ti_chip() == CHIP_OMAP_4)
417 		sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET;
418 	else if (ti_chip() == CHIP_AM335X)
419 		sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET;
420 	else
421 		panic("Unknown OMAP device\n");
422 
423 	/*
424 	 * The standard SDHCI registers are at a fixed offset (the same on all
425 	 * SoCs) beyond the MMCHS registers.
426 	 */
427 	sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET;
428 
429 	/* Resource setup. */
430 	rid = 0;
431 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
432 	    RF_ACTIVE);
433 	if (!sc->mem_res) {
434 		device_printf(dev, "cannot allocate memory window\n");
435 		err = ENXIO;
436 		goto fail;
437 	}
438 
439 	rid = 0;
440 	sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
441 	    RF_ACTIVE);
442 	if (!sc->irq_res) {
443 		device_printf(dev, "cannot allocate interrupt\n");
444 		err = ENXIO;
445 		goto fail;
446 	}
447 
448 	if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
449 	    NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) {
450 		device_printf(dev, "cannot setup interrupt handler\n");
451 		err = ENXIO;
452 		goto fail;
453 	}
454 
455 	/* Initialise the MMCHS hardware. */
456 	ti_sdhci_hw_init(dev);
457 
458 	/*
459 	 * The capabilities register can only express base clock frequencies in
460 	 * the range of 0-63MHz for a v2.0 controller.  Since our clock runs
461 	 * faster than that, the hardware sets the frequency to zero in the
462 	 * register.  When the register contains zero, the sdhci driver expects
463 	 * slot.max_clk to already have the right value in it.
464 	 */
465 	sc->slot.max_clk = sc->baseclk_hz;
466 
467 	/*
468 	 * The MMCHS timeout counter is based on the output sdclock.  Tell the
469 	 * sdhci driver to recalculate the timeout clock whenever the output
470 	 * sdclock frequency changes.
471 	 */
472 	sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
473 
474 	/*
475 	 * The MMCHS hardware shifts the 136-bit response data (in violation of
476 	 * the spec), so tell the sdhci driver not to do the same in software.
477 	 */
478 	sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE;
479 
480 	/*
481 	 * DMA is not really broken, I just haven't implemented it yet.
482 	 */
483 	sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA;
484 
485 	/* Set up the hardware and go. */
486 	sdhci_init_slot(dev, &sc->slot, 0);
487 
488 	/*
489 	 * The SDHCI controller doesn't realize it, but we support 8-bit even
490 	 * though we're not a v3.0 controller.  Advertise the ability.
491 	 */
492 	sc->slot.host.caps |= MMC_CAP_8_BIT_DATA;
493 
494 	bus_generic_probe(dev);
495 	bus_generic_attach(dev);
496 
497 	sdhci_start_slot(&sc->slot);
498 
499 	return (0);
500 
501 fail:
502 	if (sc->intr_cookie)
503 		bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
504 	if (sc->irq_res)
505 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
506 	if (sc->mem_res)
507 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
508 
509 	return (err);
510 }
511 
512 static int
513 ti_sdhci_probe(device_t dev)
514 {
515 
516 	if (!ofw_bus_is_compatible(dev, "ti,mmchs")) {
517 		return (ENXIO);
518 	}
519 
520 	device_set_desc(dev, "TI MMCHS (SDHCI 2.0)");
521 
522 	return (BUS_PROBE_DEFAULT);
523 }
524 
525 static device_method_t ti_sdhci_methods[] = {
526 	/* Device interface */
527 	DEVMETHOD(device_probe,		ti_sdhci_probe),
528 	DEVMETHOD(device_attach,	ti_sdhci_attach),
529 	DEVMETHOD(device_detach,	ti_sdhci_detach),
530 
531 	/* Bus interface */
532 	DEVMETHOD(bus_read_ivar,	sdhci_generic_read_ivar),
533 	DEVMETHOD(bus_write_ivar,	sdhci_generic_write_ivar),
534 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
535 
536 	/* MMC bridge interface */
537 	DEVMETHOD(mmcbr_update_ios,	ti_sdhci_update_ios),
538 	DEVMETHOD(mmcbr_request,	sdhci_generic_request),
539 	DEVMETHOD(mmcbr_get_ro,		ti_sdhci_get_ro),
540 	DEVMETHOD(mmcbr_acquire_host,	sdhci_generic_acquire_host),
541 	DEVMETHOD(mmcbr_release_host,	sdhci_generic_release_host),
542 
543 	/* SDHCI registers accessors */
544 	DEVMETHOD(sdhci_read_1,		ti_sdhci_read_1),
545 	DEVMETHOD(sdhci_read_2,		ti_sdhci_read_2),
546 	DEVMETHOD(sdhci_read_4,		ti_sdhci_read_4),
547 	DEVMETHOD(sdhci_read_multi_4,	ti_sdhci_read_multi_4),
548 	DEVMETHOD(sdhci_write_1,	ti_sdhci_write_1),
549 	DEVMETHOD(sdhci_write_2,	ti_sdhci_write_2),
550 	DEVMETHOD(sdhci_write_4,	ti_sdhci_write_4),
551 	DEVMETHOD(sdhci_write_multi_4,	ti_sdhci_write_multi_4),
552 
553 	DEVMETHOD_END
554 };
555 
556 static devclass_t ti_sdhci_devclass;
557 
558 static driver_t ti_sdhci_driver = {
559 	"sdhci_ti",
560 	ti_sdhci_methods,
561 	sizeof(struct ti_sdhci_softc),
562 };
563 
564 DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, 0, 0);
565 MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1);
566