1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/gpio.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/taskqueue.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 #include <machine/intr.h> 45 46 #include <dev/fdt/fdt_common.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <dev/mmc/bridge.h> 51 #include <dev/mmc/mmcreg.h> 52 #include <dev/mmc/mmcbrvar.h> 53 54 #include <dev/sdhci/sdhci.h> 55 #include "sdhci_if.h" 56 57 #include <arm/ti/ti_cpuid.h> 58 #include <arm/ti/ti_prcm.h> 59 #include "gpio_if.h" 60 61 struct ti_sdhci_softc { 62 device_t dev; 63 device_t gpio_dev; 64 struct resource * mem_res; 65 struct resource * irq_res; 66 void * intr_cookie; 67 struct sdhci_slot slot; 68 uint32_t mmchs_device_id; 69 uint32_t mmchs_reg_off; 70 uint32_t sdhci_reg_off; 71 uint32_t baseclk_hz; 72 uint32_t wp_gpio_pin; 73 uint32_t cmd_and_mode; 74 uint32_t sdhci_clkdiv; 75 }; 76 77 /* 78 * Table of supported FDT compat strings. 79 * 80 * Note that "ti,mmchs" is our own invention, and should be phased out in favor 81 * of the documented names. 82 * 83 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x. 84 */ 85 static struct ofw_compat_data compat_data[] = { 86 {"ti,omap3-hsmmc", 1}, 87 {"ti,omap4-hsmmc", 1}, 88 {"ti,mmchs", 1}, 89 {NULL, 0}, 90 }; 91 92 /* 93 * The MMCHS hardware has a few control and status registers at the beginning of 94 * the device's memory map, followed by the standard sdhci register block. 95 * Different SoCs have the register blocks at different offsets from the 96 * beginning of the device. Define some constants to map out the registers we 97 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far 98 * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs. 99 */ 100 #define OMAP3_MMCHS_REG_OFFSET 0x000 101 #define OMAP4_MMCHS_REG_OFFSET 0x100 102 #define AM335X_MMCHS_REG_OFFSET 0x100 103 #define SDHCI_REG_OFFSET 0x100 104 105 #define MMCHS_SYSCONFIG 0x010 106 #define MMCHS_SYSCONFIG_RESET (1 << 1) 107 #define MMCHS_SYSSTATUS 0x014 108 #define MMCHS_CON 0x02C 109 #define MMCHS_CON_DW8 (1 << 5) 110 #define MMCHS_CON_DVAL_8_4MS (3 << 9) 111 #define MMCHS_SD_CAPA 0x140 112 #define MMCHS_SD_CAPA_VS18 (1 << 26) 113 #define MMCHS_SD_CAPA_VS30 (1 << 25) 114 #define MMCHS_SD_CAPA_VS33 (1 << 24) 115 116 static inline uint32_t 117 ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off) 118 { 119 120 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); 121 } 122 123 static inline void 124 ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 125 { 126 127 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); 128 } 129 130 static inline uint32_t 131 RD4(struct ti_sdhci_softc *sc, bus_size_t off) 132 { 133 134 return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off)); 135 } 136 137 static inline void 138 WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 139 { 140 141 bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val); 142 } 143 144 static uint8_t 145 ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 146 { 147 struct ti_sdhci_softc *sc = device_get_softc(dev); 148 149 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 150 } 151 152 static uint16_t 153 ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 154 { 155 struct ti_sdhci_softc *sc = device_get_softc(dev); 156 uint32_t clkdiv, val32; 157 158 /* 159 * The MMCHS hardware has a non-standard interpretation of the sdclock 160 * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6) 161 * but doesn't split them into low:high fields. Instead they're a 162 * single number in the range 0..1023 and the number is exactly the 163 * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI 164 * driver code expects a v2.0 divisor (value N is power of two in the 165 * range 0..128 and clock is divided by 2N). The shifting and masking 166 * here extracts the MMCHS representation from the hardware word, cleans 167 * those bits out, applies the 2N adjustment, and plugs that into the 168 * bit positions for the 2.0 divisor in the returned register value. The 169 * ti_sdhci_write_2() routine performs the opposite transformation when 170 * the SDHCI driver writes to the register. 171 */ 172 if (off == SDHCI_CLOCK_CONTROL) { 173 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 174 clkdiv = (val32 >> SDHCI_DIVIDER_HI_SHIFT) & 0xff; 175 val32 &= ~(0xff << SDHCI_DIVIDER_HI_SHIFT); 176 val32 |= (clkdiv / 2) << SDHCI_DIVIDER_SHIFT; 177 return (val32 & 0xffff); 178 } 179 180 /* 181 * Standard 32-bit handling of command and transfer mode. 182 */ 183 if (off == SDHCI_TRANSFER_MODE) { 184 return (sc->cmd_and_mode >> 16); 185 } else if (off == SDHCI_COMMAND_FLAGS) { 186 return (sc->cmd_and_mode & 0x0000ffff); 187 } 188 189 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 190 } 191 192 static uint32_t 193 ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 194 { 195 struct ti_sdhci_softc *sc = device_get_softc(dev); 196 197 return (RD4(sc, off)); 198 } 199 200 static void 201 ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 202 uint32_t *data, bus_size_t count) 203 { 204 struct ti_sdhci_softc *sc = device_get_softc(dev); 205 206 bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 207 } 208 209 static void 210 ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 211 uint8_t val) 212 { 213 struct ti_sdhci_softc *sc = device_get_softc(dev); 214 uint32_t val32; 215 216 val32 = RD4(sc, off & ~3); 217 val32 &= ~(0xff << (off & 3) * 8); 218 val32 |= (val << (off & 3) * 8); 219 220 WR4(sc, off & ~3, val32); 221 } 222 223 static void 224 ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 225 uint16_t val) 226 { 227 struct ti_sdhci_softc *sc = device_get_softc(dev); 228 uint32_t clkdiv, val32; 229 230 /* 231 * Translate between the hardware and SDHCI 2.0 representations of the 232 * clock divisor. See the comments in ti_sdhci_read_2() for details. 233 */ 234 if (off == SDHCI_CLOCK_CONTROL) { 235 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 236 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 237 val32 &= 0xffff0000; 238 val32 |= val & ~(SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT); 239 val32 |= (clkdiv * 2) << SDHCI_DIVIDER_HI_SHIFT; 240 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 241 return; 242 } 243 244 /* 245 * Standard 32-bit handling of command and transfer mode. 246 */ 247 if (off == SDHCI_TRANSFER_MODE) { 248 sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) | 249 ((uint32_t)val & 0x0000ffff); 250 return; 251 } else if (off == SDHCI_COMMAND_FLAGS) { 252 sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) | 253 ((uint32_t)val << 16); 254 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 255 return; 256 } 257 258 val32 = RD4(sc, off & ~3); 259 val32 &= ~(0xffff << (off & 3) * 8); 260 val32 |= ((val & 0xffff) << (off & 3) * 8); 261 WR4(sc, off & ~3, val32); 262 } 263 264 static void 265 ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 266 uint32_t val) 267 { 268 struct ti_sdhci_softc *sc = device_get_softc(dev); 269 270 WR4(sc, off, val); 271 } 272 273 static void 274 ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 275 uint32_t *data, bus_size_t count) 276 { 277 struct ti_sdhci_softc *sc = device_get_softc(dev); 278 279 bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 280 } 281 282 static void 283 ti_sdhci_intr(void *arg) 284 { 285 struct ti_sdhci_softc *sc = arg; 286 287 sdhci_generic_intr(&sc->slot); 288 } 289 290 static int 291 ti_sdhci_update_ios(device_t brdev, device_t reqdev) 292 { 293 struct ti_sdhci_softc *sc = device_get_softc(brdev); 294 struct sdhci_slot *slot; 295 struct mmc_ios *ios; 296 uint32_t val32; 297 298 slot = device_get_ivars(reqdev); 299 ios = &slot->host.ios; 300 301 /* 302 * There is an 8-bit-bus bit in the MMCHS control register which, when 303 * set, overrides the 1 vs 4 bit setting in the standard SDHCI 304 * registers. Set that bit first according to whether an 8-bit bus is 305 * requested, then let the standard driver handle everything else. 306 */ 307 val32 = ti_mmchs_read_4(sc, MMCHS_CON); 308 if (ios->bus_width == bus_width_8) 309 ti_mmchs_write_4(sc, MMCHS_CON, val32 | MMCHS_CON_DW8); 310 else 311 ti_mmchs_write_4(sc, MMCHS_CON, val32 & ~MMCHS_CON_DW8); 312 313 return (sdhci_generic_update_ios(brdev, reqdev)); 314 } 315 316 static int 317 ti_sdhci_get_ro(device_t brdev, device_t reqdev) 318 { 319 struct ti_sdhci_softc *sc = device_get_softc(brdev); 320 unsigned int readonly = 0; 321 322 /* If a gpio pin is configured, read it. */ 323 if (sc->gpio_dev != NULL) { 324 GPIO_PIN_GET(sc->gpio_dev, sc->wp_gpio_pin, &readonly); 325 } 326 327 return (readonly); 328 } 329 330 static int 331 ti_sdhci_detach(device_t dev) 332 { 333 334 return (EBUSY); 335 } 336 337 static void 338 ti_sdhci_hw_init(device_t dev) 339 { 340 struct ti_sdhci_softc *sc = device_get_softc(dev); 341 clk_ident_t clk; 342 uint32_t regval; 343 unsigned long timeout; 344 345 /* Enable the controller and interface/functional clocks */ 346 clk = MMC0_CLK + sc->mmchs_device_id; 347 if (ti_prcm_clk_enable(clk) != 0) { 348 device_printf(dev, "Error: failed to enable MMC clock\n"); 349 return; 350 } 351 352 /* Get the frequency of the source clock */ 353 if (ti_prcm_clk_get_source_freq(clk, &sc->baseclk_hz) != 0) { 354 device_printf(dev, "Error: failed to get source clock freq\n"); 355 return; 356 } 357 358 /* Issue a softreset to the controller */ 359 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET); 360 timeout = 1000; 361 while ((ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & MMCHS_SYSCONFIG_RESET)) { 362 if (--timeout == 0) { 363 device_printf(dev, "Error: Controller reset operation timed out\n"); 364 break; 365 } 366 DELAY(100); 367 } 368 369 /* Reset both the command and data state machines */ 370 ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL); 371 timeout = 1000; 372 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL)) { 373 if (--timeout == 0) { 374 device_printf(dev, "Error: Software reset operation timed out\n"); 375 break; 376 } 377 DELAY(100); 378 } 379 380 /* 381 * The attach() routine has examined fdt data and set flags in 382 * slot.host.caps to reflect what voltages we can handle. Set those 383 * values in the CAPA register. The manual says that these values can 384 * only be set once, "before initialization" whatever that means, and 385 * that they survive a reset. So maybe doing this will be a no-op if 386 * u-boot has already initialized the hardware. 387 */ 388 regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA); 389 if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE) 390 regval |= MMCHS_SD_CAPA_VS18; 391 if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310)) 392 regval |= MMCHS_SD_CAPA_VS30; 393 ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval); 394 395 /* Set initial host configuration (1-bit, std speed, pwr off). */ 396 ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0); 397 ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0); 398 399 /* Set the initial controller configuration. */ 400 ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS); 401 } 402 403 static int 404 ti_sdhci_attach(device_t dev) 405 { 406 struct ti_sdhci_softc *sc = device_get_softc(dev); 407 int rid, err; 408 pcell_t prop; 409 phandle_t node; 410 411 sc->dev = dev; 412 413 /* 414 * Get the MMCHS device id from FDT. If it's not there use the newbus 415 * unit number (which will work as long as the devices are in order and 416 * none are skipped in the fdt). Note that this is a property we made 417 * up and added in freebsd, it doesn't exist in the published bindings. 418 */ 419 node = ofw_bus_get_node(dev); 420 if ((OF_getprop(node, "mmchs-device-id", &prop, sizeof(prop))) <= 0) { 421 sc->mmchs_device_id = device_get_unit(dev); 422 device_printf(dev, "missing mmchs-device-id attribute in FDT, " 423 "using unit number (%d)", sc->mmchs_device_id); 424 } else 425 sc->mmchs_device_id = fdt32_to_cpu(prop); 426 427 /* 428 * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first 429 * device, and only 1p8v on other devices unless an external transceiver 430 * is used. The only way we could know about a transceiver is fdt data. 431 * Note that we have to do this before calling ti_sdhci_hw_init() so 432 * that it can set the right values in the CAPA register, which can only 433 * be done once and never reset. 434 */ 435 sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE; 436 if (sc->mmchs_device_id == 0 || OF_hasprop(node, "ti,dual-volt")) { 437 sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310; 438 } 439 440 /* 441 * See if we've got a GPIO-based write detect pin. This is not the 442 * standard documented property for this, we added it in freebsd. 443 */ 444 if ((OF_getprop(node, "mmchs-wp-gpio-pin", &prop, sizeof(prop))) <= 0) 445 sc->wp_gpio_pin = 0xffffffff; 446 else 447 sc->wp_gpio_pin = fdt32_to_cpu(prop); 448 449 if (sc->wp_gpio_pin != 0xffffffff) { 450 sc->gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 451 if (sc->gpio_dev == NULL) 452 device_printf(dev, "Error: No GPIO device, " 453 "Write Protect pin will not function\n"); 454 else 455 GPIO_PIN_SETFLAGS(sc->gpio_dev, sc->wp_gpio_pin, 456 GPIO_PIN_INPUT); 457 } 458 459 /* 460 * Set the offset from the device's memory start to the MMCHS registers. 461 */ 462 if (ti_chip() == CHIP_OMAP_3) 463 sc->mmchs_reg_off = OMAP3_MMCHS_REG_OFFSET; 464 else if (ti_chip() == CHIP_OMAP_4) 465 sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET; 466 else if (ti_chip() == CHIP_AM335X) 467 sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET; 468 else 469 panic("Unknown OMAP device\n"); 470 471 /* 472 * The standard SDHCI registers are at a fixed offset (the same on all 473 * SoCs) beyond the MMCHS registers. 474 */ 475 sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET; 476 477 /* Resource setup. */ 478 rid = 0; 479 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 480 RF_ACTIVE); 481 if (!sc->mem_res) { 482 device_printf(dev, "cannot allocate memory window\n"); 483 err = ENXIO; 484 goto fail; 485 } 486 487 rid = 0; 488 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 489 RF_ACTIVE); 490 if (!sc->irq_res) { 491 device_printf(dev, "cannot allocate interrupt\n"); 492 err = ENXIO; 493 goto fail; 494 } 495 496 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 497 NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) { 498 device_printf(dev, "cannot setup interrupt handler\n"); 499 err = ENXIO; 500 goto fail; 501 } 502 503 /* Initialise the MMCHS hardware. */ 504 ti_sdhci_hw_init(dev); 505 506 /* 507 * The capabilities register can only express base clock frequencies in 508 * the range of 0-63MHz for a v2.0 controller. Since our clock runs 509 * faster than that, the hardware sets the frequency to zero in the 510 * register. When the register contains zero, the sdhci driver expects 511 * slot.max_clk to already have the right value in it. 512 */ 513 sc->slot.max_clk = sc->baseclk_hz; 514 515 /* 516 * The MMCHS timeout counter is based on the output sdclock. Tell the 517 * sdhci driver to recalculate the timeout clock whenever the output 518 * sdclock frequency changes. 519 */ 520 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 521 522 /* 523 * The MMCHS hardware shifts the 136-bit response data (in violation of 524 * the spec), so tell the sdhci driver not to do the same in software. 525 */ 526 sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE; 527 528 /* 529 * DMA is not really broken, I just haven't implemented it yet. 530 */ 531 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 532 533 /* 534 * Set up the hardware and go. Note that this sets many of the 535 * slot.host.* fields, so we have to do this before overriding any of 536 * those values based on fdt data, below. 537 */ 538 sdhci_init_slot(dev, &sc->slot, 0); 539 540 /* 541 * The SDHCI controller doesn't realize it, but we can support 8-bit 542 * even though we're not a v3.0 controller. If there's an fdt bus-width 543 * property, honor it. 544 */ 545 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) { 546 sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA | 547 MMC_CAP_8_BIT_DATA); 548 switch (prop) { 549 case 8: 550 sc->slot.host.caps |= MMC_CAP_8_BIT_DATA; 551 /* FALLTHROUGH */ 552 case 4: 553 sc->slot.host.caps |= MMC_CAP_4_BIT_DATA; 554 break; 555 case 1: 556 break; 557 default: 558 device_printf(dev, "Bad bus-width value %u\n", prop); 559 break; 560 } 561 } 562 563 bus_generic_probe(dev); 564 bus_generic_attach(dev); 565 566 sdhci_start_slot(&sc->slot); 567 568 return (0); 569 570 fail: 571 if (sc->intr_cookie) 572 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 573 if (sc->irq_res) 574 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 575 if (sc->mem_res) 576 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 577 578 return (err); 579 } 580 581 static int 582 ti_sdhci_probe(device_t dev) 583 { 584 585 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 586 device_set_desc(dev, "TI MMCHS (SDHCI 2.0)"); 587 return (BUS_PROBE_DEFAULT); 588 } 589 590 return (ENXIO); 591 } 592 593 static device_method_t ti_sdhci_methods[] = { 594 /* Device interface */ 595 DEVMETHOD(device_probe, ti_sdhci_probe), 596 DEVMETHOD(device_attach, ti_sdhci_attach), 597 DEVMETHOD(device_detach, ti_sdhci_detach), 598 599 /* Bus interface */ 600 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 601 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 602 DEVMETHOD(bus_print_child, bus_generic_print_child), 603 604 /* MMC bridge interface */ 605 DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios), 606 DEVMETHOD(mmcbr_request, sdhci_generic_request), 607 DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro), 608 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 609 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 610 611 /* SDHCI registers accessors */ 612 DEVMETHOD(sdhci_read_1, ti_sdhci_read_1), 613 DEVMETHOD(sdhci_read_2, ti_sdhci_read_2), 614 DEVMETHOD(sdhci_read_4, ti_sdhci_read_4), 615 DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4), 616 DEVMETHOD(sdhci_write_1, ti_sdhci_write_1), 617 DEVMETHOD(sdhci_write_2, ti_sdhci_write_2), 618 DEVMETHOD(sdhci_write_4, ti_sdhci_write_4), 619 DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4), 620 621 DEVMETHOD_END 622 }; 623 624 static devclass_t ti_sdhci_devclass; 625 626 static driver_t ti_sdhci_driver = { 627 "sdhci_ti", 628 ti_sdhci_methods, 629 sizeof(struct ti_sdhci_softc), 630 }; 631 632 DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, 0, 0); 633 MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1); 634