1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/gpio.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/intr.h> 46 47 #include <dev/fdt/fdt_common.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <dev/mmc/bridge.h> 52 #include <dev/mmc/mmcreg.h> 53 #include <dev/mmc/mmcbrvar.h> 54 55 #include <dev/sdhci/sdhci.h> 56 #include "sdhci_if.h" 57 58 #include <arm/ti/ti_cpuid.h> 59 #include <arm/ti/ti_prcm.h> 60 #include <arm/ti/ti_hwmods.h> 61 #include "gpio_if.h" 62 63 struct ti_sdhci_softc { 64 device_t dev; 65 device_t gpio_dev; 66 struct resource * mem_res; 67 struct resource * irq_res; 68 void * intr_cookie; 69 struct sdhci_slot slot; 70 clk_ident_t mmchs_clk_id; 71 uint32_t mmchs_reg_off; 72 uint32_t sdhci_reg_off; 73 uint32_t baseclk_hz; 74 uint32_t wp_gpio_pin; 75 uint32_t cmd_and_mode; 76 uint32_t sdhci_clkdiv; 77 boolean_t disable_highspeed; 78 boolean_t force_card_present; 79 }; 80 81 /* 82 * Table of supported FDT compat strings. 83 * 84 * Note that "ti,mmchs" is our own invention, and should be phased out in favor 85 * of the documented names. 86 * 87 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x. 88 */ 89 static struct ofw_compat_data compat_data[] = { 90 {"ti,omap3-hsmmc", 1}, 91 {"ti,omap4-hsmmc", 1}, 92 {"ti,mmchs", 1}, 93 {NULL, 0}, 94 }; 95 96 /* 97 * The MMCHS hardware has a few control and status registers at the beginning of 98 * the device's memory map, followed by the standard sdhci register block. 99 * Different SoCs have the register blocks at different offsets from the 100 * beginning of the device. Define some constants to map out the registers we 101 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far 102 * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs. 103 */ 104 #define OMAP3_MMCHS_REG_OFFSET 0x000 105 #define OMAP4_MMCHS_REG_OFFSET 0x100 106 #define AM335X_MMCHS_REG_OFFSET 0x100 107 #define SDHCI_REG_OFFSET 0x100 108 109 #define MMCHS_SYSCONFIG 0x010 110 #define MMCHS_SYSCONFIG_RESET (1 << 1) 111 #define MMCHS_SYSSTATUS 0x014 112 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0) 113 #define MMCHS_CON 0x02C 114 #define MMCHS_CON_DW8 (1 << 5) 115 #define MMCHS_CON_DVAL_8_4MS (3 << 9) 116 #define MMCHS_CON_OD (1 << 0) 117 #define MMCHS_SYSCTL 0x12C 118 #define MMCHS_SYSCTL_CLKD_MASK 0x3FF 119 #define MMCHS_SYSCTL_CLKD_SHIFT 6 120 #define MMCHS_SD_CAPA 0x140 121 #define MMCHS_SD_CAPA_VS18 (1 << 26) 122 #define MMCHS_SD_CAPA_VS30 (1 << 25) 123 #define MMCHS_SD_CAPA_VS33 (1 << 24) 124 125 static inline uint32_t 126 ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off) 127 { 128 129 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); 130 } 131 132 static inline void 133 ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 134 { 135 136 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); 137 } 138 139 static inline uint32_t 140 RD4(struct ti_sdhci_softc *sc, bus_size_t off) 141 { 142 143 return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off)); 144 } 145 146 static inline void 147 WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 148 { 149 150 bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val); 151 } 152 153 static uint8_t 154 ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 155 { 156 struct ti_sdhci_softc *sc = device_get_softc(dev); 157 158 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 159 } 160 161 static uint16_t 162 ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 163 { 164 struct ti_sdhci_softc *sc = device_get_softc(dev); 165 uint32_t clkdiv, val32; 166 167 /* 168 * The MMCHS hardware has a non-standard interpretation of the sdclock 169 * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6) 170 * but doesn't split them into low:high fields. Instead they're a 171 * single number in the range 0..1023 and the number is exactly the 172 * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI 173 * driver code expects a v2.0 or v3.0 divisor. The shifting and masking 174 * here extracts the MMCHS representation from the hardware word, cleans 175 * those bits out, applies the 2N adjustment, and plugs the result into 176 * the bit positions for the 2.0 or 3.0 divisor in the returned register 177 * value. The ti_sdhci_write_2() routine performs the opposite 178 * transformation when the SDHCI driver writes to the register. 179 */ 180 if (off == SDHCI_CLOCK_CONTROL) { 181 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 182 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) & 183 MMCHS_SYSCTL_CLKD_MASK) / 2; 184 val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT); 185 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 186 if (slot->version >= SDHCI_SPEC_300) 187 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) & 188 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT; 189 return (val32 & 0xffff); 190 } 191 192 /* 193 * Standard 32-bit handling of command and transfer mode. 194 */ 195 if (off == SDHCI_TRANSFER_MODE) { 196 return (sc->cmd_and_mode >> 16); 197 } else if (off == SDHCI_COMMAND_FLAGS) { 198 return (sc->cmd_and_mode & 0x0000ffff); 199 } 200 201 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 202 } 203 204 static uint32_t 205 ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 206 { 207 struct ti_sdhci_softc *sc = device_get_softc(dev); 208 uint32_t val32; 209 210 val32 = RD4(sc, off); 211 212 /* 213 * If we need to disallow highspeed mode due to the OMAP4 erratum, strip 214 * that flag from the returned capabilities. 215 */ 216 if (off == SDHCI_CAPABILITIES && sc->disable_highspeed) 217 val32 &= ~SDHCI_CAN_DO_HISPD; 218 219 /* 220 * Force the card-present state if necessary. 221 */ 222 if (off == SDHCI_PRESENT_STATE && sc->force_card_present) 223 val32 |= SDHCI_CARD_PRESENT; 224 225 return (val32); 226 } 227 228 static void 229 ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 230 uint32_t *data, bus_size_t count) 231 { 232 struct ti_sdhci_softc *sc = device_get_softc(dev); 233 234 bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 235 } 236 237 static void 238 ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 239 uint8_t val) 240 { 241 struct ti_sdhci_softc *sc = device_get_softc(dev); 242 uint32_t val32; 243 244 val32 = RD4(sc, off & ~3); 245 val32 &= ~(0xff << (off & 3) * 8); 246 val32 |= (val << (off & 3) * 8); 247 248 WR4(sc, off & ~3, val32); 249 } 250 251 static void 252 ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 253 uint16_t val) 254 { 255 struct ti_sdhci_softc *sc = device_get_softc(dev); 256 uint32_t clkdiv, val32; 257 258 /* 259 * Translate between the hardware and SDHCI 2.0 or 3.0 representations 260 * of the clock divisor. See the comments in ti_sdhci_read_2() for 261 * details. 262 */ 263 if (off == SDHCI_CLOCK_CONTROL) { 264 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 265 if (slot->version >= SDHCI_SPEC_300) 266 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) & 267 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; 268 clkdiv *= 2; 269 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK) 270 clkdiv = MMCHS_SYSCTL_CLKD_MASK; 271 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 272 val32 &= 0xffff0000; 273 val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK << 274 MMCHS_SYSCTL_CLKD_SHIFT); 275 val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT; 276 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 277 return; 278 } 279 280 /* 281 * Standard 32-bit handling of command and transfer mode. 282 */ 283 if (off == SDHCI_TRANSFER_MODE) { 284 sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) | 285 ((uint32_t)val & 0x0000ffff); 286 return; 287 } else if (off == SDHCI_COMMAND_FLAGS) { 288 sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) | 289 ((uint32_t)val << 16); 290 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 291 return; 292 } 293 294 val32 = RD4(sc, off & ~3); 295 val32 &= ~(0xffff << (off & 3) * 8); 296 val32 |= ((val & 0xffff) << (off & 3) * 8); 297 WR4(sc, off & ~3, val32); 298 } 299 300 static void 301 ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 302 uint32_t val) 303 { 304 struct ti_sdhci_softc *sc = device_get_softc(dev); 305 306 WR4(sc, off, val); 307 } 308 309 static void 310 ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 311 uint32_t *data, bus_size_t count) 312 { 313 struct ti_sdhci_softc *sc = device_get_softc(dev); 314 315 bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 316 } 317 318 static void 319 ti_sdhci_intr(void *arg) 320 { 321 struct ti_sdhci_softc *sc = arg; 322 323 sdhci_generic_intr(&sc->slot); 324 } 325 326 static int 327 ti_sdhci_update_ios(device_t brdev, device_t reqdev) 328 { 329 struct ti_sdhci_softc *sc = device_get_softc(brdev); 330 struct sdhci_slot *slot; 331 struct mmc_ios *ios; 332 uint32_t val32, newval32; 333 334 slot = device_get_ivars(reqdev); 335 ios = &slot->host.ios; 336 337 /* 338 * There is an 8-bit-bus bit in the MMCHS control register which, when 339 * set, overrides the 1 vs 4 bit setting in the standard SDHCI 340 * registers. Set that bit first according to whether an 8-bit bus is 341 * requested, then let the standard driver handle everything else. 342 */ 343 val32 = ti_mmchs_read_4(sc, MMCHS_CON); 344 newval32 = val32; 345 346 if (ios->bus_width == bus_width_8) 347 newval32 |= MMCHS_CON_DW8; 348 else 349 newval32 &= ~MMCHS_CON_DW8; 350 351 if (ios->bus_mode == opendrain) 352 newval32 |= MMCHS_CON_OD; 353 else /* if (ios->bus_mode == pushpull) */ 354 newval32 &= ~MMCHS_CON_OD; 355 356 if (newval32 != val32) 357 ti_mmchs_write_4(sc, MMCHS_CON, newval32); 358 359 return (sdhci_generic_update_ios(brdev, reqdev)); 360 } 361 362 static int 363 ti_sdhci_get_ro(device_t brdev, device_t reqdev) 364 { 365 struct ti_sdhci_softc *sc = device_get_softc(brdev); 366 unsigned int readonly = 0; 367 368 /* If a gpio pin is configured, read it. */ 369 if (sc->gpio_dev != NULL) { 370 GPIO_PIN_GET(sc->gpio_dev, sc->wp_gpio_pin, &readonly); 371 } 372 373 return (readonly); 374 } 375 376 static int 377 ti_sdhci_detach(device_t dev) 378 { 379 380 return (EBUSY); 381 } 382 383 static void 384 ti_sdhci_hw_init(device_t dev) 385 { 386 struct ti_sdhci_softc *sc = device_get_softc(dev); 387 uint32_t regval; 388 unsigned long timeout; 389 390 /* Enable the controller and interface/functional clocks */ 391 if (ti_prcm_clk_enable(sc->mmchs_clk_id) != 0) { 392 device_printf(dev, "Error: failed to enable MMC clock\n"); 393 return; 394 } 395 396 /* Get the frequency of the source clock */ 397 if (ti_prcm_clk_get_source_freq(sc->mmchs_clk_id, 398 &sc->baseclk_hz) != 0) { 399 device_printf(dev, "Error: failed to get source clock freq\n"); 400 return; 401 } 402 403 /* Issue a softreset to the controller */ 404 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET); 405 timeout = 1000; 406 while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & 407 MMCHS_SYSSTATUS_RESETDONE)) { 408 if (--timeout == 0) { 409 device_printf(dev, 410 "Error: Controller reset operation timed out\n"); 411 break; 412 } 413 DELAY(100); 414 } 415 416 /* 417 * Reset the command and data state machines and also other aspects of 418 * the controller such as bus clock and power. 419 * 420 * If we read the software reset register too fast after writing it we 421 * can get back a zero that means the reset hasn't started yet rather 422 * than that the reset is complete. Per TI recommendations, work around 423 * it by reading until we see the reset bit asserted, then read until 424 * it's clear. We also set the SDHCI_QUIRK_WAITFOR_RESET_ASSERTED quirk 425 * so that the main sdhci driver uses this same logic in its resets. 426 */ 427 ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL); 428 timeout = 10000; 429 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & 430 SDHCI_RESET_ALL) != SDHCI_RESET_ALL) { 431 if (--timeout == 0) { 432 break; 433 } 434 DELAY(1); 435 } 436 timeout = 10000; 437 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & 438 SDHCI_RESET_ALL)) { 439 if (--timeout == 0) { 440 device_printf(dev, 441 "Error: Software reset operation timed out\n"); 442 break; 443 } 444 DELAY(100); 445 } 446 447 /* 448 * The attach() routine has examined fdt data and set flags in 449 * slot.host.caps to reflect what voltages we can handle. Set those 450 * values in the CAPA register. The manual says that these values can 451 * only be set once, "before initialization" whatever that means, and 452 * that they survive a reset. So maybe doing this will be a no-op if 453 * u-boot has already initialized the hardware. 454 */ 455 regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA); 456 if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE) 457 regval |= MMCHS_SD_CAPA_VS18; 458 if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310)) 459 regval |= MMCHS_SD_CAPA_VS30; 460 ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval); 461 462 /* Set initial host configuration (1-bit, std speed, pwr off). */ 463 ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0); 464 ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0); 465 466 /* Set the initial controller configuration. */ 467 ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS); 468 } 469 470 static int 471 ti_sdhci_attach(device_t dev) 472 { 473 struct ti_sdhci_softc *sc = device_get_softc(dev); 474 int rid, err; 475 pcell_t prop; 476 phandle_t node; 477 478 sc->dev = dev; 479 480 /* 481 * Get the MMCHS device id from FDT. If it's not there use the newbus 482 * unit number (which will work as long as the devices are in order and 483 * none are skipped in the fdt). Note that this is a property we made 484 * up and added in freebsd, it doesn't exist in the published bindings. 485 */ 486 node = ofw_bus_get_node(dev); 487 sc->mmchs_clk_id = ti_hwmods_get_clock(dev); 488 if (sc->mmchs_clk_id == INVALID_CLK_IDENT) { 489 device_printf(dev, "failed to get clock based on hwmods property\n"); 490 } 491 492 /* 493 * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first 494 * device, and only 1p8v on other devices unless an external transceiver 495 * is used. The only way we could know about a transceiver is fdt data. 496 * Note that we have to do this before calling ti_sdhci_hw_init() so 497 * that it can set the right values in the CAPA register, which can only 498 * be done once and never reset. 499 */ 500 sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE; 501 if (sc->mmchs_clk_id == MMC1_CLK || OF_hasprop(node, "ti,dual-volt")) { 502 sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310; 503 } 504 505 /* 506 * See if we've got a GPIO-based write detect pin. This is not the 507 * standard documented property for this, we added it in freebsd. 508 */ 509 if ((OF_getprop(node, "mmchs-wp-gpio-pin", &prop, sizeof(prop))) <= 0) 510 sc->wp_gpio_pin = 0xffffffff; 511 else 512 sc->wp_gpio_pin = fdt32_to_cpu(prop); 513 514 if (sc->wp_gpio_pin != 0xffffffff) { 515 sc->gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 516 if (sc->gpio_dev == NULL) 517 device_printf(dev, "Error: No GPIO device, " 518 "Write Protect pin will not function\n"); 519 else 520 GPIO_PIN_SETFLAGS(sc->gpio_dev, sc->wp_gpio_pin, 521 GPIO_PIN_INPUT); 522 } 523 524 /* 525 * Set the offset from the device's memory start to the MMCHS registers. 526 * Also for OMAP4 disable high speed mode due to erratum ID i626. 527 */ 528 switch (ti_chip()) { 529 #ifdef SOC_OMAP4 530 case CHIP_OMAP_4: 531 sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET; 532 sc->disable_highspeed = true; 533 break; 534 #endif 535 #ifdef SOC_TI_AM335X 536 case CHIP_AM335X: 537 sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET; 538 break; 539 #endif 540 default: 541 panic("Unknown OMAP device\n"); 542 } 543 544 /* 545 * The standard SDHCI registers are at a fixed offset (the same on all 546 * SoCs) beyond the MMCHS registers. 547 */ 548 sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET; 549 550 /* Resource setup. */ 551 rid = 0; 552 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 553 RF_ACTIVE); 554 if (!sc->mem_res) { 555 device_printf(dev, "cannot allocate memory window\n"); 556 err = ENXIO; 557 goto fail; 558 } 559 560 rid = 0; 561 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 562 RF_ACTIVE); 563 if (!sc->irq_res) { 564 device_printf(dev, "cannot allocate interrupt\n"); 565 err = ENXIO; 566 goto fail; 567 } 568 569 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 570 NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) { 571 device_printf(dev, "cannot setup interrupt handler\n"); 572 err = ENXIO; 573 goto fail; 574 } 575 576 /* Initialise the MMCHS hardware. */ 577 ti_sdhci_hw_init(dev); 578 579 /* 580 * The capabilities register can only express base clock frequencies in 581 * the range of 0-63MHz for a v2.0 controller. Since our clock runs 582 * faster than that, the hardware sets the frequency to zero in the 583 * register. When the register contains zero, the sdhci driver expects 584 * slot.max_clk to already have the right value in it. 585 */ 586 sc->slot.max_clk = sc->baseclk_hz; 587 588 /* 589 * The MMCHS timeout counter is based on the output sdclock. Tell the 590 * sdhci driver to recalculate the timeout clock whenever the output 591 * sdclock frequency changes. 592 */ 593 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 594 595 /* 596 * The MMCHS hardware shifts the 136-bit response data (in violation of 597 * the spec), so tell the sdhci driver not to do the same in software. 598 */ 599 sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE; 600 601 /* 602 * Reset bits are broken, have to wait to see the bits asserted 603 * before waiting to see them de-asserted. 604 */ 605 sc->slot.quirks |= SDHCI_QUIRK_WAITFOR_RESET_ASSERTED; 606 607 /* 608 * DMA is not really broken, I just haven't implemented it yet. 609 */ 610 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 611 612 /* 613 * Set up the hardware and go. Note that this sets many of the 614 * slot.host.* fields, so we have to do this before overriding any of 615 * those values based on fdt data, below. 616 */ 617 sdhci_init_slot(dev, &sc->slot, 0); 618 619 /* 620 * The SDHCI controller doesn't realize it, but we can support 8-bit 621 * even though we're not a v3.0 controller. If there's an fdt bus-width 622 * property, honor it. 623 */ 624 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) { 625 sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA | 626 MMC_CAP_8_BIT_DATA); 627 switch (prop) { 628 case 8: 629 sc->slot.host.caps |= MMC_CAP_8_BIT_DATA; 630 /* FALLTHROUGH */ 631 case 4: 632 sc->slot.host.caps |= MMC_CAP_4_BIT_DATA; 633 break; 634 case 1: 635 break; 636 default: 637 device_printf(dev, "Bad bus-width value %u\n", prop); 638 break; 639 } 640 } 641 642 /* 643 * If the slot is flagged with the non-removable property, set our flag 644 * to always force the SDHCI_CARD_PRESENT bit on. 645 */ 646 node = ofw_bus_get_node(dev); 647 if (OF_hasprop(node, "non-removable")) 648 sc->force_card_present = true; 649 650 bus_generic_probe(dev); 651 bus_generic_attach(dev); 652 653 sdhci_start_slot(&sc->slot); 654 655 return (0); 656 657 fail: 658 if (sc->intr_cookie) 659 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 660 if (sc->irq_res) 661 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 662 if (sc->mem_res) 663 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 664 665 return (err); 666 } 667 668 static int 669 ti_sdhci_probe(device_t dev) 670 { 671 672 if (!ofw_bus_status_okay(dev)) 673 return (ENXIO); 674 675 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 676 device_set_desc(dev, "TI MMCHS (SDHCI 2.0)"); 677 return (BUS_PROBE_DEFAULT); 678 } 679 680 return (ENXIO); 681 } 682 683 static device_method_t ti_sdhci_methods[] = { 684 /* Device interface */ 685 DEVMETHOD(device_probe, ti_sdhci_probe), 686 DEVMETHOD(device_attach, ti_sdhci_attach), 687 DEVMETHOD(device_detach, ti_sdhci_detach), 688 689 /* Bus interface */ 690 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 691 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 692 DEVMETHOD(bus_print_child, bus_generic_print_child), 693 694 /* MMC bridge interface */ 695 DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios), 696 DEVMETHOD(mmcbr_request, sdhci_generic_request), 697 DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro), 698 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 699 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 700 701 /* SDHCI registers accessors */ 702 DEVMETHOD(sdhci_read_1, ti_sdhci_read_1), 703 DEVMETHOD(sdhci_read_2, ti_sdhci_read_2), 704 DEVMETHOD(sdhci_read_4, ti_sdhci_read_4), 705 DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4), 706 DEVMETHOD(sdhci_write_1, ti_sdhci_write_1), 707 DEVMETHOD(sdhci_write_2, ti_sdhci_write_2), 708 DEVMETHOD(sdhci_write_4, ti_sdhci_write_4), 709 DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4), 710 711 DEVMETHOD_END 712 }; 713 714 static devclass_t ti_sdhci_devclass; 715 716 static driver_t ti_sdhci_driver = { 717 "sdhci_ti", 718 ti_sdhci_methods, 719 sizeof(struct ti_sdhci_softc), 720 }; 721 722 DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, 0, 0); 723 MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1); 724 DRIVER_MODULE(mmc, sdhci_ti, mmc_driver, mmc_devclass, NULL, NULL); 725 MODULE_DEPEND(sdhci_ti, mmc, 1, 1, 1); 726