1 /*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/gpio.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/intr.h> 46 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <dev/mmc/bridge.h> 51 #include <dev/mmc/mmcreg.h> 52 #include <dev/mmc/mmcbrvar.h> 53 54 #include <dev/sdhci/sdhci.h> 55 #include <dev/sdhci/sdhci_fdt_gpio.h> 56 #include "sdhci_if.h" 57 58 #include <arm/ti/ti_cpuid.h> 59 #include <arm/ti/ti_prcm.h> 60 #include <arm/ti/ti_hwmods.h> 61 #include "gpio_if.h" 62 63 struct ti_sdhci_softc { 64 device_t dev; 65 struct sdhci_fdt_gpio * gpio; 66 struct resource * mem_res; 67 struct resource * irq_res; 68 void * intr_cookie; 69 struct sdhci_slot slot; 70 clk_ident_t mmchs_clk_id; 71 uint32_t mmchs_reg_off; 72 uint32_t sdhci_reg_off; 73 uint32_t baseclk_hz; 74 uint32_t cmd_and_mode; 75 uint32_t sdhci_clkdiv; 76 boolean_t disable_highspeed; 77 boolean_t force_card_present; 78 boolean_t disable_readonly; 79 }; 80 81 /* 82 * Table of supported FDT compat strings. 83 * 84 * Note that "ti,mmchs" is our own invention, and should be phased out in favor 85 * of the documented names. 86 * 87 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x. 88 */ 89 static struct ofw_compat_data compat_data[] = { 90 {"ti,omap3-hsmmc", 1}, 91 {"ti,omap4-hsmmc", 1}, 92 {"ti,mmchs", 1}, 93 {NULL, 0}, 94 }; 95 96 /* 97 * The MMCHS hardware has a few control and status registers at the beginning of 98 * the device's memory map, followed by the standard sdhci register block. 99 * Different SoCs have the register blocks at different offsets from the 100 * beginning of the device. Define some constants to map out the registers we 101 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far 102 * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs. 103 */ 104 #define OMAP3_MMCHS_REG_OFFSET 0x000 105 #define OMAP4_MMCHS_REG_OFFSET 0x100 106 #define AM335X_MMCHS_REG_OFFSET 0x100 107 #define SDHCI_REG_OFFSET 0x100 108 109 #define MMCHS_SYSCONFIG 0x010 110 #define MMCHS_SYSCONFIG_RESET (1 << 1) 111 #define MMCHS_SYSSTATUS 0x014 112 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0) 113 #define MMCHS_CON 0x02C 114 #define MMCHS_CON_DW8 (1 << 5) 115 #define MMCHS_CON_DVAL_8_4MS (3 << 9) 116 #define MMCHS_CON_OD (1 << 0) 117 #define MMCHS_SYSCTL 0x12C 118 #define MMCHS_SYSCTL_CLKD_MASK 0x3FF 119 #define MMCHS_SYSCTL_CLKD_SHIFT 6 120 #define MMCHS_SD_CAPA 0x140 121 #define MMCHS_SD_CAPA_VS18 (1 << 26) 122 #define MMCHS_SD_CAPA_VS30 (1 << 25) 123 #define MMCHS_SD_CAPA_VS33 (1 << 24) 124 125 static inline uint32_t 126 ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off) 127 { 128 129 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); 130 } 131 132 static inline void 133 ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 134 { 135 136 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); 137 } 138 139 static inline uint32_t 140 RD4(struct ti_sdhci_softc *sc, bus_size_t off) 141 { 142 143 return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off)); 144 } 145 146 static inline void 147 WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) 148 { 149 150 bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val); 151 } 152 153 static uint8_t 154 ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 155 { 156 struct ti_sdhci_softc *sc = device_get_softc(dev); 157 158 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); 159 } 160 161 static uint16_t 162 ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 163 { 164 struct ti_sdhci_softc *sc = device_get_softc(dev); 165 uint32_t clkdiv, val32; 166 167 /* 168 * The MMCHS hardware has a non-standard interpretation of the sdclock 169 * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6) 170 * but doesn't split them into low:high fields. Instead they're a 171 * single number in the range 0..1023 and the number is exactly the 172 * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI 173 * driver code expects a v2.0 or v3.0 divisor. The shifting and masking 174 * here extracts the MMCHS representation from the hardware word, cleans 175 * those bits out, applies the 2N adjustment, and plugs the result into 176 * the bit positions for the 2.0 or 3.0 divisor in the returned register 177 * value. The ti_sdhci_write_2() routine performs the opposite 178 * transformation when the SDHCI driver writes to the register. 179 */ 180 if (off == SDHCI_CLOCK_CONTROL) { 181 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 182 clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) & 183 MMCHS_SYSCTL_CLKD_MASK) / 2; 184 val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT); 185 val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; 186 if (slot->version >= SDHCI_SPEC_300) 187 val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) & 188 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT; 189 return (val32 & 0xffff); 190 } 191 192 /* 193 * Standard 32-bit handling of command and transfer mode. 194 */ 195 if (off == SDHCI_TRANSFER_MODE) { 196 return (sc->cmd_and_mode >> 16); 197 } else if (off == SDHCI_COMMAND_FLAGS) { 198 return (sc->cmd_and_mode & 0x0000ffff); 199 } 200 201 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); 202 } 203 204 static uint32_t 205 ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 206 { 207 struct ti_sdhci_softc *sc = device_get_softc(dev); 208 uint32_t val32; 209 210 val32 = RD4(sc, off); 211 212 /* 213 * If we need to disallow highspeed mode due to the OMAP4 erratum, strip 214 * that flag from the returned capabilities. 215 */ 216 if (off == SDHCI_CAPABILITIES && sc->disable_highspeed) 217 val32 &= ~SDHCI_CAN_DO_HISPD; 218 219 /* 220 * Force the card-present state if necessary. 221 */ 222 if (off == SDHCI_PRESENT_STATE && sc->force_card_present) 223 val32 |= SDHCI_CARD_PRESENT; 224 225 return (val32); 226 } 227 228 static void 229 ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 230 uint32_t *data, bus_size_t count) 231 { 232 struct ti_sdhci_softc *sc = device_get_softc(dev); 233 234 bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 235 } 236 237 static void 238 ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, 239 uint8_t val) 240 { 241 struct ti_sdhci_softc *sc = device_get_softc(dev); 242 uint32_t val32; 243 244 val32 = RD4(sc, off & ~3); 245 val32 &= ~(0xff << (off & 3) * 8); 246 val32 |= (val << (off & 3) * 8); 247 248 WR4(sc, off & ~3, val32); 249 } 250 251 static void 252 ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, 253 uint16_t val) 254 { 255 struct ti_sdhci_softc *sc = device_get_softc(dev); 256 uint32_t clkdiv, val32; 257 258 /* 259 * Translate between the hardware and SDHCI 2.0 or 3.0 representations 260 * of the clock divisor. See the comments in ti_sdhci_read_2() for 261 * details. 262 */ 263 if (off == SDHCI_CLOCK_CONTROL) { 264 clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; 265 if (slot->version >= SDHCI_SPEC_300) 266 clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) & 267 SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; 268 clkdiv *= 2; 269 if (clkdiv > MMCHS_SYSCTL_CLKD_MASK) 270 clkdiv = MMCHS_SYSCTL_CLKD_MASK; 271 val32 = RD4(sc, SDHCI_CLOCK_CONTROL); 272 val32 &= 0xffff0000; 273 val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK << 274 MMCHS_SYSCTL_CLKD_SHIFT); 275 val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT; 276 WR4(sc, SDHCI_CLOCK_CONTROL, val32); 277 return; 278 } 279 280 /* 281 * Standard 32-bit handling of command and transfer mode. 282 */ 283 if (off == SDHCI_TRANSFER_MODE) { 284 sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) | 285 ((uint32_t)val & 0x0000ffff); 286 return; 287 } else if (off == SDHCI_COMMAND_FLAGS) { 288 sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) | 289 ((uint32_t)val << 16); 290 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); 291 return; 292 } 293 294 val32 = RD4(sc, off & ~3); 295 val32 &= ~(0xffff << (off & 3) * 8); 296 val32 |= ((val & 0xffff) << (off & 3) * 8); 297 WR4(sc, off & ~3, val32); 298 } 299 300 static void 301 ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 302 uint32_t val) 303 { 304 struct ti_sdhci_softc *sc = device_get_softc(dev); 305 306 WR4(sc, off, val); 307 } 308 309 static void 310 ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, 311 uint32_t *data, bus_size_t count) 312 { 313 struct ti_sdhci_softc *sc = device_get_softc(dev); 314 315 bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); 316 } 317 318 static void 319 ti_sdhci_intr(void *arg) 320 { 321 struct ti_sdhci_softc *sc = arg; 322 323 sdhci_generic_intr(&sc->slot); 324 } 325 326 static int 327 ti_sdhci_update_ios(device_t brdev, device_t reqdev) 328 { 329 struct ti_sdhci_softc *sc = device_get_softc(brdev); 330 struct sdhci_slot *slot; 331 struct mmc_ios *ios; 332 uint32_t val32, newval32; 333 334 slot = device_get_ivars(reqdev); 335 ios = &slot->host.ios; 336 337 /* 338 * There is an 8-bit-bus bit in the MMCHS control register which, when 339 * set, overrides the 1 vs 4 bit setting in the standard SDHCI 340 * registers. Set that bit first according to whether an 8-bit bus is 341 * requested, then let the standard driver handle everything else. 342 */ 343 val32 = ti_mmchs_read_4(sc, MMCHS_CON); 344 newval32 = val32; 345 346 if (ios->bus_width == bus_width_8) 347 newval32 |= MMCHS_CON_DW8; 348 else 349 newval32 &= ~MMCHS_CON_DW8; 350 351 if (ios->bus_mode == opendrain) 352 newval32 |= MMCHS_CON_OD; 353 else /* if (ios->bus_mode == pushpull) */ 354 newval32 &= ~MMCHS_CON_OD; 355 356 if (newval32 != val32) 357 ti_mmchs_write_4(sc, MMCHS_CON, newval32); 358 359 return (sdhci_generic_update_ios(brdev, reqdev)); 360 } 361 362 static int 363 ti_sdhci_get_ro(device_t brdev, device_t reqdev) 364 { 365 struct ti_sdhci_softc *sc = device_get_softc(brdev); 366 367 if (sc->disable_readonly) 368 return (0); 369 370 return (sdhci_fdt_gpio_get_readonly(sc->gpio)); 371 } 372 373 static bool 374 ti_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot) 375 { 376 struct ti_sdhci_softc *sc = device_get_softc(dev); 377 378 return (sdhci_fdt_gpio_get_present(sc->gpio)); 379 } 380 381 static int 382 ti_sdhci_detach(device_t dev) 383 { 384 385 /* sdhci_fdt_gpio_teardown(sc->gpio); */ 386 387 return (EBUSY); 388 } 389 390 static void 391 ti_sdhci_hw_init(device_t dev) 392 { 393 struct ti_sdhci_softc *sc = device_get_softc(dev); 394 uint32_t regval; 395 unsigned long timeout; 396 397 /* Enable the controller and interface/functional clocks */ 398 if (ti_prcm_clk_enable(sc->mmchs_clk_id) != 0) { 399 device_printf(dev, "Error: failed to enable MMC clock\n"); 400 return; 401 } 402 403 /* Get the frequency of the source clock */ 404 if (ti_prcm_clk_get_source_freq(sc->mmchs_clk_id, 405 &sc->baseclk_hz) != 0) { 406 device_printf(dev, "Error: failed to get source clock freq\n"); 407 return; 408 } 409 410 /* Issue a softreset to the controller */ 411 ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET); 412 timeout = 1000; 413 while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & 414 MMCHS_SYSSTATUS_RESETDONE)) { 415 if (--timeout == 0) { 416 device_printf(dev, 417 "Error: Controller reset operation timed out\n"); 418 break; 419 } 420 DELAY(100); 421 } 422 423 /* 424 * Reset the command and data state machines and also other aspects of 425 * the controller such as bus clock and power. 426 * 427 * If we read the software reset register too fast after writing it we 428 * can get back a zero that means the reset hasn't started yet rather 429 * than that the reset is complete. Per TI recommendations, work around 430 * it by reading until we see the reset bit asserted, then read until 431 * it's clear. We also set the SDHCI_QUIRK_WAITFOR_RESET_ASSERTED quirk 432 * so that the main sdhci driver uses this same logic in its resets. 433 */ 434 ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL); 435 timeout = 10000; 436 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & 437 SDHCI_RESET_ALL) != SDHCI_RESET_ALL) { 438 if (--timeout == 0) { 439 break; 440 } 441 DELAY(1); 442 } 443 timeout = 10000; 444 while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & 445 SDHCI_RESET_ALL)) { 446 if (--timeout == 0) { 447 device_printf(dev, 448 "Error: Software reset operation timed out\n"); 449 break; 450 } 451 DELAY(100); 452 } 453 454 /* 455 * The attach() routine has examined fdt data and set flags in 456 * slot.host.caps to reflect what voltages we can handle. Set those 457 * values in the CAPA register. The manual says that these values can 458 * only be set once, "before initialization" whatever that means, and 459 * that they survive a reset. So maybe doing this will be a no-op if 460 * u-boot has already initialized the hardware. 461 */ 462 regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA); 463 if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE) 464 regval |= MMCHS_SD_CAPA_VS18; 465 if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310)) 466 regval |= MMCHS_SD_CAPA_VS30; 467 ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval); 468 469 /* Set initial host configuration (1-bit, std speed, pwr off). */ 470 ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0); 471 ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0); 472 473 /* Set the initial controller configuration. */ 474 ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS); 475 } 476 477 static int 478 ti_sdhci_attach(device_t dev) 479 { 480 struct ti_sdhci_softc *sc = device_get_softc(dev); 481 int rid, err; 482 pcell_t prop; 483 phandle_t node; 484 485 sc->dev = dev; 486 487 /* 488 * Get the MMCHS device id from FDT. If it's not there use the newbus 489 * unit number (which will work as long as the devices are in order and 490 * none are skipped in the fdt). Note that this is a property we made 491 * up and added in freebsd, it doesn't exist in the published bindings. 492 */ 493 node = ofw_bus_get_node(dev); 494 sc->mmchs_clk_id = ti_hwmods_get_clock(dev); 495 if (sc->mmchs_clk_id == INVALID_CLK_IDENT) { 496 device_printf(dev, "failed to get clock based on hwmods property\n"); 497 } 498 499 /* 500 * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first 501 * device, and only 1p8v on other devices unless an external transceiver 502 * is used. The only way we could know about a transceiver is fdt data. 503 * Note that we have to do this before calling ti_sdhci_hw_init() so 504 * that it can set the right values in the CAPA register, which can only 505 * be done once and never reset. 506 */ 507 sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE; 508 if (sc->mmchs_clk_id == MMC1_CLK || OF_hasprop(node, "ti,dual-volt")) { 509 sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310; 510 } 511 512 /* 513 * Set the offset from the device's memory start to the MMCHS registers. 514 * Also for OMAP4 disable high speed mode due to erratum ID i626. 515 */ 516 switch (ti_chip()) { 517 #ifdef SOC_OMAP4 518 case CHIP_OMAP_4: 519 sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET; 520 sc->disable_highspeed = true; 521 break; 522 #endif 523 #ifdef SOC_TI_AM335X 524 case CHIP_AM335X: 525 sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET; 526 break; 527 #endif 528 default: 529 panic("Unknown OMAP device\n"); 530 } 531 532 /* 533 * The standard SDHCI registers are at a fixed offset (the same on all 534 * SoCs) beyond the MMCHS registers. 535 */ 536 sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET; 537 538 /* Resource setup. */ 539 rid = 0; 540 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 541 RF_ACTIVE); 542 if (!sc->mem_res) { 543 device_printf(dev, "cannot allocate memory window\n"); 544 err = ENXIO; 545 goto fail; 546 } 547 548 rid = 0; 549 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 550 RF_ACTIVE); 551 if (!sc->irq_res) { 552 device_printf(dev, "cannot allocate interrupt\n"); 553 err = ENXIO; 554 goto fail; 555 } 556 557 if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 558 NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) { 559 device_printf(dev, "cannot setup interrupt handler\n"); 560 err = ENXIO; 561 goto fail; 562 } 563 564 /* 565 * Set up handling of card-detect and write-protect gpio lines. 566 * 567 * If there is no write protect info in the fdt data, fall back to the 568 * historical practice of assuming that the card is writable. This 569 * works around bad fdt data from the upstream source. The alternative 570 * would be to trust the sdhci controller's PRESENT_STATE register WP 571 * bit, but it may say write protect is in effect when it's not if the 572 * pinmux setup doesn't route the WP signal into the sdchi block. 573 */ 574 sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot); 575 576 if (!OF_hasprop(node, "wp-gpios") && !OF_hasprop(node, "wp-disable")) 577 sc->disable_readonly = true; 578 579 /* Initialise the MMCHS hardware. */ 580 ti_sdhci_hw_init(dev); 581 582 /* 583 * The capabilities register can only express base clock frequencies in 584 * the range of 0-63MHz for a v2.0 controller. Since our clock runs 585 * faster than that, the hardware sets the frequency to zero in the 586 * register. When the register contains zero, the sdhci driver expects 587 * slot.max_clk to already have the right value in it. 588 */ 589 sc->slot.max_clk = sc->baseclk_hz; 590 591 /* 592 * The MMCHS timeout counter is based on the output sdclock. Tell the 593 * sdhci driver to recalculate the timeout clock whenever the output 594 * sdclock frequency changes. 595 */ 596 sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; 597 598 /* 599 * The MMCHS hardware shifts the 136-bit response data (in violation of 600 * the spec), so tell the sdhci driver not to do the same in software. 601 */ 602 sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE; 603 604 /* 605 * Reset bits are broken, have to wait to see the bits asserted 606 * before waiting to see them de-asserted. 607 */ 608 sc->slot.quirks |= SDHCI_QUIRK_WAITFOR_RESET_ASSERTED; 609 610 /* 611 * DMA is not really broken, I just haven't implemented it yet. 612 */ 613 sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; 614 615 /* 616 * Set up the hardware and go. Note that this sets many of the 617 * slot.host.* fields, so we have to do this before overriding any of 618 * those values based on fdt data, below. 619 */ 620 sdhci_init_slot(dev, &sc->slot, 0); 621 622 /* 623 * The SDHCI controller doesn't realize it, but we can support 8-bit 624 * even though we're not a v3.0 controller. If there's an fdt bus-width 625 * property, honor it. 626 */ 627 if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) { 628 sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA | 629 MMC_CAP_8_BIT_DATA); 630 switch (prop) { 631 case 8: 632 sc->slot.host.caps |= MMC_CAP_8_BIT_DATA; 633 /* FALLTHROUGH */ 634 case 4: 635 sc->slot.host.caps |= MMC_CAP_4_BIT_DATA; 636 break; 637 case 1: 638 break; 639 default: 640 device_printf(dev, "Bad bus-width value %u\n", prop); 641 break; 642 } 643 } 644 645 /* 646 * If the slot is flagged with the non-removable property, set our flag 647 * to always force the SDHCI_CARD_PRESENT bit on. 648 */ 649 node = ofw_bus_get_node(dev); 650 if (OF_hasprop(node, "non-removable")) 651 sc->force_card_present = true; 652 653 bus_generic_probe(dev); 654 bus_generic_attach(dev); 655 656 sdhci_start_slot(&sc->slot); 657 658 return (0); 659 660 fail: 661 if (sc->intr_cookie) 662 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); 663 if (sc->irq_res) 664 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 665 if (sc->mem_res) 666 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 667 668 return (err); 669 } 670 671 static int 672 ti_sdhci_probe(device_t dev) 673 { 674 675 if (!ofw_bus_status_okay(dev)) 676 return (ENXIO); 677 678 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 679 device_set_desc(dev, "TI MMCHS (SDHCI 2.0)"); 680 return (BUS_PROBE_DEFAULT); 681 } 682 683 return (ENXIO); 684 } 685 686 static device_method_t ti_sdhci_methods[] = { 687 /* Device interface */ 688 DEVMETHOD(device_probe, ti_sdhci_probe), 689 DEVMETHOD(device_attach, ti_sdhci_attach), 690 DEVMETHOD(device_detach, ti_sdhci_detach), 691 692 /* Bus interface */ 693 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 694 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 695 DEVMETHOD(bus_print_child, bus_generic_print_child), 696 697 /* MMC bridge interface */ 698 DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios), 699 DEVMETHOD(mmcbr_request, sdhci_generic_request), 700 DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro), 701 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 702 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 703 704 /* SDHCI registers accessors */ 705 DEVMETHOD(sdhci_read_1, ti_sdhci_read_1), 706 DEVMETHOD(sdhci_read_2, ti_sdhci_read_2), 707 DEVMETHOD(sdhci_read_4, ti_sdhci_read_4), 708 DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4), 709 DEVMETHOD(sdhci_write_1, ti_sdhci_write_1), 710 DEVMETHOD(sdhci_write_2, ti_sdhci_write_2), 711 DEVMETHOD(sdhci_write_4, ti_sdhci_write_4), 712 DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4), 713 DEVMETHOD(sdhci_get_card_present, ti_sdhci_get_card_present), 714 715 DEVMETHOD_END 716 }; 717 718 static devclass_t ti_sdhci_devclass; 719 720 static driver_t ti_sdhci_driver = { 721 "sdhci_ti", 722 ti_sdhci_methods, 723 sizeof(struct ti_sdhci_softc), 724 }; 725 726 DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, 0, 0); 727 MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1); 728 DRIVER_MODULE(mmc, sdhci_ti, mmc_driver, mmc_devclass, NULL, NULL); 729 MODULE_DEPEND(sdhci_ti, mmc, 1, 1, 1); 730