xref: /freebsd/sys/arm/ti/ti_scm_syscon.c (revision ddd30dd82b5e6eee3d073a1f5987a11c44ed9e7c)
10050ea24SMichal Meloun /*-
20050ea24SMichal Meloun  * Copyright (c) 2019 Emmanuel Vadot <manu@FreeBSD.org>
30050ea24SMichal Meloun  *
40050ea24SMichal Meloun  * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se>
50050ea24SMichal Meloun  *
60050ea24SMichal Meloun  * Redistribution and use in source and binary forms, with or without
70050ea24SMichal Meloun  * modification, are permitted provided that the following conditions
80050ea24SMichal Meloun  * are met:
90050ea24SMichal Meloun  * 1. Redistributions of source code must retain the above copyright
100050ea24SMichal Meloun  *    notice, this list of conditions and the following disclaimer.
110050ea24SMichal Meloun  * 2. Redistributions in binary form must reproduce the above copyright
120050ea24SMichal Meloun  *    notice, this list of conditions and the following disclaimer in the
130050ea24SMichal Meloun  *    documentation and/or other materials provided with the distribution.
140050ea24SMichal Meloun  *
150050ea24SMichal Meloun  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
160050ea24SMichal Meloun  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
170050ea24SMichal Meloun  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
180050ea24SMichal Meloun  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
190050ea24SMichal Meloun  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
200050ea24SMichal Meloun  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
210050ea24SMichal Meloun  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
220050ea24SMichal Meloun  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
230050ea24SMichal Meloun  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
240050ea24SMichal Meloun  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
250050ea24SMichal Meloun  * SUCH DAMAGE.
260050ea24SMichal Meloun  *
270050ea24SMichal Meloun  * $FreeBSD$
280050ea24SMichal Meloun  */
290050ea24SMichal Meloun /* Based on sys/arm/ti/ti_sysc.c */
300050ea24SMichal Meloun 
310050ea24SMichal Meloun #include <sys/cdefs.h>
320050ea24SMichal Meloun __FBSDID("$FreeBSD$");
330050ea24SMichal Meloun 
340050ea24SMichal Meloun #include <sys/param.h>
350050ea24SMichal Meloun #include <sys/systm.h>
360050ea24SMichal Meloun #include <sys/kernel.h>
370050ea24SMichal Meloun #include <sys/module.h>
380050ea24SMichal Meloun #include <sys/bus.h>
390050ea24SMichal Meloun #include <sys/resource.h>
400050ea24SMichal Meloun #include <sys/rman.h>
410050ea24SMichal Meloun #include <sys/lock.h>
420050ea24SMichal Meloun #include <sys/mutex.h>
430050ea24SMichal Meloun 
440050ea24SMichal Meloun #include <machine/bus.h>
450050ea24SMichal Meloun #include <machine/resource.h>
460050ea24SMichal Meloun 
470050ea24SMichal Meloun #include <dev/fdt/simplebus.h>
480050ea24SMichal Meloun 
490050ea24SMichal Meloun #include <dev/ofw/openfirm.h>
500050ea24SMichal Meloun #include <dev/ofw/ofw_bus.h>
510050ea24SMichal Meloun #include <dev/ofw/ofw_bus_subr.h>
520050ea24SMichal Meloun 
530050ea24SMichal Meloun #include "syscon_if.h"
540050ea24SMichal Meloun #include <dev/extres/syscon/syscon.h>
550050ea24SMichal Meloun #include "clkdev_if.h"
560050ea24SMichal Meloun 
57*ddd30dd8SIan Lepore #include <arm/ti/ti_cpuid.h>
58*ddd30dd8SIan Lepore 
590050ea24SMichal Meloun #if 0
600050ea24SMichal Meloun #define DPRINTF(dev, msg...) device_printf(dev, msg)
610050ea24SMichal Meloun #else
620050ea24SMichal Meloun #define DPRINTF(dev, msg...)
630050ea24SMichal Meloun #endif
640050ea24SMichal Meloun 
650050ea24SMichal Meloun MALLOC_DECLARE(M_SYSCON);
660050ea24SMichal Meloun 
670050ea24SMichal Meloun struct ti_scm_syscon_softc {
680050ea24SMichal Meloun 	struct simplebus_softc	sc_simplebus;
690050ea24SMichal Meloun 	device_t		dev;
700050ea24SMichal Meloun 	struct syscon *		syscon;
710050ea24SMichal Meloun 	struct resource *	res[1];
720050ea24SMichal Meloun 	bus_space_tag_t		bst;
730050ea24SMichal Meloun 	bus_space_handle_t	bsh;
740050ea24SMichal Meloun 	struct mtx		mtx;
750050ea24SMichal Meloun };
760050ea24SMichal Meloun 
770050ea24SMichal Meloun static struct resource_spec ti_scm_syscon_res_spec[] = {
780050ea24SMichal Meloun 	{ SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE },
790050ea24SMichal Meloun 	{ -1, 0 }
800050ea24SMichal Meloun };
810050ea24SMichal Meloun 
820050ea24SMichal Meloun /* Device */
830050ea24SMichal Meloun static struct ofw_compat_data compat_data[] = {
840050ea24SMichal Meloun 	{ "syscon",	1 },
850050ea24SMichal Meloun 	{ NULL,		0 }
860050ea24SMichal Meloun };
870050ea24SMichal Meloun 
880050ea24SMichal Meloun /* --- dev/extres/syscon syscon_method_t interface --- */
890050ea24SMichal Meloun static int
900050ea24SMichal Meloun ti_scm_syscon_write_4(struct syscon *syscon, bus_size_t offset, uint32_t val)
910050ea24SMichal Meloun {
920050ea24SMichal Meloun 	struct ti_scm_syscon_softc *sc;
930050ea24SMichal Meloun 
940050ea24SMichal Meloun 	sc = device_get_softc(syscon->pdev);
950050ea24SMichal Meloun 	DPRINTF(sc->dev, "offset=%lx write %x\n", offset, val);
960050ea24SMichal Meloun 	mtx_lock(&sc->mtx);
970050ea24SMichal Meloun 	bus_space_write_4(sc->bst, sc->bsh, offset, val);
980050ea24SMichal Meloun 	mtx_unlock(&sc->mtx);
990050ea24SMichal Meloun 	return (0);
1000050ea24SMichal Meloun }
1010050ea24SMichal Meloun 
1020050ea24SMichal Meloun static uint32_t
1030050ea24SMichal Meloun ti_scm_syscon_read_4(struct syscon *syscon, bus_size_t offset)
1040050ea24SMichal Meloun {
1050050ea24SMichal Meloun 	struct ti_scm_syscon_softc *sc;
1060050ea24SMichal Meloun 	uint32_t val;
1070050ea24SMichal Meloun 
1080050ea24SMichal Meloun 	sc = device_get_softc(syscon->pdev);
1090050ea24SMichal Meloun 
1100050ea24SMichal Meloun 	mtx_lock(&sc->mtx);
1110050ea24SMichal Meloun 	val = bus_space_read_4(sc->bst, sc->bsh, offset);
1120050ea24SMichal Meloun 	mtx_unlock(&sc->mtx);
1130050ea24SMichal Meloun 	DPRINTF(sc->dev, "offset=%lx Read %x\n", offset, val);
1140050ea24SMichal Meloun 	return (val);
1150050ea24SMichal Meloun }
1160050ea24SMichal Meloun static int
1170050ea24SMichal Meloun ti_scm_syscon_modify_4(struct syscon *syscon, bus_size_t offset, uint32_t clr, uint32_t set)
1180050ea24SMichal Meloun {
1190050ea24SMichal Meloun 	struct ti_scm_syscon_softc *sc;
1200050ea24SMichal Meloun 	uint32_t reg;
1210050ea24SMichal Meloun 
1220050ea24SMichal Meloun 	sc = device_get_softc(syscon->pdev);
1230050ea24SMichal Meloun 
1240050ea24SMichal Meloun 	mtx_lock(&sc->mtx);
1250050ea24SMichal Meloun 	reg = bus_space_read_4(sc->bst, sc->bsh, offset);
1260050ea24SMichal Meloun 	reg &= ~clr;
1270050ea24SMichal Meloun 	reg |= set;
1280050ea24SMichal Meloun 	bus_space_write_4(sc->bst, sc->bsh, offset, reg);
1290050ea24SMichal Meloun 	mtx_unlock(&sc->mtx);
1300050ea24SMichal Meloun 	DPRINTF(sc->dev, "offset=%lx reg: %x (clr %x set %x)\n", offset, reg, clr, set);
1310050ea24SMichal Meloun 
1320050ea24SMichal Meloun 	return (0);
1330050ea24SMichal Meloun }
1340050ea24SMichal Meloun 
1350050ea24SMichal Meloun static syscon_method_t ti_scm_syscon_reg_methods[] = {
1360050ea24SMichal Meloun 	SYSCONMETHOD(syscon_read_4,	ti_scm_syscon_read_4),
1370050ea24SMichal Meloun 	SYSCONMETHOD(syscon_write_4,	ti_scm_syscon_write_4),
1380050ea24SMichal Meloun 	SYSCONMETHOD(syscon_modify_4,	ti_scm_syscon_modify_4),
1390050ea24SMichal Meloun 
1400050ea24SMichal Meloun 	SYSCONMETHOD_END
1410050ea24SMichal Meloun };
1420050ea24SMichal Meloun 
1430050ea24SMichal Meloun DEFINE_CLASS_1(ti_scm_syscon_reg, ti_scm_syscon_reg_class, ti_scm_syscon_reg_methods,
1440050ea24SMichal Meloun     0, syscon_class);
1450050ea24SMichal Meloun 
1460050ea24SMichal Meloun /* device interface */
1470050ea24SMichal Meloun static int
1480050ea24SMichal Meloun ti_scm_syscon_probe(device_t dev)
1490050ea24SMichal Meloun {
1500050ea24SMichal Meloun 	if (!ofw_bus_status_okay(dev))
1510050ea24SMichal Meloun 		return (ENXIO);
1520050ea24SMichal Meloun 
153*ddd30dd8SIan Lepore 	if (!ti_soc_is_supported())
154*ddd30dd8SIan Lepore 		return (ENXIO);
155*ddd30dd8SIan Lepore 
1560050ea24SMichal Meloun 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1570050ea24SMichal Meloun 		return (ENXIO);
1580050ea24SMichal Meloun 
1590050ea24SMichal Meloun 	device_set_desc(dev, "TI OMAP Control Module Syscon");
1600050ea24SMichal Meloun 	return(BUS_PROBE_DEFAULT);
1610050ea24SMichal Meloun }
1620050ea24SMichal Meloun 
1630050ea24SMichal Meloun static int
1640050ea24SMichal Meloun ti_scm_syscon_attach(device_t dev)
1650050ea24SMichal Meloun {
1660050ea24SMichal Meloun 	struct ti_scm_syscon_softc *sc;
1670050ea24SMichal Meloun 	phandle_t node, child;
1680050ea24SMichal Meloun 	int err;
1690050ea24SMichal Meloun 
1700050ea24SMichal Meloun  	sc = device_get_softc(dev);
1710050ea24SMichal Meloun 	sc->dev = dev;
1720050ea24SMichal Meloun 
1730050ea24SMichal Meloun 	if (bus_alloc_resources(dev, ti_scm_syscon_res_spec, sc->res)) {
1740050ea24SMichal Meloun 		device_printf(sc->dev, "Cant allocate resources\n");
1750050ea24SMichal Meloun 		return (ENXIO);
1760050ea24SMichal Meloun 	}
1770050ea24SMichal Meloun 
1780050ea24SMichal Meloun 	sc->dev = dev;
1790050ea24SMichal Meloun 	sc->bst = rman_get_bustag(sc->res[0]);
1800050ea24SMichal Meloun 	sc->bsh = rman_get_bushandle(sc->res[0]);
1810050ea24SMichal Meloun 
1820050ea24SMichal Meloun 	mtx_init(&sc->mtx, device_get_nameunit(sc->dev), NULL, MTX_DEF);
1830050ea24SMichal Meloun 	node = ofw_bus_get_node(sc->dev);
1840050ea24SMichal Meloun 
1850050ea24SMichal Meloun 	/* dev/extres/syscon interface */
1860050ea24SMichal Meloun 	sc->syscon = syscon_create_ofw_node(dev, &ti_scm_syscon_reg_class, node);
1870050ea24SMichal Meloun 	if (sc->syscon == NULL) {
1880050ea24SMichal Meloun 		device_printf(dev, "Failed to create/register syscon\n");
1890050ea24SMichal Meloun 		return (ENXIO);
1900050ea24SMichal Meloun 	}
1910050ea24SMichal Meloun 
1920050ea24SMichal Meloun 	simplebus_init(sc->dev, node);
1930050ea24SMichal Meloun 
1940050ea24SMichal Meloun 	err = bus_generic_probe(sc->dev);
1950050ea24SMichal Meloun 	for (child = OF_child(node); child != 0; child = OF_peer(child)) {
1960050ea24SMichal Meloun 		simplebus_add_device(sc->dev, child, 0, NULL, -1, NULL);
1970050ea24SMichal Meloun 	}
1980050ea24SMichal Meloun 
1990050ea24SMichal Meloun 	return (bus_generic_attach(sc->dev));
2000050ea24SMichal Meloun }
2010050ea24SMichal Meloun 
2020050ea24SMichal Meloun /* syscon interface */
2030050ea24SMichal Meloun static int
2040050ea24SMichal Meloun ti_scm_syscon_get_handle(device_t dev, struct syscon **syscon)
2050050ea24SMichal Meloun {
2060050ea24SMichal Meloun 	struct ti_scm_syscon_softc *sc;
2070050ea24SMichal Meloun 
2080050ea24SMichal Meloun 	sc = device_get_softc(dev);
2090050ea24SMichal Meloun 	*syscon = sc->syscon;
2100050ea24SMichal Meloun 	if (*syscon == NULL)
2110050ea24SMichal Meloun 		return (ENODEV);
2120050ea24SMichal Meloun 	return (0);
2130050ea24SMichal Meloun }
2140050ea24SMichal Meloun 
2150050ea24SMichal Meloun /* clkdev interface */
2160050ea24SMichal Meloun static int
2170050ea24SMichal Meloun ti_scm_syscon_clk_write_4(device_t dev, bus_addr_t addr, uint32_t val)
2180050ea24SMichal Meloun {
2190050ea24SMichal Meloun 	struct ti_scm_syscon_softc *sc;
2200050ea24SMichal Meloun 
2210050ea24SMichal Meloun 	sc = device_get_softc(dev);
2220050ea24SMichal Meloun 	DPRINTF(sc->dev, "offset=%lx write %x\n", addr, val);
2230050ea24SMichal Meloun 	bus_space_write_4(sc->bst, sc->bsh, addr, val);
2240050ea24SMichal Meloun 	return (0);
2250050ea24SMichal Meloun }
2260050ea24SMichal Meloun 
2270050ea24SMichal Meloun static int
2280050ea24SMichal Meloun ti_scm_syscon_clk_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
2290050ea24SMichal Meloun {
2300050ea24SMichal Meloun 	struct ti_scm_syscon_softc *sc;
2310050ea24SMichal Meloun 
2320050ea24SMichal Meloun 	sc = device_get_softc(dev);
2330050ea24SMichal Meloun 
2340050ea24SMichal Meloun 	*val = bus_space_read_4(sc->bst, sc->bsh, addr);
2350050ea24SMichal Meloun 	DPRINTF(sc->dev, "offset=%lx Read %x\n", addr, *val);
2360050ea24SMichal Meloun 	return (0);
2370050ea24SMichal Meloun }
2380050ea24SMichal Meloun 
2390050ea24SMichal Meloun static int
2400050ea24SMichal Meloun ti_scm_syscon_clk_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set)
2410050ea24SMichal Meloun {
2420050ea24SMichal Meloun 	struct ti_scm_syscon_softc *sc;
2430050ea24SMichal Meloun 	uint32_t reg;
2440050ea24SMichal Meloun 
2450050ea24SMichal Meloun 	sc = device_get_softc(dev);
2460050ea24SMichal Meloun 
2470050ea24SMichal Meloun 	reg = bus_space_read_4(sc->bst, sc->bsh, addr);
2480050ea24SMichal Meloun 	reg &= ~clr;
2490050ea24SMichal Meloun 	reg |= set;
2500050ea24SMichal Meloun 	bus_space_write_4(sc->bst, sc->bsh, addr, reg);
2510050ea24SMichal Meloun 	DPRINTF(sc->dev, "offset=%lx reg: %x (clr %x set %x)\n", addr, reg, clr, set);
2520050ea24SMichal Meloun 
2530050ea24SMichal Meloun 	return (0);
2540050ea24SMichal Meloun }
2550050ea24SMichal Meloun 
2560050ea24SMichal Meloun static void
2570050ea24SMichal Meloun ti_scm_syscon_clk_device_lock(device_t dev)
2580050ea24SMichal Meloun {
2590050ea24SMichal Meloun 	struct ti_scm_syscon_softc *sc;
2600050ea24SMichal Meloun 
2610050ea24SMichal Meloun 	sc = device_get_softc(dev);
2620050ea24SMichal Meloun 	mtx_lock(&sc->mtx);
2630050ea24SMichal Meloun }
2640050ea24SMichal Meloun 
2650050ea24SMichal Meloun static void
2660050ea24SMichal Meloun ti_scm_syscon_clk_device_unlock(device_t dev)
2670050ea24SMichal Meloun {
2680050ea24SMichal Meloun 	struct ti_scm_syscon_softc *sc;
2690050ea24SMichal Meloun 	sc = device_get_softc(dev);
2700050ea24SMichal Meloun 	mtx_unlock(&sc->mtx);
2710050ea24SMichal Meloun }
2720050ea24SMichal Meloun 
2730050ea24SMichal Meloun static device_method_t ti_scm_syscon_methods[] = {
2740050ea24SMichal Meloun 	DEVMETHOD(device_probe,		ti_scm_syscon_probe),
2750050ea24SMichal Meloun 	DEVMETHOD(device_attach,	ti_scm_syscon_attach),
2760050ea24SMichal Meloun 
2770050ea24SMichal Meloun 	/* syscon interface */
2780050ea24SMichal Meloun 	DEVMETHOD(syscon_get_handle,	ti_scm_syscon_get_handle),
2790050ea24SMichal Meloun 
2800050ea24SMichal Meloun 	/* clkdev interface */
2810050ea24SMichal Meloun 	DEVMETHOD(clkdev_write_4,	ti_scm_syscon_clk_write_4),
2820050ea24SMichal Meloun 	DEVMETHOD(clkdev_read_4,	ti_scm_syscon_clk_read_4),
2830050ea24SMichal Meloun 	DEVMETHOD(clkdev_modify_4,	ti_scm_syscon_clk_modify_4),
2840050ea24SMichal Meloun 	DEVMETHOD(clkdev_device_lock,	ti_scm_syscon_clk_device_lock),
2850050ea24SMichal Meloun 	DEVMETHOD(clkdev_device_unlock,	ti_scm_syscon_clk_device_unlock),
2860050ea24SMichal Meloun 
2870050ea24SMichal Meloun 	DEVMETHOD_END
2880050ea24SMichal Meloun };
2890050ea24SMichal Meloun 
2900050ea24SMichal Meloun DEFINE_CLASS_1(ti_scm_syscon, ti_scm_syscon_driver, ti_scm_syscon_methods,
2910050ea24SMichal Meloun     sizeof(struct ti_scm_syscon_softc), simplebus_driver);
2920050ea24SMichal Meloun 
2930050ea24SMichal Meloun static devclass_t ti_scm_syscon_devclass;
2940050ea24SMichal Meloun 
2950050ea24SMichal Meloun EARLY_DRIVER_MODULE(ti_scm_syscon, simplebus, ti_scm_syscon_driver,
2960050ea24SMichal Meloun     ti_scm_syscon_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
2970050ea24SMichal Meloun MODULE_VERSION(ti_scm_syscon, 1);
2980050ea24SMichal Meloun MODULE_DEPEND(ti_scm_syscon, ti_scm, 1, 1, 1);
299