xref: /freebsd/sys/arm/ti/ti_prcm.c (revision 18250ec6c089c0c50cbd9fd87d78e03ff89916df)
1af3dc4a7SPedro F. Giffuni /*-
24d846d26SWarner Losh  * SPDX-License-Identifier: BSD-2-Clause
3af3dc4a7SPedro F. Giffuni  *
40050ea24SMichal Meloun  * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
50050ea24SMichal Meloun  * All rights reserved.
60050ea24SMichal Meloun  *
70050ea24SMichal Meloun  * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se>
80050ea24SMichal Meloun  *
90050ea24SMichal Meloun  * Redistribution and use in source and binary forms, with or without
100050ea24SMichal Meloun  * modification, are permitted provided that the following conditions
110050ea24SMichal Meloun  * are met:
120050ea24SMichal Meloun  * 1. Redistributions of source code must retain the above copyright
130050ea24SMichal Meloun  *    notice, this list of conditions and the following disclaimer.
140050ea24SMichal Meloun  * 2. Redistributions in binary form must reproduce the above copyright
150050ea24SMichal Meloun  *    notice, this list of conditions and the following disclaimer in the
160050ea24SMichal Meloun  *    documentation and/or other materials provided with the distribution.
170050ea24SMichal Meloun  *
180050ea24SMichal Meloun  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
190050ea24SMichal Meloun  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
200050ea24SMichal Meloun  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
210050ea24SMichal Meloun  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
220050ea24SMichal Meloun  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
230050ea24SMichal Meloun  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
240050ea24SMichal Meloun  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
250050ea24SMichal Meloun  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
260050ea24SMichal Meloun  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
270050ea24SMichal Meloun  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
280050ea24SMichal Meloun  * SUCH DAMAGE.
290050ea24SMichal Meloun  */
300050ea24SMichal Meloun 
310050ea24SMichal Meloun /* Based on sys/arm/ti/am335x/am335x_prcm.c */
320050ea24SMichal Meloun 
330050ea24SMichal Meloun #include <sys/param.h>
340050ea24SMichal Meloun #include <sys/systm.h>
350050ea24SMichal Meloun #include <sys/bus.h>
360050ea24SMichal Meloun #include <sys/kernel.h>
370050ea24SMichal Meloun #include <sys/module.h>
380050ea24SMichal Meloun #include <sys/malloc.h>
390050ea24SMichal Meloun #include <sys/rman.h>
400050ea24SMichal Meloun #include <sys/timeet.h>
410050ea24SMichal Meloun #include <sys/timetc.h>
420050ea24SMichal Meloun #include <sys/watchdog.h>
430050ea24SMichal Meloun #include <machine/bus.h>
440050ea24SMichal Meloun #include <machine/cpu.h>
450050ea24SMichal Meloun #include <machine/intr.h>
460050ea24SMichal Meloun 
470050ea24SMichal Meloun #include <arm/ti/ti_cpuid.h>
480050ea24SMichal Meloun #include <arm/ti/ti_prcm.h>
490050ea24SMichal Meloun #include <arm/ti/tivar.h>
500050ea24SMichal Meloun 
510050ea24SMichal Meloun #include <dev/fdt/simplebus.h>
520050ea24SMichal Meloun 
530050ea24SMichal Meloun #include <dev/ofw/openfirm.h>
540050ea24SMichal Meloun #include <dev/ofw/ofw_bus.h>
550050ea24SMichal Meloun #include <dev/ofw/ofw_bus_subr.h>
560050ea24SMichal Meloun 
570050ea24SMichal Meloun #include "clkdev_if.h"
580050ea24SMichal Meloun 
590050ea24SMichal Meloun #if 0
600050ea24SMichal Meloun #define DPRINTF(dev, msg...) device_printf(dev, msg)
610050ea24SMichal Meloun #else
620050ea24SMichal Meloun #define DPRINTF(dev, msg...)
630050ea24SMichal Meloun #endif
640050ea24SMichal Meloun 
650050ea24SMichal Meloun struct ti_prcm_softc {
660050ea24SMichal Meloun 	struct simplebus_softc  sc_simplebus;
670050ea24SMichal Meloun 	device_t		dev;
680050ea24SMichal Meloun 	struct resource *	mem_res;
690050ea24SMichal Meloun 	bus_space_tag_t		bst;
700050ea24SMichal Meloun 	bus_space_handle_t	bsh;
710050ea24SMichal Meloun 	int			attach_done;
720050ea24SMichal Meloun 	struct mtx		mtx;
730050ea24SMichal Meloun };
740050ea24SMichal Meloun 
750050ea24SMichal Meloun static struct ti_prcm_softc *ti_prcm_sc = NULL;
760050ea24SMichal Meloun static void omap4_prcm_reset(void);
770050ea24SMichal Meloun static void am335x_prcm_reset(void);
780050ea24SMichal Meloun 
790050ea24SMichal Meloun #define TI_AM3_PRCM		18
800050ea24SMichal Meloun #define TI_AM4_PRCM		17
810050ea24SMichal Meloun #define TI_OMAP2_PRCM		16
820050ea24SMichal Meloun #define TI_OMAP3_PRM		15
830050ea24SMichal Meloun #define TI_OMAP3_CM		14
840050ea24SMichal Meloun #define TI_OMAP4_CM1		13
850050ea24SMichal Meloun #define TI_OMAP4_PRM		12
860050ea24SMichal Meloun #define TI_OMAP4_CM2		11
870050ea24SMichal Meloun #define TI_OMAP4_SCRM		10
880050ea24SMichal Meloun #define TI_OMAP5_PRM		9
890050ea24SMichal Meloun #define TI_OMAP5_CM_CORE_AON	8
900050ea24SMichal Meloun #define TI_OMAP5_SCRM		7
910050ea24SMichal Meloun #define TI_OMAP5_CM_CORE	6
920050ea24SMichal Meloun #define TI_DRA7_PRM		5
930050ea24SMichal Meloun #define TI_DRA7_CM_CORE_AON	4
940050ea24SMichal Meloun #define TI_DRA7_CM_CORE		3
950050ea24SMichal Meloun #define TI_DM814_PRCM		2
960050ea24SMichal Meloun #define TI_DM816_PRCM		1
970050ea24SMichal Meloun #define TI_PRCM_END		0
980050ea24SMichal Meloun 
990050ea24SMichal Meloun static struct ofw_compat_data compat_data[] = {
1000050ea24SMichal Meloun 	{ "ti,am3-prcm",		TI_AM3_PRCM },
1010050ea24SMichal Meloun 	{ "ti,am4-prcm",		TI_AM4_PRCM },
1020050ea24SMichal Meloun 	{ "ti,omap2-prcm",		TI_OMAP2_PRCM },
1030050ea24SMichal Meloun 	{ "ti,omap3-prm",		TI_OMAP3_PRM },
1040050ea24SMichal Meloun 	{ "ti,omap3-cm",		TI_OMAP3_CM },
1050050ea24SMichal Meloun 	{ "ti,omap4-cm1",		TI_OMAP4_CM1 },
1060050ea24SMichal Meloun 	{ "ti,omap4-prm",		TI_OMAP4_PRM },
1070050ea24SMichal Meloun 	{ "ti,omap4-cm2",		TI_OMAP4_CM2 },
1080050ea24SMichal Meloun 	{ "ti,omap4-scrm",		TI_OMAP4_SCRM },
1090050ea24SMichal Meloun 	{ "ti,omap5-prm",		TI_OMAP5_PRM },
1100050ea24SMichal Meloun 	{ "ti,omap5-cm-core-aon",	TI_OMAP5_CM_CORE_AON },
1110050ea24SMichal Meloun 	{ "ti,omap5-scrm",		TI_OMAP5_SCRM },
1120050ea24SMichal Meloun 	{ "ti,omap5-cm-core",		TI_OMAP5_CM_CORE },
1130050ea24SMichal Meloun 	{ "ti,dra7-prm",		TI_DRA7_PRM },
1140050ea24SMichal Meloun 	{ "ti,dra7-cm-core-aon",	TI_DRA7_CM_CORE_AON },
1150050ea24SMichal Meloun 	{ "ti,dra7-cm-core",		TI_DRA7_CM_CORE },
1160050ea24SMichal Meloun 	{ "ti,dm814-prcm",		TI_DM814_PRCM },
1170050ea24SMichal Meloun 	{ "ti,dm816-prcm",		TI_DM816_PRCM },
1180050ea24SMichal Meloun 	{ NULL,				TI_PRCM_END}
1190050ea24SMichal Meloun };
1200050ea24SMichal Meloun 
1210050ea24SMichal Meloun static int
ti_prcm_probe(device_t dev)1220050ea24SMichal Meloun ti_prcm_probe(device_t dev)
1230050ea24SMichal Meloun {
1240050ea24SMichal Meloun 	if (!ofw_bus_status_okay(dev))
1250050ea24SMichal Meloun 		return (ENXIO);
1260050ea24SMichal Meloun 
1270050ea24SMichal Meloun 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) {
1280050ea24SMichal Meloun 		return (ENXIO);
1290050ea24SMichal Meloun 	}
1300050ea24SMichal Meloun 
1310050ea24SMichal Meloun 	device_set_desc(dev, "TI Power and Clock Management");
1320050ea24SMichal Meloun 	return(BUS_PROBE_DEFAULT);
1330050ea24SMichal Meloun }
1340050ea24SMichal Meloun 
1350050ea24SMichal Meloun static int
ti_prcm_attach(device_t dev)1360050ea24SMichal Meloun ti_prcm_attach(device_t dev)
1370050ea24SMichal Meloun {
1380050ea24SMichal Meloun 	struct ti_prcm_softc *sc;
1390050ea24SMichal Meloun 	phandle_t node, child;
1400050ea24SMichal Meloun 	int rid;
1410050ea24SMichal Meloun 
1420050ea24SMichal Meloun 	sc = device_get_softc(dev);
1430050ea24SMichal Meloun 	sc->dev = dev;
1440050ea24SMichal Meloun 
1450050ea24SMichal Meloun 	node = ofw_bus_get_node(sc->dev);
1460050ea24SMichal Meloun 	simplebus_init(sc->dev, node);
1470050ea24SMichal Meloun 
1480050ea24SMichal Meloun 	if (simplebus_fill_ranges(node, &sc->sc_simplebus) < 0) {
1490050ea24SMichal Meloun 		device_printf(sc->dev, "could not get ranges\n");
1500050ea24SMichal Meloun 		return (ENXIO);
1510050ea24SMichal Meloun 	}
1520050ea24SMichal Meloun 	if (sc->sc_simplebus.nranges == 0) {
1530050ea24SMichal Meloun 		device_printf(sc->dev, "nranges == 0\n");
1540050ea24SMichal Meloun 		return (ENXIO);
1550050ea24SMichal Meloun 	}
1560050ea24SMichal Meloun 
1570050ea24SMichal Meloun 	sc->mem_res = bus_alloc_resource(sc->dev, SYS_RES_MEMORY, &rid,
1580050ea24SMichal Meloun 		sc->sc_simplebus.ranges[0].host,
1590050ea24SMichal Meloun 		(sc->sc_simplebus.ranges[0].host +
1600050ea24SMichal Meloun 			sc->sc_simplebus.ranges[0].size - 1),
1610050ea24SMichal Meloun 		sc->sc_simplebus.ranges[0].size,
1620050ea24SMichal Meloun 		RF_ACTIVE | RF_SHAREABLE);
1630050ea24SMichal Meloun 
1640050ea24SMichal Meloun 	if (sc->mem_res == NULL) {
1650050ea24SMichal Meloun 		return (ENXIO);
1660050ea24SMichal Meloun 	}
1670050ea24SMichal Meloun 
1680050ea24SMichal Meloun 	sc->bst = rman_get_bustag(sc->mem_res);
1690050ea24SMichal Meloun 	sc->bsh = rman_get_bushandle(sc->mem_res);
1700050ea24SMichal Meloun 
1710050ea24SMichal Meloun 	mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
1720050ea24SMichal Meloun 
1730050ea24SMichal Meloun 	/* Fixme: for xxx_prcm_reset functions.
1740050ea24SMichal Meloun 	 * Get rid of global variables?
1750050ea24SMichal Meloun 	 */
1760050ea24SMichal Meloun 	ti_prcm_sc = sc;
1770050ea24SMichal Meloun 
1780050ea24SMichal Meloun 	switch(ti_chip()) {
1790050ea24SMichal Meloun #ifdef SOC_OMAP4
1800050ea24SMichal Meloun 	case CHIP_OMAP_4:
1810050ea24SMichal Meloun 		ti_cpu_reset = omap4_prcm_reset;
1820050ea24SMichal Meloun 		break;
1830050ea24SMichal Meloun #endif
1840050ea24SMichal Meloun #ifdef SOC_TI_AM335X
1850050ea24SMichal Meloun 	case CHIP_AM335X:
1860050ea24SMichal Meloun 		ti_cpu_reset = am335x_prcm_reset;
1870050ea24SMichal Meloun 		break;
1880050ea24SMichal Meloun #endif
1890050ea24SMichal Meloun 	}
1900050ea24SMichal Meloun 
191723da5d9SJohn Baldwin 	bus_identify_children(sc->dev);
1920050ea24SMichal Meloun 	for (child = OF_child(node); child != 0; child = OF_peer(child)) {
1930050ea24SMichal Meloun 		simplebus_add_device(dev, child, 0, NULL, -1, NULL);
1940050ea24SMichal Meloun 	}
195*18250ec6SJohn Baldwin 	bus_attach_children(sc->dev);
196*18250ec6SJohn Baldwin 	return (0);
1970050ea24SMichal Meloun }
1980050ea24SMichal Meloun 
1990050ea24SMichal Meloun int
ti_prcm_write_4(device_t dev,bus_addr_t addr,uint32_t val)2000050ea24SMichal Meloun ti_prcm_write_4(device_t dev, bus_addr_t addr, uint32_t val)
2010050ea24SMichal Meloun {
2020050ea24SMichal Meloun 	struct ti_prcm_softc *sc;
2030050ea24SMichal Meloun 
2040050ea24SMichal Meloun 	sc = device_get_softc(dev);
2050050ea24SMichal Meloun 	DPRINTF(sc->dev, "offset=%lx write %x\n", addr, val);
2060050ea24SMichal Meloun 	bus_space_write_4(sc->bst, sc->bsh, addr, val);
2070050ea24SMichal Meloun 	return (0);
2080050ea24SMichal Meloun }
2090050ea24SMichal Meloun int
ti_prcm_read_4(device_t dev,bus_addr_t addr,uint32_t * val)2100050ea24SMichal Meloun ti_prcm_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
2110050ea24SMichal Meloun {
2120050ea24SMichal Meloun 	struct ti_prcm_softc *sc;
2130050ea24SMichal Meloun 
2140050ea24SMichal Meloun 	sc = device_get_softc(dev);
2150050ea24SMichal Meloun 
2160050ea24SMichal Meloun 	*val = bus_space_read_4(sc->bst, sc->bsh, addr);
2170050ea24SMichal Meloun 	DPRINTF(sc->dev, "offset=%lx Read %x\n", addr, *val);
2180050ea24SMichal Meloun 	return (0);
2190050ea24SMichal Meloun }
2200050ea24SMichal Meloun 
2210050ea24SMichal Meloun int
ti_prcm_modify_4(device_t dev,bus_addr_t addr,uint32_t clr,uint32_t set)2220050ea24SMichal Meloun ti_prcm_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set)
2230050ea24SMichal Meloun {
2240050ea24SMichal Meloun 	struct ti_prcm_softc *sc;
2250050ea24SMichal Meloun 	uint32_t reg;
2260050ea24SMichal Meloun 
2270050ea24SMichal Meloun 	sc = device_get_softc(dev);
2280050ea24SMichal Meloun 
2290050ea24SMichal Meloun 	reg = bus_space_read_4(sc->bst, sc->bsh, addr);
2300050ea24SMichal Meloun 	reg &= ~clr;
2310050ea24SMichal Meloun 	reg |= set;
2320050ea24SMichal Meloun 	bus_space_write_4(sc->bst, sc->bsh, addr, reg);
2330050ea24SMichal Meloun 	DPRINTF(sc->dev, "offset=%lx reg: %x (clr %x set %x)\n", addr, reg, clr, set);
2340050ea24SMichal Meloun 
2350050ea24SMichal Meloun 	return (0);
2360050ea24SMichal Meloun }
2370050ea24SMichal Meloun 
2380050ea24SMichal Meloun void
ti_prcm_device_lock(device_t dev)2390050ea24SMichal Meloun ti_prcm_device_lock(device_t dev)
2400050ea24SMichal Meloun {
2410050ea24SMichal Meloun 	struct ti_prcm_softc *sc;
2420050ea24SMichal Meloun 
2430050ea24SMichal Meloun 	sc = device_get_softc(dev);
2440050ea24SMichal Meloun 	mtx_lock(&sc->mtx);
2450050ea24SMichal Meloun }
2460050ea24SMichal Meloun 
2470050ea24SMichal Meloun void
ti_prcm_device_unlock(device_t dev)2480050ea24SMichal Meloun ti_prcm_device_unlock(device_t dev)
2490050ea24SMichal Meloun {
2500050ea24SMichal Meloun 	struct ti_prcm_softc *sc;
2510050ea24SMichal Meloun 
2520050ea24SMichal Meloun 	sc = device_get_softc(dev);
2530050ea24SMichal Meloun 	mtx_unlock(&sc->mtx);
2540050ea24SMichal Meloun }
2550050ea24SMichal Meloun 
2560050ea24SMichal Meloun static device_method_t ti_prcm_methods[] = {
2570050ea24SMichal Meloun 	DEVMETHOD(device_probe,		ti_prcm_probe),
2580050ea24SMichal Meloun 	DEVMETHOD(device_attach,	ti_prcm_attach),
2590050ea24SMichal Meloun 
2600050ea24SMichal Meloun 	/* clkdev interface */
2610050ea24SMichal Meloun 	DEVMETHOD(clkdev_write_4,	ti_prcm_write_4),
2620050ea24SMichal Meloun 	DEVMETHOD(clkdev_read_4,	ti_prcm_read_4),
2630050ea24SMichal Meloun 	DEVMETHOD(clkdev_modify_4,	ti_prcm_modify_4),
2640050ea24SMichal Meloun 	DEVMETHOD(clkdev_device_lock,	ti_prcm_device_lock),
2650050ea24SMichal Meloun 	DEVMETHOD(clkdev_device_unlock, ti_prcm_device_unlock),
2660050ea24SMichal Meloun 
2670050ea24SMichal Meloun 	DEVMETHOD_END
2680050ea24SMichal Meloun };
2690050ea24SMichal Meloun 
2700050ea24SMichal Meloun DEFINE_CLASS_1(ti_prcm, ti_prcm_driver, ti_prcm_methods,
2710050ea24SMichal Meloun     sizeof(struct ti_prcm_softc), simplebus_driver);
2720050ea24SMichal Meloun 
2738537e671SJohn Baldwin EARLY_DRIVER_MODULE(ti_prcm, ofwbus, ti_prcm_driver, 0, 0, BUS_PASS_BUS);
2748537e671SJohn Baldwin EARLY_DRIVER_MODULE(ti_prcm, simplebus, ti_prcm_driver, 0, 0,
2758537e671SJohn Baldwin     BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
2760050ea24SMichal Meloun MODULE_VERSION(ti_prcm, 1);
2770050ea24SMichal Meloun MODULE_DEPEND(ti_prcm, ti_scm, 1, 1, 1);
2780050ea24SMichal Meloun 
2790050ea24SMichal Meloun /* From sys/arm/ti/am335x/am335x_prcm.c
2800050ea24SMichal Meloun  * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
2810050ea24SMichal Meloun  */
2820050ea24SMichal Meloun #define PRM_DEVICE_OFFSET		0xF00
2830050ea24SMichal Meloun #define AM335x_PRM_RSTCTRL		(PRM_DEVICE_OFFSET + 0x00)
2840050ea24SMichal Meloun 
2850050ea24SMichal Meloun static void
am335x_prcm_reset(void)2860050ea24SMichal Meloun am335x_prcm_reset(void)
2870050ea24SMichal Meloun {
2880050ea24SMichal Meloun 	ti_prcm_write_4(ti_prcm_sc->dev, AM335x_PRM_RSTCTRL, (1<<1));
2890050ea24SMichal Meloun }
2900050ea24SMichal Meloun 
2910050ea24SMichal Meloun /* FIXME: Is this correct - or should the license part be ontop? */
2920050ea24SMichal Meloun 
2930050ea24SMichal Meloun /* From sys/arm/ti/omap4/omap4_prcm_clks.c */
2940050ea24SMichal Meloun /*-
2950050ea24SMichal Meloun  * SPDX-License-Identifier: BSD-3-Clause
2960050ea24SMichal Meloun  *
2970050ea24SMichal Meloun  * Copyright (c) 2011
298e53470feSOleksandr Tymoshenko  *      Ben Gray <ben.r.gray@gmail.com>.
299e53470feSOleksandr Tymoshenko  * All rights reserved.
300e53470feSOleksandr Tymoshenko  *
301e53470feSOleksandr Tymoshenko  * Redistribution and use in source and binary forms, with or without
302e53470feSOleksandr Tymoshenko  * modification, are permitted provided that the following conditions
303e53470feSOleksandr Tymoshenko  * are met:
304e53470feSOleksandr Tymoshenko  * 1. Redistributions of source code must retain the above copyright
305e53470feSOleksandr Tymoshenko  *    notice, this list of conditions and the following disclaimer.
306e53470feSOleksandr Tymoshenko  * 2. Redistributions in binary form must reproduce the above copyright
307e53470feSOleksandr Tymoshenko  *    notice, this list of conditions and the following disclaimer in the
308e53470feSOleksandr Tymoshenko  *    documentation and/or other materials provided with the distribution.
3090050ea24SMichal Meloun  * 3. The name of the company nor the name of the author may be used to
310e53470feSOleksandr Tymoshenko  *    endorse or promote products derived from this software without specific
311e53470feSOleksandr Tymoshenko  *    prior written permission.
312e53470feSOleksandr Tymoshenko  *
313e53470feSOleksandr Tymoshenko  * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR
314e53470feSOleksandr Tymoshenko  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
315e53470feSOleksandr Tymoshenko  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
316e53470feSOleksandr Tymoshenko  * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
317e53470feSOleksandr Tymoshenko  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
318e53470feSOleksandr Tymoshenko  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
319e53470feSOleksandr Tymoshenko  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
320e53470feSOleksandr Tymoshenko  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
321e53470feSOleksandr Tymoshenko  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
322e53470feSOleksandr Tymoshenko  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
323e53470feSOleksandr Tymoshenko  */
3240050ea24SMichal Meloun #define PRM_RSTCTRL		0x1b00
3250050ea24SMichal Meloun #define PRM_RSTCTRL_RESET	0x2
326e53470feSOleksandr Tymoshenko 
3270050ea24SMichal Meloun static void
omap4_prcm_reset(void)3280050ea24SMichal Meloun omap4_prcm_reset(void)
329e53470feSOleksandr Tymoshenko {
3300050ea24SMichal Meloun 	uint32_t reg;
331e53470feSOleksandr Tymoshenko 
3320050ea24SMichal Meloun 	ti_prcm_read_4(ti_prcm_sc->dev, PRM_RSTCTRL, &reg);
3330050ea24SMichal Meloun 	reg = reg | PRM_RSTCTRL_RESET;
3340050ea24SMichal Meloun 	ti_prcm_write_4(ti_prcm_sc->dev, PRM_RSTCTRL, reg);
3350050ea24SMichal Meloun 	ti_prcm_read_4(ti_prcm_sc->dev, PRM_RSTCTRL, &reg);
336e53470feSOleksandr Tymoshenko }
337