1 /*- 2 * Copyright (c) 2011 3 * Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _TI_I2C_H_ 31 #define _TI_I2C_H_ 32 33 /** 34 * Header file for the OMAP I2C driver. 35 * 36 * Simply contains register bit flags. 37 */ 38 39 /* 40 * OMAP4 I2C Registers, Summary 1 41 */ 42 #define I2C_REG_IE 0x84 43 #define I2C_IE_XDR (1UL << 14) /* Transmit draining interrupt */ 44 #define I2C_IE_RDR (1UL << 13) /* Receive draining interrupt */ 45 #define I2C_IE_AAS (1UL << 9) /* Addressed as Slave interrupt */ 46 #define I2C_IE_BF (1UL << 8) /* Bus Free interrupt */ 47 #define I2C_IE_AERR (1UL << 7) /* Access Error interrupt */ 48 #define I2C_IE_STC (1UL << 6) /* Start Condition interrupt */ 49 #define I2C_IE_GC (1UL << 5) /* General Call interrupt */ 50 #define I2C_IE_XRDY (1UL << 4) /* Transmit Data Ready interrupt */ 51 #define I2C_IE_RRDY (1UL << 3) /* Receive Data Ready interrupt */ 52 #define I2C_IE_ARDY (1UL << 2) /* Register Access Ready interrupt */ 53 #define I2C_IE_NACK (1UL << 1) /* No Acknowledgment interrupt */ 54 #define I2C_IE_AL (1UL << 0) /* Arbitration Lost interrupt */ 55 #define I2C_REG_STAT 0x88 56 #define I2C_STAT_XDR (1UL << 14) 57 #define I2C_STAT_RDR (1UL << 13) 58 #define I2C_STAT_BB (1UL << 12) 59 #define I2C_STAT_ROVR (1UL << 11) 60 #define I2C_STAT_XUDF (1UL << 10) 61 #define I2C_STAT_AAS (1UL << 9) 62 #define I2C_STAT_BF (1UL << 8) 63 #define I2C_STAT_AERR (1UL << 7) 64 #define I2C_STAT_STC (1UL << 6) 65 #define I2C_STAT_GC (1UL << 5) 66 #define I2C_STAT_XRDY (1UL << 4) 67 #define I2C_STAT_RRDY (1UL << 3) 68 #define I2C_STAT_ARDY (1UL << 2) 69 #define I2C_STAT_NACK (1UL << 1) 70 #define I2C_STAT_AL (1UL << 0) 71 #define I2C_REG_SYSS 0x90 72 #define I2C_SYSS_RDONE (1UL << 0) 73 #define I2C_REG_BUF 0x94 74 #define I2C_BUF_RXFIFO_CLR (1UL << 14) 75 #define I2C_BUF_TXFIFO_CLR (1UL << 6) 76 #define I2C_BUF_RXTRSH_SHIFT 8 77 #define I2C_BUF_TRSH_MASK 0x3f 78 #define I2C_REG_CNT 0x98 79 #define I2C_REG_DATA 0x9c 80 #define I2C_REG_CON 0xa4 81 #define I2C_CON_I2C_EN (1UL << 15) 82 #define I2C_CON_OPMODE_STD (0UL << 12) 83 #define I2C_CON_OPMODE_HS (1UL << 12) 84 #define I2C_CON_OPMODE_SCCB (2UL << 12) 85 #define I2C_CON_OPMODE_MASK (3UL << 13) 86 #define I2C_CON_I2C_STB (1UL << 11) 87 #define I2C_CON_MST (1UL << 10) 88 #define I2C_CON_TRX (1UL << 9) 89 #define I2C_CON_XSA (1UL << 8) 90 #define I2C_CON_XOA0 (1UL << 7) 91 #define I2C_CON_XOA1 (1UL << 6) 92 #define I2C_CON_XOA2 (1UL << 5) 93 #define I2C_CON_XOA3 (1UL << 4) 94 #define I2C_CON_STP (1UL << 1) 95 #define I2C_CON_STT (1UL << 0) 96 #define I2C_REG_OA0 0xa8 97 #define I2C_REG_SA 0xac 98 #define I2C_REG_PSC 0xb0 99 #define I2C_PSC_MASK 0xff 100 #define I2C_REG_SCLL 0xb4 101 #define I2C_SCLL_MASK 0xff 102 #define I2C_HSSCLL_SHIFT 8 103 #define I2C_REG_SCLH 0xb8 104 #define I2C_SCLH_MASK 0xff 105 #define I2C_HSSCLH_SHIFT 8 106 #define I2C_REG_SYSTEST 0xbc 107 #define I2C_REG_BUFSTAT 0xc0 108 #define I2C_BUFSTAT_FIFODEPTH_MASK 0x3 109 #define I2C_BUFSTAT_FIFODEPTH_SHIFT 14 110 #define I2C_REG_OA1 0xc4 111 #define I2C_REG_OA2 0xc8 112 #define I2C_REG_OA3 0xcc 113 #define I2C_REG_ACTOA 0xd0 114 #define I2C_REG_SBLOCK 0xd4 115 116 /* 117 * OMAP4 I2C Registers, Summary 2 118 */ 119 #define I2C_REG_REVNB_LO 0x00 120 #define I2C_REG_REVNB_HI 0x04 121 #define I2C_REG_SYSC 0x10 122 #define I2C_REG_SYSC_SRST (1UL << 1) 123 #define I2C_REG_STATUS_RAW 0x24 124 #define I2C_REG_STATUS 0x28 125 #define I2C_REG_IRQENABLE_SET 0x2C 126 #define I2C_REG_IRQENABLE_CLR 0x30 127 128 #define I2C_CLK 96000000UL /* 96MHz */ 129 #define I2C_ICLK 12000000UL /* 12MHz */ 130 131 #endif /* _TI_I2C_H_ */ 132