1 /*- 2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /** 29 * Driver for the I2C module on the TI SoC. 30 * 31 * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c). 32 * 33 * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses, 34 * 32 bit data access is not allowed and can corrupt register content. 35 * 36 * This driver currently doesn't use DMA for the transfer, although I hope to 37 * incorporate that sometime in the future. The idea being that for transaction 38 * larger than a certain size the DMA engine is used, for anything less the 39 * normal interrupt/fifo driven option is used. 40 * 41 * 42 * WARNING: This driver uses mtx_sleep and interrupts to perform transactions, 43 * which means you can't do a transaction during startup before the interrupts 44 * have been enabled. Hint - the freebsd function config_intrhook_establish(). 45 */ 46 47 #include <sys/cdefs.h> 48 __FBSDID("$FreeBSD$"); 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/bus.h> 53 #include <sys/conf.h> 54 #include <sys/kernel.h> 55 #include <sys/lock.h> 56 #include <sys/mbuf.h> 57 #include <sys/malloc.h> 58 #include <sys/module.h> 59 #include <sys/mutex.h> 60 #include <sys/rman.h> 61 #include <sys/sysctl.h> 62 #include <machine/bus.h> 63 64 #include <dev/ofw/openfirm.h> 65 #include <dev/ofw/ofw_bus.h> 66 #include <dev/ofw/ofw_bus_subr.h> 67 68 #include <arm/ti/ti_cpuid.h> 69 #include <arm/ti/ti_prcm.h> 70 #include <arm/ti/ti_i2c.h> 71 72 #include <dev/iicbus/iiconf.h> 73 #include <dev/iicbus/iicbus.h> 74 75 #include "iicbus_if.h" 76 77 /** 78 * I2C device driver context, a pointer to this is stored in the device 79 * driver structure. 80 */ 81 struct ti_i2c_softc 82 { 83 device_t sc_dev; 84 uint32_t device_id; 85 struct resource* sc_irq_res; 86 struct resource* sc_mem_res; 87 device_t sc_iicbus; 88 89 void* sc_irq_h; 90 91 struct mtx sc_mtx; 92 93 struct iic_msg* sc_buffer; 94 int sc_bus_inuse; 95 int sc_buffer_pos; 96 int sc_error; 97 int sc_fifo_trsh; 98 99 uint16_t sc_con_reg; 100 uint16_t sc_rev; 101 }; 102 103 struct ti_i2c_clock_config 104 { 105 int speed; 106 int bitrate; 107 uint8_t psc; /* Fast/Standard mode prescale divider */ 108 uint8_t scll; /* Fast/Standard mode SCL low time */ 109 uint8_t sclh; /* Fast/Standard mode SCL high time */ 110 uint8_t hsscll; /* High Speed mode SCL low time */ 111 uint8_t hssclh; /* High Speed mode SCL high time */ 112 }; 113 114 #if defined(SOC_OMAP4) 115 static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = { 116 { IIC_UNKNOWN, 100000, 23, 13, 15, 0, 0}, 117 { IIC_SLOW, 100000, 23, 13, 15, 0, 0}, 118 { IIC_FAST, 400000, 9, 5, 7, 0, 0}, 119 { IIC_FASTEST, 1000000, 5, 3, 4, 0, 0}, 120 /* { IIC_FASTEST, 3200000, 1, 113, 115, 7, 10}, - HS mode */ 121 { -1, 0 } 122 }; 123 #endif 124 125 #if defined(SOC_TI_AM335X) 126 /* 127 * AM335X doesn't support HS mode. For 100kHz I2C clock set the internal 128 * clock to 12Mhz, for 400kHz I2C clock set the internal clock to 24Mhz. 129 */ 130 static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = { 131 { IIC_UNKNOWN, 100000, 7, 59, 61, 0, 0}, 132 { IIC_SLOW, 100000, 7, 59, 61, 0, 0}, 133 { IIC_FAST, 400000, 3, 23, 25, 0, 0}, 134 { IIC_FASTEST, 400000, 3, 23, 25, 0, 0}, 135 { -1, 0 } 136 }; 137 #endif 138 139 /** 140 * Locking macros used throughout the driver 141 */ 142 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 143 #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 144 #define TI_I2C_LOCK_INIT(_sc) \ 145 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 146 "ti_i2c", MTX_DEF) 147 #define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx) 148 #define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) 149 #define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED) 150 151 #ifdef DEBUG 152 #define ti_i2c_dbg(_sc, fmt, args...) \ 153 device_printf((_sc)->sc_dev, fmt, ##args) 154 #else 155 #define ti_i2c_dbg(_sc, fmt, args...) 156 #endif 157 158 /** 159 * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers 160 * @sc: I2C device context 161 * @off: the byte offset within the register bank to read from. 162 * 163 * 164 * LOCKING: 165 * No locking required 166 * 167 * RETURNS: 168 * 16-bit value read from the register. 169 */ 170 static inline uint16_t 171 ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off) 172 { 173 174 return (bus_read_2(sc->sc_mem_res, off)); 175 } 176 177 /** 178 * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers 179 * @sc: I2C device context 180 * @off: the byte offset within the register bank to read from. 181 * @val: the value to write into the register 182 * 183 * LOCKING: 184 * No locking required 185 * 186 * RETURNS: 187 * 16-bit value read from the register. 188 */ 189 static inline void 190 ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val) 191 { 192 193 bus_write_2(sc->sc_mem_res, off, val); 194 } 195 196 static int 197 ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status) 198 { 199 int amount, done, i; 200 201 done = 0; 202 amount = 0; 203 /* Check for the error conditions. */ 204 if (status & I2C_STAT_NACK) { 205 /* No ACK from slave. */ 206 ti_i2c_dbg(sc, "NACK\n"); 207 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK); 208 sc->sc_error = ENXIO; 209 } else if (status & I2C_STAT_AL) { 210 /* Arbitration lost. */ 211 ti_i2c_dbg(sc, "Arbitration lost\n"); 212 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL); 213 sc->sc_error = ENXIO; 214 } 215 216 /* Check if we have finished. */ 217 if (status & I2C_STAT_ARDY) { 218 /* Register access ready - transaction complete basically. */ 219 ti_i2c_dbg(sc, "ARDY transaction complete\n"); 220 if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) { 221 ti_i2c_write_2(sc, I2C_REG_CON, 222 sc->sc_con_reg | I2C_CON_STP); 223 } 224 ti_i2c_write_2(sc, I2C_REG_STATUS, 225 I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY | 226 I2C_STAT_XDR | I2C_STAT_XRDY); 227 return (1); 228 } 229 230 if (sc->sc_buffer->flags & IIC_M_RD) { 231 /* Read some data. */ 232 if (status & I2C_STAT_RDR) { 233 /* 234 * Receive draining interrupt - last data received. 235 * The set FIFO threshold wont be reached to trigger 236 * RRDY. 237 */ 238 ti_i2c_dbg(sc, "Receive draining interrupt\n"); 239 240 /* 241 * Drain the FIFO. Read the pending data in the FIFO. 242 */ 243 amount = sc->sc_buffer->len - sc->sc_buffer_pos; 244 } else if (status & I2C_STAT_RRDY) { 245 /* 246 * Receive data ready interrupt - FIFO has reached the 247 * set threshold. 248 */ 249 ti_i2c_dbg(sc, "Receive data ready interrupt\n"); 250 251 amount = min(sc->sc_fifo_trsh, 252 sc->sc_buffer->len - sc->sc_buffer_pos); 253 } 254 255 /* Read the bytes from the fifo. */ 256 for (i = 0; i < amount; i++) 257 sc->sc_buffer->buf[sc->sc_buffer_pos++] = 258 (uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff); 259 260 if (status & I2C_STAT_RDR) 261 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR); 262 if (status & I2C_STAT_RRDY) 263 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY); 264 265 } else { 266 /* Write some data. */ 267 if (status & I2C_STAT_XDR) { 268 /* 269 * Transmit draining interrupt - FIFO level is below 270 * the set threshold and the amount of data still to 271 * be transferred wont reach the set FIFO threshold. 272 */ 273 ti_i2c_dbg(sc, "Transmit draining interrupt\n"); 274 275 /* 276 * Drain the TX data. Write the pending data in the 277 * FIFO. 278 */ 279 amount = sc->sc_buffer->len - sc->sc_buffer_pos; 280 } else if (status & I2C_STAT_XRDY) { 281 /* 282 * Transmit data ready interrupt - the FIFO level 283 * is below the set threshold. 284 */ 285 ti_i2c_dbg(sc, "Transmit data ready interrupt\n"); 286 287 amount = min(sc->sc_fifo_trsh, 288 sc->sc_buffer->len - sc->sc_buffer_pos); 289 } 290 291 /* Write the bytes from the fifo. */ 292 for (i = 0; i < amount; i++) 293 ti_i2c_write_2(sc, I2C_REG_DATA, 294 sc->sc_buffer->buf[sc->sc_buffer_pos++]); 295 296 if (status & I2C_STAT_XDR) 297 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR); 298 if (status & I2C_STAT_XRDY) 299 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY); 300 } 301 302 return (done); 303 } 304 305 /** 306 * ti_i2c_intr - interrupt handler for the I2C module 307 * @dev: i2c device handle 308 * 309 * 310 * 311 * LOCKING: 312 * Called from timer context 313 * 314 * RETURNS: 315 * EH_HANDLED or EH_NOT_HANDLED 316 */ 317 static void 318 ti_i2c_intr(void *arg) 319 { 320 int done; 321 struct ti_i2c_softc *sc; 322 uint16_t events, status; 323 324 sc = (struct ti_i2c_softc *)arg; 325 326 TI_I2C_LOCK(sc); 327 328 status = ti_i2c_read_2(sc, I2C_REG_STATUS); 329 if (status == 0) { 330 TI_I2C_UNLOCK(sc); 331 return; 332 } 333 334 /* Save enabled interrupts. */ 335 events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET); 336 337 /* We only care about enabled interrupts. */ 338 status &= events; 339 340 done = 0; 341 342 if (sc->sc_buffer != NULL) 343 done = ti_i2c_transfer_intr(sc, status); 344 else { 345 ti_i2c_dbg(sc, "Transfer interrupt without buffer\n"); 346 sc->sc_error = EINVAL; 347 done = 1; 348 } 349 350 if (done) 351 /* Wakeup the process that started the transaction. */ 352 wakeup(sc); 353 354 TI_I2C_UNLOCK(sc); 355 } 356 357 /** 358 * ti_i2c_transfer - called to perform the transfer 359 * @dev: i2c device handle 360 * @msgs: the messages to send/receive 361 * @nmsgs: the number of messages in the msgs array 362 * 363 * 364 * LOCKING: 365 * Internally locked 366 * 367 * RETURNS: 368 * 0 on function succeeded 369 * EINVAL if invalid message is passed as an arg 370 */ 371 static int 372 ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 373 { 374 int err, i, repstart, timeout; 375 struct ti_i2c_softc *sc; 376 uint16_t reg; 377 378 sc = device_get_softc(dev); 379 TI_I2C_LOCK(sc); 380 381 /* If the controller is busy wait until it is available. */ 382 while (sc->sc_bus_inuse == 1) 383 mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0); 384 385 /* Now we have control over the I2C controller. */ 386 sc->sc_bus_inuse = 1; 387 388 err = 0; 389 repstart = 0; 390 for (i = 0; i < nmsgs; i++) { 391 392 sc->sc_buffer = &msgs[i]; 393 sc->sc_buffer_pos = 0; 394 sc->sc_error = 0; 395 396 /* Zero byte transfers aren't allowed. */ 397 if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL || 398 sc->sc_buffer->len == 0) { 399 err = EINVAL; 400 break; 401 } 402 403 /* Check if the i2c bus is free. */ 404 if (repstart == 0) { 405 /* 406 * On repeated start we send the START condition while 407 * the bus _is_ busy. 408 */ 409 timeout = 0; 410 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) { 411 if (timeout++ > 100) { 412 err = EBUSY; 413 goto out; 414 } 415 DELAY(1000); 416 } 417 timeout = 0; 418 } else 419 repstart = 0; 420 421 if (sc->sc_buffer->flags & IIC_M_NOSTOP) 422 repstart = 1; 423 424 /* Set the slave address. */ 425 ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1); 426 427 /* Write the data length. */ 428 ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len); 429 430 /* Clear the RX and the TX FIFO. */ 431 reg = ti_i2c_read_2(sc, I2C_REG_BUF); 432 reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR; 433 ti_i2c_write_2(sc, I2C_REG_BUF, reg); 434 435 reg = sc->sc_con_reg | I2C_CON_STT; 436 if (repstart == 0) 437 reg |= I2C_CON_STP; 438 if ((sc->sc_buffer->flags & IIC_M_RD) == 0) 439 reg |= I2C_CON_TRX; 440 ti_i2c_write_2(sc, I2C_REG_CON, reg); 441 442 /* Wait for an event. */ 443 err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", hz); 444 if (err == 0) 445 err = sc->sc_error; 446 447 if (err) 448 break; 449 } 450 451 out: 452 if (timeout == 0) { 453 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) { 454 if (timeout++ > 100) 455 break; 456 DELAY(1000); 457 } 458 } 459 /* Put the controller in master mode again. */ 460 if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0) 461 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 462 463 sc->sc_buffer = NULL; 464 sc->sc_bus_inuse = 0; 465 466 /* Wake up the processes that are waiting for the bus. */ 467 wakeup(sc); 468 469 TI_I2C_UNLOCK(sc); 470 471 return (err); 472 } 473 474 /** 475 * ti_i2c_callback - as we only provide iicbus_transfer() interface 476 * we don't need to implement the serialization here. 477 * @dev: i2c device handle 478 * 479 * 480 * 481 * LOCKING: 482 * Called from timer context 483 * 484 * RETURNS: 485 * EH_HANDLED or EH_NOT_HANDLED 486 */ 487 static int 488 ti_i2c_callback(device_t dev, int index, caddr_t data) 489 { 490 int error = 0; 491 492 switch (index) { 493 case IIC_REQUEST_BUS: 494 break; 495 496 case IIC_RELEASE_BUS: 497 break; 498 499 default: 500 error = EINVAL; 501 } 502 503 return (error); 504 } 505 506 static int 507 ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed) 508 { 509 int timeout; 510 struct ti_i2c_clock_config *clkcfg; 511 uint16_t fifo_trsh, reg, scll, sclh; 512 513 switch (ti_chip()) { 514 #ifdef SOC_OMAP4 515 case CHIP_OMAP_4: 516 clkcfg = ti_omap4_i2c_clock_configs; 517 break; 518 #endif 519 #ifdef SOC_TI_AM335X 520 case CHIP_AM335X: 521 clkcfg = ti_am335x_i2c_clock_configs; 522 break; 523 #endif 524 default: 525 panic("Unknown Ti SoC, unable to reset the i2c"); 526 } 527 while (clkcfg->speed != -1) { 528 if (clkcfg->speed == speed) 529 break; 530 clkcfg++; 531 } 532 if (clkcfg->speed == -1) 533 return (EINVAL); 534 535 /* 536 * 23.1.4.3 - HS I2C Software Reset 537 * From OMAP4 TRM at page 4068. 538 * 539 * 1. Ensure that the module is disabled. 540 */ 541 sc->sc_con_reg = 0; 542 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 543 544 /* 2. Issue a softreset to the controller. */ 545 bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST); 546 547 /* 548 * 3. Enable the module. 549 * The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module 550 * is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1. 551 */ 552 ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN); 553 554 /* 4. Wait for the software reset to complete. */ 555 timeout = 0; 556 while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) { 557 if (timeout++ > 100) 558 return (EBUSY); 559 DELAY(100); 560 } 561 562 /* 563 * Disable the I2C controller once again, now that the reset has 564 * finished. 565 */ 566 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 567 568 /* 569 * The following sequence is taken from the OMAP4 TRM at page 4077. 570 * 571 * 1. Enable the functional and interface clocks (see Section 572 * 23.1.5.1.1.1.1). Done at ti_i2c_activate(). 573 * 574 * 2. Program the prescaler to obtain an approximately 12MHz internal 575 * sampling clock (I2Ci_INTERNAL_CLK) by programming the 576 * corresponding value in the I2Ci.I2C_PSC[3:0] PSC field. 577 * This value depends on the frequency of the functional clock 578 * (I2Ci_FCLK). Because this frequency is 96MHz, the 579 * I2Ci.I2C_PSC[7:0] PSC field value is 0x7. 580 */ 581 ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc); 582 583 /* 584 * 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH 585 * bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps. 586 * These values depend on the internal sampling clock frequency 587 * (see Table 23-8). 588 */ 589 scll = clkcfg->scll & I2C_SCLL_MASK; 590 sclh = clkcfg->sclh & I2C_SCLH_MASK; 591 592 /* 593 * 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and 594 * I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of 595 * 400K bps or 3.4M bps (for the second phase of HS mode). These 596 * values depend on the internal sampling clock frequency (see 597 * Table 23-8). 598 * 599 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line 600 * capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional 601 * Multiplexing and Configuration). 602 */ 603 switch (ti_chip()) { 604 #ifdef SOC_OMAP4 605 case CHIP_OMAP_4: 606 if ((clkcfg->hsscll + clkcfg->hssclh) > 0) { 607 scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT; 608 sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT; 609 sc->sc_con_reg |= I2C_CON_OPMODE_HS; 610 } 611 break; 612 #endif 613 } 614 615 /* Write the selected bit rate. */ 616 ti_i2c_write_2(sc, I2C_REG_SCLL, scll); 617 ti_i2c_write_2(sc, I2C_REG_SCLH, sclh); 618 619 /* 620 * 6. Configure the Own Address of the I2C controller by storing it in 621 * the I2Ci.I2C_OA0 register. Up to four Own Addresses can be 622 * programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3) 623 * for each I2C controller. 624 * 625 * Note: For a 10-bit address, set the corresponding expand Own Address 626 * bit in the I2Ci.I2C_CON register. 627 * 628 * Driver currently always in single master mode so ignore this step. 629 */ 630 631 /* 632 * 7. Set the TX threshold (in transmitter mode) and the RX threshold 633 * (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to 634 * (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX 635 * threshold - 1), where the TX and RX thresholds are greater than 636 * or equal to 1. 637 * 638 * The threshold is set to 5 for now. 639 */ 640 fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK; 641 reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT); 642 ti_i2c_write_2(sc, I2C_REG_BUF, reg); 643 644 /* 645 * 8. Take the I2C controller out of reset by setting the 646 * I2Ci.I2C_CON[15] I2C_EN bit to 1. 647 * 648 * 23.1.5.1.1.1.2 - Initialize the I2C Controller 649 * 650 * To initialize the I2C controller, perform the following steps: 651 * 652 * 1. Configure the I2Ci.I2C_CON register: 653 * . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit 654 * (0: slave, 1: master). 655 * . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX 656 * bit (0: receiver, 1: transmitter). 657 */ 658 659 /* Enable the I2C controller in master mode. */ 660 sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST; 661 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 662 663 /* 664 * 2. If using an interrupt to transmit/receive data, set the 665 * corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4] 666 * XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY 667 * bit for the receive interrupt). 668 */ 669 670 /* Set the interrupts we want to be notified. */ 671 reg = I2C_IE_XDR | /* Transmit draining interrupt. */ 672 I2C_IE_XRDY | /* Transmit Data Ready interrupt. */ 673 I2C_IE_RDR | /* Receive draining interrupt. */ 674 I2C_IE_RRDY | /* Receive Data Ready interrupt. */ 675 I2C_IE_ARDY | /* Register Access Ready interrupt. */ 676 I2C_IE_NACK | /* No Acknowledgment interrupt. */ 677 I2C_IE_AL; /* Arbitration lost interrupt. */ 678 679 /* Enable the interrupts. */ 680 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg); 681 682 /* 683 * 3. If using DMA to receive/transmit data, set to 1 the corresponding 684 * bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN 685 * bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit 686 * for the transmit DMA channel). 687 * 688 * Not using DMA for now, so ignore this. 689 */ 690 691 return (0); 692 } 693 694 static int 695 ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 696 { 697 struct ti_i2c_softc *sc; 698 int err; 699 700 sc = device_get_softc(dev); 701 TI_I2C_LOCK(sc); 702 err = ti_i2c_reset(sc, speed); 703 TI_I2C_UNLOCK(sc); 704 if (err) 705 return (err); 706 707 return (IIC_ENOADDR); 708 } 709 710 static int 711 ti_i2c_activate(device_t dev) 712 { 713 clk_ident_t clk; 714 int err; 715 struct ti_i2c_softc *sc; 716 717 sc = (struct ti_i2c_softc*)device_get_softc(dev); 718 719 /* 720 * 1. Enable the functional and interface clocks (see Section 721 * 23.1.5.1.1.1.1). 722 */ 723 clk = I2C0_CLK + sc->device_id; 724 err = ti_prcm_clk_enable(clk); 725 if (err) 726 return (err); 727 728 return (ti_i2c_reset(sc, IIC_UNKNOWN)); 729 } 730 731 /** 732 * ti_i2c_deactivate - deactivates the controller and releases resources 733 * @dev: i2c device handle 734 * 735 * 736 * 737 * LOCKING: 738 * Assumed called in an atomic context. 739 * 740 * RETURNS: 741 * nothing 742 */ 743 static void 744 ti_i2c_deactivate(device_t dev) 745 { 746 struct ti_i2c_softc *sc = device_get_softc(dev); 747 clk_ident_t clk; 748 749 /* Disable the controller - cancel all transactions. */ 750 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff); 751 ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff); 752 ti_i2c_write_2(sc, I2C_REG_CON, 0); 753 754 /* Release the interrupt handler. */ 755 if (sc->sc_irq_h != NULL) { 756 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h); 757 sc->sc_irq_h = NULL; 758 } 759 760 bus_generic_detach(sc->sc_dev); 761 762 /* Unmap the I2C controller registers. */ 763 if (sc->sc_mem_res != NULL) { 764 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 765 sc->sc_mem_res = NULL; 766 } 767 768 /* Release the IRQ resource. */ 769 if (sc->sc_irq_res != NULL) { 770 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 771 sc->sc_irq_res = NULL; 772 } 773 774 /* Finally disable the functional and interface clocks. */ 775 clk = I2C0_CLK + sc->device_id; 776 ti_prcm_clk_disable(clk); 777 } 778 779 static int 780 ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS) 781 { 782 device_t dev; 783 int clk, psc, sclh, scll; 784 struct ti_i2c_softc *sc; 785 786 dev = (device_t)arg1; 787 sc = device_get_softc(dev); 788 789 TI_I2C_LOCK(sc); 790 /* Get the system prescaler value. */ 791 psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1; 792 793 /* Get the bitrate. */ 794 scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK; 795 sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK; 796 797 clk = I2C_CLK / psc / (scll + 7 + sclh + 5); 798 TI_I2C_UNLOCK(sc); 799 800 return (sysctl_handle_int(oidp, &clk, 0, req)); 801 } 802 803 static int 804 ti_i2c_probe(device_t dev) 805 { 806 807 if (!ofw_bus_status_okay(dev)) 808 return (ENXIO); 809 if (!ofw_bus_is_compatible(dev, "ti,i2c")) 810 return (ENXIO); 811 device_set_desc(dev, "TI I2C Controller"); 812 813 return (0); 814 } 815 816 static int 817 ti_i2c_attach(device_t dev) 818 { 819 int err, rid; 820 phandle_t node; 821 struct ti_i2c_softc *sc; 822 struct sysctl_ctx_list *ctx; 823 struct sysctl_oid_list *tree; 824 uint16_t fifosz; 825 826 sc = device_get_softc(dev); 827 sc->sc_dev = dev; 828 829 /* Get the i2c device id from FDT. */ 830 node = ofw_bus_get_node(dev); 831 if ((OF_getencprop(node, "i2c-device-id", &sc->device_id, 832 sizeof(sc->device_id))) <= 0) { 833 device_printf(dev, "missing i2c-device-id attribute in FDT\n"); 834 return (ENXIO); 835 } 836 837 /* Get the memory resource for the register mapping. */ 838 rid = 0; 839 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 840 RF_ACTIVE); 841 if (sc->sc_mem_res == NULL) { 842 device_printf(dev, "Cannot map registers.\n"); 843 return (ENXIO); 844 } 845 846 /* Allocate our IRQ resource. */ 847 rid = 0; 848 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 849 RF_ACTIVE | RF_SHAREABLE); 850 if (sc->sc_irq_res == NULL) { 851 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 852 device_printf(dev, "Cannot allocate interrupt.\n"); 853 return (ENXIO); 854 } 855 856 TI_I2C_LOCK_INIT(sc); 857 858 /* First of all, we _must_ activate the H/W. */ 859 err = ti_i2c_activate(dev); 860 if (err) { 861 device_printf(dev, "ti_i2c_activate failed\n"); 862 goto out; 863 } 864 865 /* Read the version number of the I2C module */ 866 sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff; 867 868 /* Get the fifo size. */ 869 fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT); 870 fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT; 871 fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK; 872 873 device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n", 874 sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz); 875 876 /* Set the FIFO threshold to 5 for now. */ 877 sc->sc_fifo_trsh = 5; 878 879 ctx = device_get_sysctl_ctx(dev); 880 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 881 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock", 882 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, dev, 0, 883 ti_i2c_sysctl_clk, "IU", "I2C bus clock"); 884 885 /* Activate the interrupt. */ 886 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 887 NULL, ti_i2c_intr, sc, &sc->sc_irq_h); 888 if (err) 889 goto out; 890 891 /* Attach the iicbus. */ 892 if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { 893 device_printf(dev, "could not allocate iicbus instance\n"); 894 err = ENXIO; 895 goto out; 896 } 897 898 /* Probe and attach the iicbus */ 899 bus_generic_attach(dev); 900 901 out: 902 if (err) { 903 ti_i2c_deactivate(dev); 904 TI_I2C_LOCK_DESTROY(sc); 905 } 906 907 return (err); 908 } 909 910 static int 911 ti_i2c_detach(device_t dev) 912 { 913 struct ti_i2c_softc *sc; 914 int rv; 915 916 sc = device_get_softc(dev); 917 ti_i2c_deactivate(dev); 918 TI_I2C_LOCK_DESTROY(sc); 919 if (sc->sc_iicbus && 920 (rv = device_delete_child(dev, sc->sc_iicbus)) != 0) 921 return (rv); 922 923 return (0); 924 } 925 926 static phandle_t 927 ti_i2c_get_node(device_t bus, device_t dev) 928 { 929 930 /* Share controller node with iibus device. */ 931 return (ofw_bus_get_node(bus)); 932 } 933 934 static device_method_t ti_i2c_methods[] = { 935 /* Device interface */ 936 DEVMETHOD(device_probe, ti_i2c_probe), 937 DEVMETHOD(device_attach, ti_i2c_attach), 938 DEVMETHOD(device_detach, ti_i2c_detach), 939 940 /* OFW methods */ 941 DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node), 942 943 /* iicbus interface */ 944 DEVMETHOD(iicbus_callback, ti_i2c_callback), 945 DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset), 946 DEVMETHOD(iicbus_transfer, ti_i2c_transfer), 947 948 DEVMETHOD_END 949 }; 950 951 static driver_t ti_i2c_driver = { 952 "iichb", 953 ti_i2c_methods, 954 sizeof(struct ti_i2c_softc), 955 }; 956 957 static devclass_t ti_i2c_devclass; 958 959 DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, ti_i2c_devclass, 0, 0); 960 DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, iicbus_devclass, 0, 0); 961 962 MODULE_DEPEND(ti_iic, ti_prcm, 1, 1, 1); 963 MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1); 964