1 /*- 2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /** 29 * Driver for the I2C module on the TI SoC. 30 * 31 * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c). 32 * 33 * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses, 34 * 32 bit data access is not allowed and can corrupt register content. 35 * 36 * This driver currently doesn't use DMA for the transfer, although I hope to 37 * incorporate that sometime in the future. The idea being that for transaction 38 * larger than a certain size the DMA engine is used, for anything less the 39 * normal interrupt/fifo driven option is used. 40 * 41 * 42 * WARNING: This driver uses mtx_sleep and interrupts to perform transactions, 43 * which means you can't do a transaction during startup before the interrupts 44 * have been enabled. Hint - the freebsd function config_intrhook_establish(). 45 */ 46 47 #include <sys/cdefs.h> 48 __FBSDID("$FreeBSD$"); 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/bus.h> 53 #include <sys/conf.h> 54 #include <sys/kernel.h> 55 #include <sys/lock.h> 56 #include <sys/mbuf.h> 57 #include <sys/malloc.h> 58 #include <sys/module.h> 59 #include <sys/mutex.h> 60 #include <sys/rman.h> 61 #include <sys/sysctl.h> 62 #include <machine/bus.h> 63 64 #include <dev/ofw/openfirm.h> 65 #include <dev/ofw/ofw_bus.h> 66 #include <dev/ofw/ofw_bus_subr.h> 67 68 #include <arm/ti/ti_cpuid.h> 69 #include <arm/ti/ti_prcm.h> 70 #include <arm/ti/ti_i2c.h> 71 72 #include <dev/iicbus/iiconf.h> 73 #include <dev/iicbus/iicbus.h> 74 75 #include "iicbus_if.h" 76 77 /** 78 * I2C device driver context, a pointer to this is stored in the device 79 * driver structure. 80 */ 81 struct ti_i2c_softc 82 { 83 device_t sc_dev; 84 uint32_t device_id; 85 struct resource* sc_irq_res; 86 struct resource* sc_mem_res; 87 device_t sc_iicbus; 88 89 void* sc_irq_h; 90 91 struct mtx sc_mtx; 92 93 struct iic_msg* sc_buffer; 94 int sc_bus_inuse; 95 int sc_buffer_pos; 96 int sc_error; 97 int sc_fifo_trsh; 98 int sc_timeout; 99 100 uint16_t sc_con_reg; 101 uint16_t sc_rev; 102 }; 103 104 struct ti_i2c_clock_config 105 { 106 u_int frequency; /* Bus frequency in Hz */ 107 uint8_t psc; /* Fast/Standard mode prescale divider */ 108 uint8_t scll; /* Fast/Standard mode SCL low time */ 109 uint8_t sclh; /* Fast/Standard mode SCL high time */ 110 uint8_t hsscll; /* High Speed mode SCL low time */ 111 uint8_t hssclh; /* High Speed mode SCL high time */ 112 }; 113 114 #if defined(SOC_OMAP4) 115 /* 116 * OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)). 117 * The prescaler values for 100KHz and 400KHz modes come from the table in the 118 * OMAP4 TRM. The table doesn't list 1MHz; these values should give that speed. 119 */ 120 static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = { 121 { 100000, 23, 13, 15, 0, 0}, 122 { 400000, 9, 5, 7, 0, 0}, 123 { 1000000, 3, 5, 7, 0, 0}, 124 /* { 3200000, 1, 113, 115, 7, 10}, - HS mode */ 125 { 0 /* Table terminator */ } 126 }; 127 #endif 128 129 #if defined(SOC_TI_AM335X) 130 /* 131 * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5)) 132 * In all cases we prescale the clock to 24MHz as recommended in the manual. 133 */ 134 static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = { 135 { 100000, 1, 111, 117, 0, 0}, 136 { 400000, 1, 23, 25, 0, 0}, 137 { 1000000, 1, 5, 7, 0, 0}, 138 { 0 /* Table terminator */ } 139 }; 140 #endif 141 142 /** 143 * Locking macros used throughout the driver 144 */ 145 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 146 #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 147 #define TI_I2C_LOCK_INIT(_sc) \ 148 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 149 "ti_i2c", MTX_DEF) 150 #define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx) 151 #define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) 152 #define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED) 153 154 #ifdef DEBUG 155 #define ti_i2c_dbg(_sc, fmt, args...) \ 156 device_printf((_sc)->sc_dev, fmt, ##args) 157 #else 158 #define ti_i2c_dbg(_sc, fmt, args...) 159 #endif 160 161 /** 162 * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers 163 * @sc: I2C device context 164 * @off: the byte offset within the register bank to read from. 165 * 166 * 167 * LOCKING: 168 * No locking required 169 * 170 * RETURNS: 171 * 16-bit value read from the register. 172 */ 173 static inline uint16_t 174 ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off) 175 { 176 177 return (bus_read_2(sc->sc_mem_res, off)); 178 } 179 180 /** 181 * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers 182 * @sc: I2C device context 183 * @off: the byte offset within the register bank to read from. 184 * @val: the value to write into the register 185 * 186 * LOCKING: 187 * No locking required 188 * 189 * RETURNS: 190 * 16-bit value read from the register. 191 */ 192 static inline void 193 ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val) 194 { 195 196 bus_write_2(sc->sc_mem_res, off, val); 197 } 198 199 static int 200 ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status) 201 { 202 int amount, done, i; 203 204 done = 0; 205 amount = 0; 206 /* Check for the error conditions. */ 207 if (status & I2C_STAT_NACK) { 208 /* No ACK from slave. */ 209 ti_i2c_dbg(sc, "NACK\n"); 210 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK); 211 sc->sc_error = ENXIO; 212 } else if (status & I2C_STAT_AL) { 213 /* Arbitration lost. */ 214 ti_i2c_dbg(sc, "Arbitration lost\n"); 215 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL); 216 sc->sc_error = ENXIO; 217 } 218 219 /* Check if we have finished. */ 220 if (status & I2C_STAT_ARDY) { 221 /* Register access ready - transaction complete basically. */ 222 ti_i2c_dbg(sc, "ARDY transaction complete\n"); 223 if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) { 224 ti_i2c_write_2(sc, I2C_REG_CON, 225 sc->sc_con_reg | I2C_CON_STP); 226 } 227 ti_i2c_write_2(sc, I2C_REG_STATUS, 228 I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY | 229 I2C_STAT_XDR | I2C_STAT_XRDY); 230 return (1); 231 } 232 233 if (sc->sc_buffer->flags & IIC_M_RD) { 234 /* Read some data. */ 235 if (status & I2C_STAT_RDR) { 236 /* 237 * Receive draining interrupt - last data received. 238 * The set FIFO threshold wont be reached to trigger 239 * RRDY. 240 */ 241 ti_i2c_dbg(sc, "Receive draining interrupt\n"); 242 243 /* 244 * Drain the FIFO. Read the pending data in the FIFO. 245 */ 246 amount = sc->sc_buffer->len - sc->sc_buffer_pos; 247 } else if (status & I2C_STAT_RRDY) { 248 /* 249 * Receive data ready interrupt - FIFO has reached the 250 * set threshold. 251 */ 252 ti_i2c_dbg(sc, "Receive data ready interrupt\n"); 253 254 amount = min(sc->sc_fifo_trsh, 255 sc->sc_buffer->len - sc->sc_buffer_pos); 256 } 257 258 /* Read the bytes from the fifo. */ 259 for (i = 0; i < amount; i++) 260 sc->sc_buffer->buf[sc->sc_buffer_pos++] = 261 (uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff); 262 263 if (status & I2C_STAT_RDR) 264 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR); 265 if (status & I2C_STAT_RRDY) 266 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY); 267 268 } else { 269 /* Write some data. */ 270 if (status & I2C_STAT_XDR) { 271 /* 272 * Transmit draining interrupt - FIFO level is below 273 * the set threshold and the amount of data still to 274 * be transferred wont reach the set FIFO threshold. 275 */ 276 ti_i2c_dbg(sc, "Transmit draining interrupt\n"); 277 278 /* 279 * Drain the TX data. Write the pending data in the 280 * FIFO. 281 */ 282 amount = sc->sc_buffer->len - sc->sc_buffer_pos; 283 } else if (status & I2C_STAT_XRDY) { 284 /* 285 * Transmit data ready interrupt - the FIFO level 286 * is below the set threshold. 287 */ 288 ti_i2c_dbg(sc, "Transmit data ready interrupt\n"); 289 290 amount = min(sc->sc_fifo_trsh, 291 sc->sc_buffer->len - sc->sc_buffer_pos); 292 } 293 294 /* Write the bytes from the fifo. */ 295 for (i = 0; i < amount; i++) 296 ti_i2c_write_2(sc, I2C_REG_DATA, 297 sc->sc_buffer->buf[sc->sc_buffer_pos++]); 298 299 if (status & I2C_STAT_XDR) 300 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR); 301 if (status & I2C_STAT_XRDY) 302 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY); 303 } 304 305 return (done); 306 } 307 308 /** 309 * ti_i2c_intr - interrupt handler for the I2C module 310 * @dev: i2c device handle 311 * 312 * 313 * 314 * LOCKING: 315 * Called from timer context 316 * 317 * RETURNS: 318 * EH_HANDLED or EH_NOT_HANDLED 319 */ 320 static void 321 ti_i2c_intr(void *arg) 322 { 323 int done; 324 struct ti_i2c_softc *sc; 325 uint16_t events, status; 326 327 sc = (struct ti_i2c_softc *)arg; 328 329 TI_I2C_LOCK(sc); 330 331 status = ti_i2c_read_2(sc, I2C_REG_STATUS); 332 if (status == 0) { 333 TI_I2C_UNLOCK(sc); 334 return; 335 } 336 337 /* Save enabled interrupts. */ 338 events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET); 339 340 /* We only care about enabled interrupts. */ 341 status &= events; 342 343 done = 0; 344 345 if (sc->sc_buffer != NULL) 346 done = ti_i2c_transfer_intr(sc, status); 347 else { 348 ti_i2c_dbg(sc, "Transfer interrupt without buffer\n"); 349 sc->sc_error = EINVAL; 350 done = 1; 351 } 352 353 if (done) 354 /* Wakeup the process that started the transaction. */ 355 wakeup(sc); 356 357 TI_I2C_UNLOCK(sc); 358 } 359 360 /** 361 * ti_i2c_transfer - called to perform the transfer 362 * @dev: i2c device handle 363 * @msgs: the messages to send/receive 364 * @nmsgs: the number of messages in the msgs array 365 * 366 * 367 * LOCKING: 368 * Internally locked 369 * 370 * RETURNS: 371 * 0 on function succeeded 372 * EINVAL if invalid message is passed as an arg 373 */ 374 static int 375 ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 376 { 377 int err, i, repstart, timeout; 378 struct ti_i2c_softc *sc; 379 uint16_t reg; 380 381 sc = device_get_softc(dev); 382 TI_I2C_LOCK(sc); 383 384 /* If the controller is busy wait until it is available. */ 385 while (sc->sc_bus_inuse == 1) 386 mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0); 387 388 /* Now we have control over the I2C controller. */ 389 sc->sc_bus_inuse = 1; 390 391 err = 0; 392 repstart = 0; 393 for (i = 0; i < nmsgs; i++) { 394 395 sc->sc_buffer = &msgs[i]; 396 sc->sc_buffer_pos = 0; 397 sc->sc_error = 0; 398 399 /* Zero byte transfers aren't allowed. */ 400 if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL || 401 sc->sc_buffer->len == 0) { 402 err = EINVAL; 403 break; 404 } 405 406 /* Check if the i2c bus is free. */ 407 if (repstart == 0) { 408 /* 409 * On repeated start we send the START condition while 410 * the bus _is_ busy. 411 */ 412 timeout = 0; 413 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) { 414 if (timeout++ > 100) { 415 err = EBUSY; 416 goto out; 417 } 418 DELAY(1000); 419 } 420 timeout = 0; 421 } else 422 repstart = 0; 423 424 if (sc->sc_buffer->flags & IIC_M_NOSTOP) 425 repstart = 1; 426 427 /* Set the slave address. */ 428 ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1); 429 430 /* Write the data length. */ 431 ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len); 432 433 /* Clear the RX and the TX FIFO. */ 434 reg = ti_i2c_read_2(sc, I2C_REG_BUF); 435 reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR; 436 ti_i2c_write_2(sc, I2C_REG_BUF, reg); 437 438 reg = sc->sc_con_reg | I2C_CON_STT; 439 if (repstart == 0) 440 reg |= I2C_CON_STP; 441 if ((sc->sc_buffer->flags & IIC_M_RD) == 0) 442 reg |= I2C_CON_TRX; 443 ti_i2c_write_2(sc, I2C_REG_CON, reg); 444 445 /* Wait for an event. */ 446 err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", sc->sc_timeout); 447 if (err == 0) 448 err = sc->sc_error; 449 450 if (err) 451 break; 452 } 453 454 out: 455 if (timeout == 0) { 456 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) { 457 if (timeout++ > 100) 458 break; 459 DELAY(1000); 460 } 461 } 462 /* Put the controller in master mode again. */ 463 if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0) 464 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 465 466 sc->sc_buffer = NULL; 467 sc->sc_bus_inuse = 0; 468 469 /* Wake up the processes that are waiting for the bus. */ 470 wakeup(sc); 471 472 TI_I2C_UNLOCK(sc); 473 474 return (err); 475 } 476 477 static int 478 ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed) 479 { 480 int timeout; 481 struct ti_i2c_clock_config *clkcfg; 482 u_int busfreq; 483 uint16_t fifo_trsh, reg, scll, sclh; 484 485 switch (ti_chip()) { 486 #ifdef SOC_OMAP4 487 case CHIP_OMAP_4: 488 clkcfg = ti_omap4_i2c_clock_configs; 489 break; 490 #endif 491 #ifdef SOC_TI_AM335X 492 case CHIP_AM335X: 493 clkcfg = ti_am335x_i2c_clock_configs; 494 break; 495 #endif 496 default: 497 panic("Unknown Ti SoC, unable to reset the i2c"); 498 } 499 500 /* 501 * If we haven't attached the bus yet, just init at the default slow 502 * speed. This lets us get the hardware initialized enough to attach 503 * the bus which is where the real speed configuration is handled. After 504 * the bus is attached, get the configured speed from it. Search the 505 * configuration table for the best speed we can do that doesn't exceed 506 * the requested speed. 507 */ 508 if (sc->sc_iicbus == NULL) 509 busfreq = 100000; 510 else 511 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); 512 for (;;) { 513 if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq) 514 break; 515 clkcfg++; 516 } 517 518 /* 519 * 23.1.4.3 - HS I2C Software Reset 520 * From OMAP4 TRM at page 4068. 521 * 522 * 1. Ensure that the module is disabled. 523 */ 524 sc->sc_con_reg = 0; 525 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 526 527 /* 2. Issue a softreset to the controller. */ 528 bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST); 529 530 /* 531 * 3. Enable the module. 532 * The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module 533 * is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1. 534 */ 535 ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN); 536 537 /* 4. Wait for the software reset to complete. */ 538 timeout = 0; 539 while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) { 540 if (timeout++ > 100) 541 return (EBUSY); 542 DELAY(100); 543 } 544 545 /* 546 * Disable the I2C controller once again, now that the reset has 547 * finished. 548 */ 549 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 550 551 /* 552 * The following sequence is taken from the OMAP4 TRM at page 4077. 553 * 554 * 1. Enable the functional and interface clocks (see Section 555 * 23.1.5.1.1.1.1). Done at ti_i2c_activate(). 556 * 557 * 2. Program the prescaler to obtain an approximately 12MHz internal 558 * sampling clock (I2Ci_INTERNAL_CLK) by programming the 559 * corresponding value in the I2Ci.I2C_PSC[3:0] PSC field. 560 * This value depends on the frequency of the functional clock 561 * (I2Ci_FCLK). Because this frequency is 96MHz, the 562 * I2Ci.I2C_PSC[7:0] PSC field value is 0x7. 563 */ 564 ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc); 565 566 /* 567 * 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH 568 * bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps. 569 * These values depend on the internal sampling clock frequency 570 * (see Table 23-8). 571 */ 572 scll = clkcfg->scll & I2C_SCLL_MASK; 573 sclh = clkcfg->sclh & I2C_SCLH_MASK; 574 575 /* 576 * 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and 577 * I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of 578 * 400K bps or 3.4M bps (for the second phase of HS mode). These 579 * values depend on the internal sampling clock frequency (see 580 * Table 23-8). 581 * 582 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line 583 * capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional 584 * Multiplexing and Configuration). 585 */ 586 switch (ti_chip()) { 587 #ifdef SOC_OMAP4 588 case CHIP_OMAP_4: 589 if ((clkcfg->hsscll + clkcfg->hssclh) > 0) { 590 scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT; 591 sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT; 592 sc->sc_con_reg |= I2C_CON_OPMODE_HS; 593 } 594 break; 595 #endif 596 } 597 598 /* Write the selected bit rate. */ 599 ti_i2c_write_2(sc, I2C_REG_SCLL, scll); 600 ti_i2c_write_2(sc, I2C_REG_SCLH, sclh); 601 602 /* 603 * 6. Configure the Own Address of the I2C controller by storing it in 604 * the I2Ci.I2C_OA0 register. Up to four Own Addresses can be 605 * programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3) 606 * for each I2C controller. 607 * 608 * Note: For a 10-bit address, set the corresponding expand Own Address 609 * bit in the I2Ci.I2C_CON register. 610 * 611 * Driver currently always in single master mode so ignore this step. 612 */ 613 614 /* 615 * 7. Set the TX threshold (in transmitter mode) and the RX threshold 616 * (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to 617 * (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX 618 * threshold - 1), where the TX and RX thresholds are greater than 619 * or equal to 1. 620 * 621 * The threshold is set to 5 for now. 622 */ 623 fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK; 624 reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT); 625 ti_i2c_write_2(sc, I2C_REG_BUF, reg); 626 627 /* 628 * 8. Take the I2C controller out of reset by setting the 629 * I2Ci.I2C_CON[15] I2C_EN bit to 1. 630 * 631 * 23.1.5.1.1.1.2 - Initialize the I2C Controller 632 * 633 * To initialize the I2C controller, perform the following steps: 634 * 635 * 1. Configure the I2Ci.I2C_CON register: 636 * . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit 637 * (0: slave, 1: master). 638 * . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX 639 * bit (0: receiver, 1: transmitter). 640 */ 641 642 /* Enable the I2C controller in master mode. */ 643 sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST; 644 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 645 646 /* 647 * 2. If using an interrupt to transmit/receive data, set the 648 * corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4] 649 * XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY 650 * bit for the receive interrupt). 651 */ 652 653 /* Set the interrupts we want to be notified. */ 654 reg = I2C_IE_XDR | /* Transmit draining interrupt. */ 655 I2C_IE_XRDY | /* Transmit Data Ready interrupt. */ 656 I2C_IE_RDR | /* Receive draining interrupt. */ 657 I2C_IE_RRDY | /* Receive Data Ready interrupt. */ 658 I2C_IE_ARDY | /* Register Access Ready interrupt. */ 659 I2C_IE_NACK | /* No Acknowledgment interrupt. */ 660 I2C_IE_AL; /* Arbitration lost interrupt. */ 661 662 /* Enable the interrupts. */ 663 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg); 664 665 /* 666 * 3. If using DMA to receive/transmit data, set to 1 the corresponding 667 * bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN 668 * bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit 669 * for the transmit DMA channel). 670 * 671 * Not using DMA for now, so ignore this. 672 */ 673 674 return (0); 675 } 676 677 static int 678 ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 679 { 680 struct ti_i2c_softc *sc; 681 int err; 682 683 sc = device_get_softc(dev); 684 TI_I2C_LOCK(sc); 685 err = ti_i2c_reset(sc, speed); 686 TI_I2C_UNLOCK(sc); 687 if (err) 688 return (err); 689 690 return (IIC_ENOADDR); 691 } 692 693 static int 694 ti_i2c_activate(device_t dev) 695 { 696 clk_ident_t clk; 697 int err; 698 struct ti_i2c_softc *sc; 699 700 sc = (struct ti_i2c_softc*)device_get_softc(dev); 701 702 /* 703 * 1. Enable the functional and interface clocks (see Section 704 * 23.1.5.1.1.1.1). 705 */ 706 clk = I2C0_CLK + sc->device_id; 707 err = ti_prcm_clk_enable(clk); 708 if (err) 709 return (err); 710 711 return (ti_i2c_reset(sc, IIC_UNKNOWN)); 712 } 713 714 /** 715 * ti_i2c_deactivate - deactivates the controller and releases resources 716 * @dev: i2c device handle 717 * 718 * 719 * 720 * LOCKING: 721 * Assumed called in an atomic context. 722 * 723 * RETURNS: 724 * nothing 725 */ 726 static void 727 ti_i2c_deactivate(device_t dev) 728 { 729 struct ti_i2c_softc *sc = device_get_softc(dev); 730 clk_ident_t clk; 731 732 /* Disable the controller - cancel all transactions. */ 733 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff); 734 ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff); 735 ti_i2c_write_2(sc, I2C_REG_CON, 0); 736 737 /* Release the interrupt handler. */ 738 if (sc->sc_irq_h != NULL) { 739 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h); 740 sc->sc_irq_h = NULL; 741 } 742 743 bus_generic_detach(sc->sc_dev); 744 745 /* Unmap the I2C controller registers. */ 746 if (sc->sc_mem_res != NULL) { 747 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 748 sc->sc_mem_res = NULL; 749 } 750 751 /* Release the IRQ resource. */ 752 if (sc->sc_irq_res != NULL) { 753 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 754 sc->sc_irq_res = NULL; 755 } 756 757 /* Finally disable the functional and interface clocks. */ 758 clk = I2C0_CLK + sc->device_id; 759 ti_prcm_clk_disable(clk); 760 } 761 762 static int 763 ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS) 764 { 765 int clk, psc, sclh, scll; 766 struct ti_i2c_softc *sc; 767 768 sc = arg1; 769 770 TI_I2C_LOCK(sc); 771 /* Get the system prescaler value. */ 772 psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1; 773 774 /* Get the bitrate. */ 775 scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK; 776 sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK; 777 778 clk = I2C_CLK / psc / (scll + 7 + sclh + 5); 779 TI_I2C_UNLOCK(sc); 780 781 return (sysctl_handle_int(oidp, &clk, 0, req)); 782 } 783 784 static int 785 ti_i2c_sysctl_timeout(SYSCTL_HANDLER_ARGS) 786 { 787 struct ti_i2c_softc *sc; 788 unsigned int val; 789 int err; 790 791 sc = arg1; 792 793 /* 794 * MTX_DEF lock can't be held while doing uimove in 795 * sysctl_handle_int 796 */ 797 TI_I2C_LOCK(sc); 798 val = sc->sc_timeout; 799 TI_I2C_UNLOCK(sc); 800 801 err = sysctl_handle_int(oidp, &val, 0, req); 802 /* Write request? */ 803 if ((err == 0) && (req->newptr != NULL)) { 804 TI_I2C_LOCK(sc); 805 sc->sc_timeout = val; 806 TI_I2C_UNLOCK(sc); 807 } 808 809 return (err); 810 } 811 812 static int 813 ti_i2c_probe(device_t dev) 814 { 815 816 if (!ofw_bus_status_okay(dev)) 817 return (ENXIO); 818 if (!ofw_bus_is_compatible(dev, "ti,i2c")) 819 return (ENXIO); 820 device_set_desc(dev, "TI I2C Controller"); 821 822 return (0); 823 } 824 825 static int 826 ti_i2c_attach(device_t dev) 827 { 828 int err, rid; 829 phandle_t node; 830 struct ti_i2c_softc *sc; 831 struct sysctl_ctx_list *ctx; 832 struct sysctl_oid_list *tree; 833 uint16_t fifosz; 834 835 sc = device_get_softc(dev); 836 sc->sc_dev = dev; 837 838 /* Get the i2c device id from FDT. */ 839 node = ofw_bus_get_node(dev); 840 if ((OF_getencprop(node, "i2c-device-id", &sc->device_id, 841 sizeof(sc->device_id))) <= 0) { 842 device_printf(dev, "missing i2c-device-id attribute in FDT\n"); 843 return (ENXIO); 844 } 845 846 /* Get the memory resource for the register mapping. */ 847 rid = 0; 848 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 849 RF_ACTIVE); 850 if (sc->sc_mem_res == NULL) { 851 device_printf(dev, "Cannot map registers.\n"); 852 return (ENXIO); 853 } 854 855 /* Allocate our IRQ resource. */ 856 rid = 0; 857 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 858 RF_ACTIVE | RF_SHAREABLE); 859 if (sc->sc_irq_res == NULL) { 860 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 861 device_printf(dev, "Cannot allocate interrupt.\n"); 862 return (ENXIO); 863 } 864 865 TI_I2C_LOCK_INIT(sc); 866 867 /* First of all, we _must_ activate the H/W. */ 868 err = ti_i2c_activate(dev); 869 if (err) { 870 device_printf(dev, "ti_i2c_activate failed\n"); 871 goto out; 872 } 873 874 /* Read the version number of the I2C module */ 875 sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff; 876 877 /* Get the fifo size. */ 878 fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT); 879 fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT; 880 fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK; 881 882 device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n", 883 sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz); 884 885 /* Set the FIFO threshold to 5 for now. */ 886 sc->sc_fifo_trsh = 5; 887 888 /* Set I2C bus timeout */ 889 sc->sc_timeout = 5*hz; 890 891 ctx = device_get_sysctl_ctx(dev); 892 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 893 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock", 894 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0, 895 ti_i2c_sysctl_clk, "IU", "I2C bus clock"); 896 897 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_timeout", 898 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0, 899 ti_i2c_sysctl_timeout, "IU", "I2C bus timeout (in ticks)"); 900 901 /* Activate the interrupt. */ 902 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 903 NULL, ti_i2c_intr, sc, &sc->sc_irq_h); 904 if (err) 905 goto out; 906 907 /* Attach the iicbus. */ 908 if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { 909 device_printf(dev, "could not allocate iicbus instance\n"); 910 err = ENXIO; 911 goto out; 912 } 913 914 /* Probe and attach the iicbus */ 915 bus_generic_attach(dev); 916 917 out: 918 if (err) { 919 ti_i2c_deactivate(dev); 920 TI_I2C_LOCK_DESTROY(sc); 921 } 922 923 return (err); 924 } 925 926 static int 927 ti_i2c_detach(device_t dev) 928 { 929 struct ti_i2c_softc *sc; 930 int rv; 931 932 sc = device_get_softc(dev); 933 ti_i2c_deactivate(dev); 934 TI_I2C_LOCK_DESTROY(sc); 935 if (sc->sc_iicbus && 936 (rv = device_delete_child(dev, sc->sc_iicbus)) != 0) 937 return (rv); 938 939 return (0); 940 } 941 942 static phandle_t 943 ti_i2c_get_node(device_t bus, device_t dev) 944 { 945 946 /* Share controller node with iibus device. */ 947 return (ofw_bus_get_node(bus)); 948 } 949 950 static device_method_t ti_i2c_methods[] = { 951 /* Device interface */ 952 DEVMETHOD(device_probe, ti_i2c_probe), 953 DEVMETHOD(device_attach, ti_i2c_attach), 954 DEVMETHOD(device_detach, ti_i2c_detach), 955 956 /* OFW methods */ 957 DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node), 958 959 /* iicbus interface */ 960 DEVMETHOD(iicbus_callback, iicbus_null_callback), 961 DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset), 962 DEVMETHOD(iicbus_transfer, ti_i2c_transfer), 963 964 DEVMETHOD_END 965 }; 966 967 static driver_t ti_i2c_driver = { 968 "iichb", 969 ti_i2c_methods, 970 sizeof(struct ti_i2c_softc), 971 }; 972 973 static devclass_t ti_i2c_devclass; 974 975 DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, ti_i2c_devclass, 0, 0); 976 DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, iicbus_devclass, 0, 0); 977 978 MODULE_DEPEND(ti_iic, ti_prcm, 1, 1, 1); 979 MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1); 980