1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 5 * Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /** 31 * Driver for the I2C module on the TI SoC. 32 * 33 * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c). 34 * 35 * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses, 36 * 32 bit data access is not allowed and can corrupt register content. 37 * 38 * This driver currently doesn't use DMA for the transfer, although I hope to 39 * incorporate that sometime in the future. The idea being that for transaction 40 * larger than a certain size the DMA engine is used, for anything less the 41 * normal interrupt/fifo driven option is used. 42 */ 43 44 #include <sys/cdefs.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/bus.h> 48 #include <sys/conf.h> 49 #include <sys/kernel.h> 50 #include <sys/lock.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/module.h> 54 #include <sys/mutex.h> 55 #include <sys/rman.h> 56 #include <sys/sysctl.h> 57 #include <machine/bus.h> 58 59 #include <dev/ofw/openfirm.h> 60 #include <dev/ofw/ofw_bus.h> 61 #include <dev/ofw/ofw_bus_subr.h> 62 63 #include <arm/ti/ti_cpuid.h> 64 #include <arm/ti/ti_sysc.h> 65 #include <arm/ti/ti_i2c.h> 66 67 #include <dev/iicbus/iiconf.h> 68 #include <dev/iicbus/iicbus.h> 69 70 #include "iicbus_if.h" 71 72 /** 73 * I2C device driver context, a pointer to this is stored in the device 74 * driver structure. 75 */ 76 struct ti_i2c_softc 77 { 78 device_t sc_dev; 79 struct resource* sc_irq_res; 80 struct resource* sc_mem_res; 81 device_t sc_iicbus; 82 83 void* sc_irq_h; 84 85 struct mtx sc_mtx; 86 87 struct iic_msg* sc_buffer; 88 int sc_bus_inuse; 89 int sc_buffer_pos; 90 int sc_error; 91 int sc_fifo_trsh; 92 int sc_timeout; 93 94 uint16_t sc_con_reg; 95 uint16_t sc_rev; 96 }; 97 98 struct ti_i2c_clock_config 99 { 100 u_int frequency; /* Bus frequency in Hz */ 101 uint8_t psc; /* Fast/Standard mode prescale divider */ 102 uint8_t scll; /* Fast/Standard mode SCL low time */ 103 uint8_t sclh; /* Fast/Standard mode SCL high time */ 104 uint8_t hsscll; /* High Speed mode SCL low time */ 105 uint8_t hssclh; /* High Speed mode SCL high time */ 106 }; 107 108 #if defined(SOC_OMAP4) 109 /* 110 * OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)). 111 * The prescaler values for 100KHz and 400KHz modes come from the table in the 112 * OMAP4 TRM. The table doesn't list 1MHz; these values should give that speed. 113 */ 114 static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = { 115 { 100000, 23, 13, 15, 0, 0}, 116 { 400000, 9, 5, 7, 0, 0}, 117 { 1000000, 3, 5, 7, 0, 0}, 118 /* { 3200000, 1, 113, 115, 7, 10}, - HS mode */ 119 { 0 /* Table terminator */ } 120 }; 121 #endif 122 123 #if defined(SOC_TI_AM335X) 124 /* 125 * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5)) 126 * In all cases we prescale the clock to 24MHz as recommended in the manual. 127 */ 128 static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = { 129 { 100000, 1, 111, 117, 0, 0}, 130 { 400000, 1, 23, 25, 0, 0}, 131 { 1000000, 1, 5, 7, 0, 0}, 132 { 0 /* Table terminator */ } 133 }; 134 #endif 135 136 /** 137 * Locking macros used throughout the driver 138 */ 139 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 140 #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 141 #define TI_I2C_LOCK_INIT(_sc) \ 142 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 143 "ti_i2c", MTX_DEF) 144 #define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx) 145 #define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) 146 #define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED) 147 148 #ifdef DEBUG 149 #define ti_i2c_dbg(_sc, fmt, args...) \ 150 device_printf((_sc)->sc_dev, fmt, ##args) 151 #else 152 #define ti_i2c_dbg(_sc, fmt, args...) 153 #endif 154 155 /** 156 * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers 157 * @sc: I2C device context 158 * @off: the byte offset within the register bank to read from. 159 * 160 * 161 * LOCKING: 162 * No locking required 163 * 164 * RETURNS: 165 * 16-bit value read from the register. 166 */ 167 static inline uint16_t 168 ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off) 169 { 170 171 return (bus_read_2(sc->sc_mem_res, off)); 172 } 173 174 /** 175 * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers 176 * @sc: I2C device context 177 * @off: the byte offset within the register bank to read from. 178 * @val: the value to write into the register 179 * 180 * LOCKING: 181 * No locking required 182 * 183 * RETURNS: 184 * 16-bit value read from the register. 185 */ 186 static inline void 187 ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val) 188 { 189 190 bus_write_2(sc->sc_mem_res, off, val); 191 } 192 193 static int 194 ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status) 195 { 196 int amount, done, i; 197 198 done = 0; 199 amount = 0; 200 /* Check for the error conditions. */ 201 if (status & I2C_STAT_NACK) { 202 /* No ACK from slave. */ 203 ti_i2c_dbg(sc, "NACK\n"); 204 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK); 205 sc->sc_error = ENXIO; 206 } else if (status & I2C_STAT_AL) { 207 /* Arbitration lost. */ 208 ti_i2c_dbg(sc, "Arbitration lost\n"); 209 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL); 210 sc->sc_error = ENXIO; 211 } 212 213 /* Check if we have finished. */ 214 if (status & I2C_STAT_ARDY) { 215 /* Register access ready - transaction complete basically. */ 216 ti_i2c_dbg(sc, "ARDY transaction complete\n"); 217 if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) { 218 ti_i2c_write_2(sc, I2C_REG_CON, 219 sc->sc_con_reg | I2C_CON_STP); 220 } 221 ti_i2c_write_2(sc, I2C_REG_STATUS, 222 I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY | 223 I2C_STAT_XDR | I2C_STAT_XRDY); 224 return (1); 225 } 226 227 if (sc->sc_buffer->flags & IIC_M_RD) { 228 /* Read some data. */ 229 if (status & I2C_STAT_RDR) { 230 /* 231 * Receive draining interrupt - last data received. 232 * The set FIFO threshold won't be reached to trigger 233 * RRDY. 234 */ 235 ti_i2c_dbg(sc, "Receive draining interrupt\n"); 236 237 /* 238 * Drain the FIFO. Read the pending data in the FIFO. 239 */ 240 amount = sc->sc_buffer->len - sc->sc_buffer_pos; 241 } else if (status & I2C_STAT_RRDY) { 242 /* 243 * Receive data ready interrupt - FIFO has reached the 244 * set threshold. 245 */ 246 ti_i2c_dbg(sc, "Receive data ready interrupt\n"); 247 248 amount = min(sc->sc_fifo_trsh, 249 sc->sc_buffer->len - sc->sc_buffer_pos); 250 } 251 252 /* Read the bytes from the fifo. */ 253 for (i = 0; i < amount; i++) 254 sc->sc_buffer->buf[sc->sc_buffer_pos++] = 255 (uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff); 256 257 if (status & I2C_STAT_RDR) 258 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR); 259 if (status & I2C_STAT_RRDY) 260 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY); 261 262 } else { 263 /* Write some data. */ 264 if (status & I2C_STAT_XDR) { 265 /* 266 * Transmit draining interrupt - FIFO level is below 267 * the set threshold and the amount of data still to 268 * be transferred won't reach the set FIFO threshold. 269 */ 270 ti_i2c_dbg(sc, "Transmit draining interrupt\n"); 271 272 /* 273 * Drain the TX data. Write the pending data in the 274 * FIFO. 275 */ 276 amount = sc->sc_buffer->len - sc->sc_buffer_pos; 277 } else if (status & I2C_STAT_XRDY) { 278 /* 279 * Transmit data ready interrupt - the FIFO level 280 * is below the set threshold. 281 */ 282 ti_i2c_dbg(sc, "Transmit data ready interrupt\n"); 283 284 amount = min(sc->sc_fifo_trsh, 285 sc->sc_buffer->len - sc->sc_buffer_pos); 286 } 287 288 /* Write the bytes from the fifo. */ 289 for (i = 0; i < amount; i++) 290 ti_i2c_write_2(sc, I2C_REG_DATA, 291 sc->sc_buffer->buf[sc->sc_buffer_pos++]); 292 293 if (status & I2C_STAT_XDR) 294 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR); 295 if (status & I2C_STAT_XRDY) 296 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY); 297 } 298 299 return (done); 300 } 301 302 /** 303 * ti_i2c_intr - interrupt handler for the I2C module 304 * @dev: i2c device handle 305 * 306 * 307 * 308 * LOCKING: 309 * Called from timer context 310 * 311 * RETURNS: 312 * EH_HANDLED or EH_NOT_HANDLED 313 */ 314 static void 315 ti_i2c_intr(void *arg) 316 { 317 int done; 318 struct ti_i2c_softc *sc; 319 uint16_t events, status; 320 321 sc = (struct ti_i2c_softc *)arg; 322 323 TI_I2C_LOCK(sc); 324 325 status = ti_i2c_read_2(sc, I2C_REG_STATUS); 326 if (status == 0) { 327 TI_I2C_UNLOCK(sc); 328 return; 329 } 330 331 /* Save enabled interrupts. */ 332 events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET); 333 334 /* We only care about enabled interrupts. */ 335 status &= events; 336 337 done = 0; 338 339 if (sc->sc_buffer != NULL) 340 done = ti_i2c_transfer_intr(sc, status); 341 else { 342 ti_i2c_dbg(sc, "Transfer interrupt without buffer\n"); 343 sc->sc_error = EINVAL; 344 done = 1; 345 } 346 347 if (done) 348 /* Wakeup the process that started the transaction. */ 349 wakeup(sc); 350 351 TI_I2C_UNLOCK(sc); 352 } 353 354 /** 355 * ti_i2c_transfer - called to perform the transfer 356 * @dev: i2c device handle 357 * @msgs: the messages to send/receive 358 * @nmsgs: the number of messages in the msgs array 359 * 360 * 361 * LOCKING: 362 * Internally locked 363 * 364 * RETURNS: 365 * 0 on function succeeded 366 * EINVAL if invalid message is passed as an arg 367 */ 368 static int 369 ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 370 { 371 int err, i, repstart, timeout; 372 struct ti_i2c_softc *sc; 373 uint16_t reg; 374 375 sc = device_get_softc(dev); 376 TI_I2C_LOCK(sc); 377 378 /* If the controller is busy wait until it is available. */ 379 while (sc->sc_bus_inuse == 1) 380 mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0); 381 382 /* Now we have control over the I2C controller. */ 383 sc->sc_bus_inuse = 1; 384 385 err = 0; 386 repstart = 0; 387 for (i = 0; i < nmsgs; i++) { 388 sc->sc_buffer = &msgs[i]; 389 sc->sc_buffer_pos = 0; 390 sc->sc_error = 0; 391 392 /* Zero byte transfers aren't allowed. */ 393 if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL || 394 sc->sc_buffer->len == 0) { 395 err = EINVAL; 396 break; 397 } 398 399 /* Check if the i2c bus is free. */ 400 if (repstart == 0) { 401 /* 402 * On repeated start we send the START condition while 403 * the bus _is_ busy. 404 */ 405 timeout = 0; 406 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) { 407 if (timeout++ > 100) { 408 err = EBUSY; 409 goto out; 410 } 411 DELAY(1000); 412 } 413 timeout = 0; 414 } else 415 repstart = 0; 416 417 if (sc->sc_buffer->flags & IIC_M_NOSTOP) 418 repstart = 1; 419 420 /* Set the slave address. */ 421 ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1); 422 423 /* Write the data length. */ 424 ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len); 425 426 /* Clear the RX and the TX FIFO. */ 427 reg = ti_i2c_read_2(sc, I2C_REG_BUF); 428 reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR; 429 ti_i2c_write_2(sc, I2C_REG_BUF, reg); 430 431 reg = sc->sc_con_reg | I2C_CON_STT; 432 if (repstart == 0) 433 reg |= I2C_CON_STP; 434 if ((sc->sc_buffer->flags & IIC_M_RD) == 0) 435 reg |= I2C_CON_TRX; 436 ti_i2c_write_2(sc, I2C_REG_CON, reg); 437 438 /* Wait for an event. */ 439 err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", sc->sc_timeout); 440 if (err == 0) 441 err = sc->sc_error; 442 443 if (err) 444 break; 445 } 446 447 out: 448 if (timeout == 0) { 449 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) { 450 if (timeout++ > 100) 451 break; 452 DELAY(1000); 453 } 454 } 455 /* Put the controller in master mode again. */ 456 if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0) 457 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 458 459 sc->sc_buffer = NULL; 460 sc->sc_bus_inuse = 0; 461 462 /* Wake up the processes that are waiting for the bus. */ 463 wakeup(sc); 464 465 TI_I2C_UNLOCK(sc); 466 467 return (err); 468 } 469 470 static int 471 ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed) 472 { 473 int timeout; 474 struct ti_i2c_clock_config *clkcfg; 475 u_int busfreq; 476 uint16_t fifo_trsh, reg, scll, sclh; 477 478 switch (ti_chip()) { 479 #ifdef SOC_OMAP4 480 case CHIP_OMAP_4: 481 clkcfg = ti_omap4_i2c_clock_configs; 482 break; 483 #endif 484 #ifdef SOC_TI_AM335X 485 case CHIP_AM335X: 486 clkcfg = ti_am335x_i2c_clock_configs; 487 break; 488 #endif 489 default: 490 panic("Unknown TI SoC, unable to reset the i2c"); 491 } 492 493 /* 494 * If we haven't attached the bus yet, just init at the default slow 495 * speed. This lets us get the hardware initialized enough to attach 496 * the bus which is where the real speed configuration is handled. After 497 * the bus is attached, get the configured speed from it. Search the 498 * configuration table for the best speed we can do that doesn't exceed 499 * the requested speed. 500 */ 501 if (sc->sc_iicbus == NULL) 502 busfreq = 100000; 503 else 504 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); 505 for (;;) { 506 if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq) 507 break; 508 clkcfg++; 509 } 510 511 /* 512 * 23.1.4.3 - HS I2C Software Reset 513 * From OMAP4 TRM at page 4068. 514 * 515 * 1. Ensure that the module is disabled. 516 */ 517 sc->sc_con_reg = 0; 518 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 519 520 /* 2. Issue a softreset to the controller. */ 521 bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST); 522 523 /* 524 * 3. Enable the module. 525 * The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module 526 * is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1. 527 */ 528 ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN); 529 530 /* 4. Wait for the software reset to complete. */ 531 timeout = 0; 532 while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) { 533 if (timeout++ > 100) 534 return (EBUSY); 535 DELAY(100); 536 } 537 538 /* 539 * Disable the I2C controller once again, now that the reset has 540 * finished. 541 */ 542 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 543 544 /* 545 * The following sequence is taken from the OMAP4 TRM at page 4077. 546 * 547 * 1. Enable the functional and interface clocks (see Section 548 * 23.1.5.1.1.1.1). Done at ti_i2c_activate(). 549 * 550 * 2. Program the prescaler to obtain an approximately 12MHz internal 551 * sampling clock (I2Ci_INTERNAL_CLK) by programming the 552 * corresponding value in the I2Ci.I2C_PSC[3:0] PSC field. 553 * This value depends on the frequency of the functional clock 554 * (I2Ci_FCLK). Because this frequency is 96MHz, the 555 * I2Ci.I2C_PSC[7:0] PSC field value is 0x7. 556 */ 557 ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc); 558 559 /* 560 * 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH 561 * bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps. 562 * These values depend on the internal sampling clock frequency 563 * (see Table 23-8). 564 */ 565 scll = clkcfg->scll & I2C_SCLL_MASK; 566 sclh = clkcfg->sclh & I2C_SCLH_MASK; 567 568 /* 569 * 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and 570 * I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of 571 * 400K bps or 3.4M bps (for the second phase of HS mode). These 572 * values depend on the internal sampling clock frequency (see 573 * Table 23-8). 574 * 575 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line 576 * capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional 577 * Multiplexing and Configuration). 578 */ 579 switch (ti_chip()) { 580 #ifdef SOC_OMAP4 581 case CHIP_OMAP_4: 582 if ((clkcfg->hsscll + clkcfg->hssclh) > 0) { 583 scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT; 584 sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT; 585 sc->sc_con_reg |= I2C_CON_OPMODE_HS; 586 } 587 break; 588 #endif 589 } 590 591 /* Write the selected bit rate. */ 592 ti_i2c_write_2(sc, I2C_REG_SCLL, scll); 593 ti_i2c_write_2(sc, I2C_REG_SCLH, sclh); 594 595 /* 596 * 6. Configure the Own Address of the I2C controller by storing it in 597 * the I2Ci.I2C_OA0 register. Up to four Own Addresses can be 598 * programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3) 599 * for each I2C controller. 600 * 601 * Note: For a 10-bit address, set the corresponding expand Own Address 602 * bit in the I2Ci.I2C_CON register. 603 * 604 * Driver currently always in single master mode so ignore this step. 605 */ 606 607 /* 608 * 7. Set the TX threshold (in transmitter mode) and the RX threshold 609 * (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to 610 * (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX 611 * threshold - 1), where the TX and RX thresholds are greater than 612 * or equal to 1. 613 * 614 * The threshold is set to 5 for now. 615 */ 616 fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK; 617 reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT); 618 ti_i2c_write_2(sc, I2C_REG_BUF, reg); 619 620 /* 621 * 8. Take the I2C controller out of reset by setting the 622 * I2Ci.I2C_CON[15] I2C_EN bit to 1. 623 * 624 * 23.1.5.1.1.1.2 - Initialize the I2C Controller 625 * 626 * To initialize the I2C controller, perform the following steps: 627 * 628 * 1. Configure the I2Ci.I2C_CON register: 629 * . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit 630 * (0: slave, 1: master). 631 * . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX 632 * bit (0: receiver, 1: transmitter). 633 */ 634 635 /* Enable the I2C controller in master mode. */ 636 sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST; 637 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 638 639 /* 640 * 2. If using an interrupt to transmit/receive data, set the 641 * corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4] 642 * XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY 643 * bit for the receive interrupt). 644 */ 645 646 /* Set the interrupts we want to be notified. */ 647 reg = I2C_IE_XDR | /* Transmit draining interrupt. */ 648 I2C_IE_XRDY | /* Transmit Data Ready interrupt. */ 649 I2C_IE_RDR | /* Receive draining interrupt. */ 650 I2C_IE_RRDY | /* Receive Data Ready interrupt. */ 651 I2C_IE_ARDY | /* Register Access Ready interrupt. */ 652 I2C_IE_NACK | /* No Acknowledgment interrupt. */ 653 I2C_IE_AL; /* Arbitration lost interrupt. */ 654 655 /* Enable the interrupts. */ 656 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg); 657 658 /* 659 * 3. If using DMA to receive/transmit data, set to 1 the corresponding 660 * bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN 661 * bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit 662 * for the transmit DMA channel). 663 * 664 * Not using DMA for now, so ignore this. 665 */ 666 667 return (0); 668 } 669 670 static int 671 ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 672 { 673 struct ti_i2c_softc *sc; 674 int err; 675 676 sc = device_get_softc(dev); 677 TI_I2C_LOCK(sc); 678 err = ti_i2c_reset(sc, speed); 679 TI_I2C_UNLOCK(sc); 680 if (err) 681 return (err); 682 683 return (IIC_ENOADDR); 684 } 685 686 static int 687 ti_i2c_activate(device_t dev) 688 { 689 int err; 690 struct ti_i2c_softc *sc; 691 692 sc = (struct ti_i2c_softc*)device_get_softc(dev); 693 694 /* 695 * 1. Enable the functional and interface clocks (see Section 696 * 23.1.5.1.1.1.1). 697 */ 698 err = ti_sysc_clock_enable(device_get_parent(dev)); 699 if (err) 700 return (err); 701 702 return (ti_i2c_reset(sc, IIC_UNKNOWN)); 703 } 704 705 /** 706 * ti_i2c_deactivate - deactivates the controller and releases resources 707 * @dev: i2c device handle 708 * 709 * 710 * 711 * LOCKING: 712 * Assumed called in an atomic context. 713 * 714 * RETURNS: 715 * nothing 716 */ 717 static void 718 ti_i2c_deactivate(device_t dev) 719 { 720 struct ti_i2c_softc *sc = device_get_softc(dev); 721 722 /* Disable the controller - cancel all transactions. */ 723 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff); 724 ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff); 725 ti_i2c_write_2(sc, I2C_REG_CON, 0); 726 727 /* Release the interrupt handler. */ 728 if (sc->sc_irq_h != NULL) { 729 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h); 730 sc->sc_irq_h = NULL; 731 } 732 733 /* Unmap the I2C controller registers. */ 734 if (sc->sc_mem_res != NULL) { 735 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 736 sc->sc_mem_res = NULL; 737 } 738 739 /* Release the IRQ resource. */ 740 if (sc->sc_irq_res != NULL) { 741 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 742 sc->sc_irq_res = NULL; 743 } 744 745 /* Finally disable the functional and interface clocks. */ 746 ti_sysc_clock_disable(device_get_parent(dev)); 747 } 748 749 static int 750 ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS) 751 { 752 int clk, psc, sclh, scll; 753 struct ti_i2c_softc *sc; 754 755 sc = arg1; 756 757 TI_I2C_LOCK(sc); 758 /* Get the system prescaler value. */ 759 psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1; 760 761 /* Get the bitrate. */ 762 scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK; 763 sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK; 764 765 clk = I2C_CLK / psc / (scll + 7 + sclh + 5); 766 TI_I2C_UNLOCK(sc); 767 768 return (sysctl_handle_int(oidp, &clk, 0, req)); 769 } 770 771 static int 772 ti_i2c_sysctl_timeout(SYSCTL_HANDLER_ARGS) 773 { 774 struct ti_i2c_softc *sc; 775 unsigned int val; 776 int err; 777 778 sc = arg1; 779 780 /* 781 * MTX_DEF lock can't be held while doing uimove in 782 * sysctl_handle_int 783 */ 784 TI_I2C_LOCK(sc); 785 val = sc->sc_timeout; 786 TI_I2C_UNLOCK(sc); 787 788 err = sysctl_handle_int(oidp, &val, 0, req); 789 /* Write request? */ 790 if ((err == 0) && (req->newptr != NULL)) { 791 TI_I2C_LOCK(sc); 792 sc->sc_timeout = val; 793 TI_I2C_UNLOCK(sc); 794 } 795 796 return (err); 797 } 798 799 static int 800 ti_i2c_probe(device_t dev) 801 { 802 803 if (!ofw_bus_status_okay(dev)) 804 return (ENXIO); 805 if (!ofw_bus_is_compatible(dev, "ti,omap4-i2c")) 806 return (ENXIO); 807 device_set_desc(dev, "TI I2C Controller"); 808 809 return (0); 810 } 811 812 static int 813 ti_i2c_attach(device_t dev) 814 { 815 int err, rid; 816 struct ti_i2c_softc *sc; 817 struct sysctl_ctx_list *ctx; 818 struct sysctl_oid_list *tree; 819 uint16_t fifosz; 820 821 sc = device_get_softc(dev); 822 sc->sc_dev = dev; 823 824 /* Get the memory resource for the register mapping. */ 825 rid = 0; 826 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 827 RF_ACTIVE); 828 if (sc->sc_mem_res == NULL) { 829 device_printf(dev, "Cannot map registers.\n"); 830 return (ENXIO); 831 } 832 833 /* Allocate our IRQ resource. */ 834 rid = 0; 835 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 836 RF_ACTIVE | RF_SHAREABLE); 837 if (sc->sc_irq_res == NULL) { 838 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 839 device_printf(dev, "Cannot allocate interrupt.\n"); 840 return (ENXIO); 841 } 842 843 TI_I2C_LOCK_INIT(sc); 844 845 /* First of all, we _must_ activate the H/W. */ 846 err = ti_i2c_activate(dev); 847 if (err) { 848 device_printf(dev, "ti_i2c_activate failed\n"); 849 goto out; 850 } 851 852 /* Read the version number of the I2C module */ 853 sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff; 854 855 /* Get the fifo size. */ 856 fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT); 857 fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT; 858 fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK; 859 860 device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n", 861 sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz); 862 863 /* Set the FIFO threshold to 5 for now. */ 864 sc->sc_fifo_trsh = 5; 865 866 /* Set I2C bus timeout */ 867 sc->sc_timeout = 5*hz; 868 869 ctx = device_get_sysctl_ctx(dev); 870 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 871 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock", 872 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0, 873 ti_i2c_sysctl_clk, "IU", "I2C bus clock"); 874 875 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_timeout", 876 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0, 877 ti_i2c_sysctl_timeout, "IU", "I2C bus timeout (in ticks)"); 878 879 /* Activate the interrupt. */ 880 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 881 NULL, ti_i2c_intr, sc, &sc->sc_irq_h); 882 if (err) 883 goto out; 884 885 /* Attach the iicbus. */ 886 if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { 887 device_printf(dev, "could not allocate iicbus instance\n"); 888 err = ENXIO; 889 goto out; 890 } 891 892 /* Probe and attach the iicbus when interrupts are available. */ 893 err = bus_delayed_attach_children(dev); 894 895 out: 896 if (err) { 897 ti_i2c_deactivate(dev); 898 TI_I2C_LOCK_DESTROY(sc); 899 } 900 901 return (err); 902 } 903 904 static int 905 ti_i2c_detach(device_t dev) 906 { 907 struct ti_i2c_softc *sc; 908 int rv; 909 910 sc = device_get_softc(dev); 911 912 if ((rv = bus_generic_detach(dev)) != 0) { 913 device_printf(dev, "cannot detach child devices\n"); 914 return (rv); 915 } 916 917 if (sc->sc_iicbus && 918 (rv = device_delete_child(dev, sc->sc_iicbus)) != 0) 919 return (rv); 920 921 ti_i2c_deactivate(dev); 922 TI_I2C_LOCK_DESTROY(sc); 923 924 return (0); 925 } 926 927 static phandle_t 928 ti_i2c_get_node(device_t bus, device_t dev) 929 { 930 931 /* Share controller node with iibus device. */ 932 return (ofw_bus_get_node(bus)); 933 } 934 935 static device_method_t ti_i2c_methods[] = { 936 /* Device interface */ 937 DEVMETHOD(device_probe, ti_i2c_probe), 938 DEVMETHOD(device_attach, ti_i2c_attach), 939 DEVMETHOD(device_detach, ti_i2c_detach), 940 941 /* Bus interface */ 942 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 943 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 944 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 945 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 946 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 947 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 948 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 949 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 950 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 951 952 /* OFW methods */ 953 DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node), 954 955 /* iicbus interface */ 956 DEVMETHOD(iicbus_callback, iicbus_null_callback), 957 DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset), 958 DEVMETHOD(iicbus_transfer, ti_i2c_transfer), 959 960 DEVMETHOD_END 961 }; 962 963 static driver_t ti_i2c_driver = { 964 "iichb", 965 ti_i2c_methods, 966 sizeof(struct ti_i2c_softc), 967 }; 968 969 DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, 0, 0); 970 DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, 0, 0); 971 972 MODULE_DEPEND(ti_iic, ti_sysc, 1, 1, 1); 973 MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1); 974