1 /*- 2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /** 29 * Driver for the I2C module on the TI SoC. 30 * 31 * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c). 32 * 33 * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses, 34 * 32 bit data access is not allowed and can corrupt register content. 35 * 36 * This driver currently doesn't use DMA for the transfer, although I hope to 37 * incorporate that sometime in the future. The idea being that for transaction 38 * larger than a certain size the DMA engine is used, for anything less the 39 * normal interrupt/fifo driven option is used. 40 * 41 * 42 * WARNING: This driver uses mtx_sleep and interrupts to perform transactions, 43 * which means you can't do a transaction during startup before the interrupts 44 * have been enabled. Hint - the freebsd function config_intrhook_establish(). 45 */ 46 47 #include <sys/cdefs.h> 48 __FBSDID("$FreeBSD$"); 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/bus.h> 53 #include <sys/conf.h> 54 #include <sys/kernel.h> 55 #include <sys/lock.h> 56 #include <sys/mbuf.h> 57 #include <sys/malloc.h> 58 #include <sys/module.h> 59 #include <sys/mutex.h> 60 #include <sys/rman.h> 61 #include <sys/sysctl.h> 62 #include <machine/bus.h> 63 64 #include <dev/ofw/openfirm.h> 65 #include <dev/ofw/ofw_bus.h> 66 #include <dev/ofw/ofw_bus_subr.h> 67 68 #include <arm/ti/ti_cpuid.h> 69 #include <arm/ti/ti_prcm.h> 70 #include <arm/ti/ti_i2c.h> 71 72 #include <dev/iicbus/iiconf.h> 73 #include <dev/iicbus/iicbus.h> 74 75 #include "iicbus_if.h" 76 77 /** 78 * I2C device driver context, a pointer to this is stored in the device 79 * driver structure. 80 */ 81 struct ti_i2c_softc 82 { 83 device_t sc_dev; 84 uint32_t device_id; 85 struct resource* sc_irq_res; 86 struct resource* sc_mem_res; 87 device_t sc_iicbus; 88 89 void* sc_irq_h; 90 91 struct mtx sc_mtx; 92 93 struct iic_msg* sc_buffer; 94 int sc_bus_inuse; 95 int sc_buffer_pos; 96 int sc_error; 97 int sc_fifo_trsh; 98 99 uint16_t sc_con_reg; 100 uint16_t sc_rev; 101 }; 102 103 struct ti_i2c_clock_config 104 { 105 u_int frequency; /* Bus frequency in Hz */ 106 uint8_t psc; /* Fast/Standard mode prescale divider */ 107 uint8_t scll; /* Fast/Standard mode SCL low time */ 108 uint8_t sclh; /* Fast/Standard mode SCL high time */ 109 uint8_t hsscll; /* High Speed mode SCL low time */ 110 uint8_t hssclh; /* High Speed mode SCL high time */ 111 }; 112 113 #if defined(SOC_OMAP4) 114 /* 115 * OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)). 116 * The prescaler values for 100KHz and 400KHz modes come from the table in the 117 * OMAP4 TRM. The table doesn't list 1MHz; these values should give that speed. 118 */ 119 static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = { 120 { 100000, 23, 13, 15, 0, 0}, 121 { 400000, 9, 5, 7, 0, 0}, 122 { 1000000, 3, 5, 7, 0, 0}, 123 /* { 3200000, 1, 113, 115, 7, 10}, - HS mode */ 124 { 0 /* Table terminator */ } 125 }; 126 #endif 127 128 #if defined(SOC_TI_AM335X) 129 /* 130 * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5)) 131 * In all cases we prescale the clock to 24MHz as recommended in the manual. 132 */ 133 static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = { 134 { 100000, 1, 111, 117, 0, 0}, 135 { 400000, 1, 23, 25, 0, 0}, 136 { 1000000, 1, 5, 7, 0, 0}, 137 { 0 /* Table terminator */ } 138 }; 139 #endif 140 141 /** 142 * Locking macros used throughout the driver 143 */ 144 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 145 #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 146 #define TI_I2C_LOCK_INIT(_sc) \ 147 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 148 "ti_i2c", MTX_DEF) 149 #define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx) 150 #define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) 151 #define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED) 152 153 #ifdef DEBUG 154 #define ti_i2c_dbg(_sc, fmt, args...) \ 155 device_printf((_sc)->sc_dev, fmt, ##args) 156 #else 157 #define ti_i2c_dbg(_sc, fmt, args...) 158 #endif 159 160 /** 161 * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers 162 * @sc: I2C device context 163 * @off: the byte offset within the register bank to read from. 164 * 165 * 166 * LOCKING: 167 * No locking required 168 * 169 * RETURNS: 170 * 16-bit value read from the register. 171 */ 172 static inline uint16_t 173 ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off) 174 { 175 176 return (bus_read_2(sc->sc_mem_res, off)); 177 } 178 179 /** 180 * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers 181 * @sc: I2C device context 182 * @off: the byte offset within the register bank to read from. 183 * @val: the value to write into the register 184 * 185 * LOCKING: 186 * No locking required 187 * 188 * RETURNS: 189 * 16-bit value read from the register. 190 */ 191 static inline void 192 ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val) 193 { 194 195 bus_write_2(sc->sc_mem_res, off, val); 196 } 197 198 static int 199 ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status) 200 { 201 int amount, done, i; 202 203 done = 0; 204 amount = 0; 205 /* Check for the error conditions. */ 206 if (status & I2C_STAT_NACK) { 207 /* No ACK from slave. */ 208 ti_i2c_dbg(sc, "NACK\n"); 209 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK); 210 sc->sc_error = ENXIO; 211 } else if (status & I2C_STAT_AL) { 212 /* Arbitration lost. */ 213 ti_i2c_dbg(sc, "Arbitration lost\n"); 214 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL); 215 sc->sc_error = ENXIO; 216 } 217 218 /* Check if we have finished. */ 219 if (status & I2C_STAT_ARDY) { 220 /* Register access ready - transaction complete basically. */ 221 ti_i2c_dbg(sc, "ARDY transaction complete\n"); 222 if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) { 223 ti_i2c_write_2(sc, I2C_REG_CON, 224 sc->sc_con_reg | I2C_CON_STP); 225 } 226 ti_i2c_write_2(sc, I2C_REG_STATUS, 227 I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY | 228 I2C_STAT_XDR | I2C_STAT_XRDY); 229 return (1); 230 } 231 232 if (sc->sc_buffer->flags & IIC_M_RD) { 233 /* Read some data. */ 234 if (status & I2C_STAT_RDR) { 235 /* 236 * Receive draining interrupt - last data received. 237 * The set FIFO threshold wont be reached to trigger 238 * RRDY. 239 */ 240 ti_i2c_dbg(sc, "Receive draining interrupt\n"); 241 242 /* 243 * Drain the FIFO. Read the pending data in the FIFO. 244 */ 245 amount = sc->sc_buffer->len - sc->sc_buffer_pos; 246 } else if (status & I2C_STAT_RRDY) { 247 /* 248 * Receive data ready interrupt - FIFO has reached the 249 * set threshold. 250 */ 251 ti_i2c_dbg(sc, "Receive data ready interrupt\n"); 252 253 amount = min(sc->sc_fifo_trsh, 254 sc->sc_buffer->len - sc->sc_buffer_pos); 255 } 256 257 /* Read the bytes from the fifo. */ 258 for (i = 0; i < amount; i++) 259 sc->sc_buffer->buf[sc->sc_buffer_pos++] = 260 (uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff); 261 262 if (status & I2C_STAT_RDR) 263 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR); 264 if (status & I2C_STAT_RRDY) 265 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY); 266 267 } else { 268 /* Write some data. */ 269 if (status & I2C_STAT_XDR) { 270 /* 271 * Transmit draining interrupt - FIFO level is below 272 * the set threshold and the amount of data still to 273 * be transferred wont reach the set FIFO threshold. 274 */ 275 ti_i2c_dbg(sc, "Transmit draining interrupt\n"); 276 277 /* 278 * Drain the TX data. Write the pending data in the 279 * FIFO. 280 */ 281 amount = sc->sc_buffer->len - sc->sc_buffer_pos; 282 } else if (status & I2C_STAT_XRDY) { 283 /* 284 * Transmit data ready interrupt - the FIFO level 285 * is below the set threshold. 286 */ 287 ti_i2c_dbg(sc, "Transmit data ready interrupt\n"); 288 289 amount = min(sc->sc_fifo_trsh, 290 sc->sc_buffer->len - sc->sc_buffer_pos); 291 } 292 293 /* Write the bytes from the fifo. */ 294 for (i = 0; i < amount; i++) 295 ti_i2c_write_2(sc, I2C_REG_DATA, 296 sc->sc_buffer->buf[sc->sc_buffer_pos++]); 297 298 if (status & I2C_STAT_XDR) 299 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR); 300 if (status & I2C_STAT_XRDY) 301 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY); 302 } 303 304 return (done); 305 } 306 307 /** 308 * ti_i2c_intr - interrupt handler for the I2C module 309 * @dev: i2c device handle 310 * 311 * 312 * 313 * LOCKING: 314 * Called from timer context 315 * 316 * RETURNS: 317 * EH_HANDLED or EH_NOT_HANDLED 318 */ 319 static void 320 ti_i2c_intr(void *arg) 321 { 322 int done; 323 struct ti_i2c_softc *sc; 324 uint16_t events, status; 325 326 sc = (struct ti_i2c_softc *)arg; 327 328 TI_I2C_LOCK(sc); 329 330 status = ti_i2c_read_2(sc, I2C_REG_STATUS); 331 if (status == 0) { 332 TI_I2C_UNLOCK(sc); 333 return; 334 } 335 336 /* Save enabled interrupts. */ 337 events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET); 338 339 /* We only care about enabled interrupts. */ 340 status &= events; 341 342 done = 0; 343 344 if (sc->sc_buffer != NULL) 345 done = ti_i2c_transfer_intr(sc, status); 346 else { 347 ti_i2c_dbg(sc, "Transfer interrupt without buffer\n"); 348 sc->sc_error = EINVAL; 349 done = 1; 350 } 351 352 if (done) 353 /* Wakeup the process that started the transaction. */ 354 wakeup(sc); 355 356 TI_I2C_UNLOCK(sc); 357 } 358 359 /** 360 * ti_i2c_transfer - called to perform the transfer 361 * @dev: i2c device handle 362 * @msgs: the messages to send/receive 363 * @nmsgs: the number of messages in the msgs array 364 * 365 * 366 * LOCKING: 367 * Internally locked 368 * 369 * RETURNS: 370 * 0 on function succeeded 371 * EINVAL if invalid message is passed as an arg 372 */ 373 static int 374 ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 375 { 376 int err, i, repstart, timeout; 377 struct ti_i2c_softc *sc; 378 uint16_t reg; 379 380 sc = device_get_softc(dev); 381 TI_I2C_LOCK(sc); 382 383 /* If the controller is busy wait until it is available. */ 384 while (sc->sc_bus_inuse == 1) 385 mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0); 386 387 /* Now we have control over the I2C controller. */ 388 sc->sc_bus_inuse = 1; 389 390 err = 0; 391 repstart = 0; 392 for (i = 0; i < nmsgs; i++) { 393 394 sc->sc_buffer = &msgs[i]; 395 sc->sc_buffer_pos = 0; 396 sc->sc_error = 0; 397 398 /* Zero byte transfers aren't allowed. */ 399 if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL || 400 sc->sc_buffer->len == 0) { 401 err = EINVAL; 402 break; 403 } 404 405 /* Check if the i2c bus is free. */ 406 if (repstart == 0) { 407 /* 408 * On repeated start we send the START condition while 409 * the bus _is_ busy. 410 */ 411 timeout = 0; 412 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) { 413 if (timeout++ > 100) { 414 err = EBUSY; 415 goto out; 416 } 417 DELAY(1000); 418 } 419 timeout = 0; 420 } else 421 repstart = 0; 422 423 if (sc->sc_buffer->flags & IIC_M_NOSTOP) 424 repstart = 1; 425 426 /* Set the slave address. */ 427 ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1); 428 429 /* Write the data length. */ 430 ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len); 431 432 /* Clear the RX and the TX FIFO. */ 433 reg = ti_i2c_read_2(sc, I2C_REG_BUF); 434 reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR; 435 ti_i2c_write_2(sc, I2C_REG_BUF, reg); 436 437 reg = sc->sc_con_reg | I2C_CON_STT; 438 if (repstart == 0) 439 reg |= I2C_CON_STP; 440 if ((sc->sc_buffer->flags & IIC_M_RD) == 0) 441 reg |= I2C_CON_TRX; 442 ti_i2c_write_2(sc, I2C_REG_CON, reg); 443 444 /* Wait for an event. */ 445 err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", hz); 446 if (err == 0) 447 err = sc->sc_error; 448 449 if (err) 450 break; 451 } 452 453 out: 454 if (timeout == 0) { 455 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) { 456 if (timeout++ > 100) 457 break; 458 DELAY(1000); 459 } 460 } 461 /* Put the controller in master mode again. */ 462 if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0) 463 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 464 465 sc->sc_buffer = NULL; 466 sc->sc_bus_inuse = 0; 467 468 /* Wake up the processes that are waiting for the bus. */ 469 wakeup(sc); 470 471 TI_I2C_UNLOCK(sc); 472 473 return (err); 474 } 475 476 static int 477 ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed) 478 { 479 int timeout; 480 struct ti_i2c_clock_config *clkcfg; 481 u_int busfreq; 482 uint16_t fifo_trsh, reg, scll, sclh; 483 484 switch (ti_chip()) { 485 #ifdef SOC_OMAP4 486 case CHIP_OMAP_4: 487 clkcfg = ti_omap4_i2c_clock_configs; 488 break; 489 #endif 490 #ifdef SOC_TI_AM335X 491 case CHIP_AM335X: 492 clkcfg = ti_am335x_i2c_clock_configs; 493 break; 494 #endif 495 default: 496 panic("Unknown Ti SoC, unable to reset the i2c"); 497 } 498 499 /* 500 * If we haven't attached the bus yet, just init at the default slow 501 * speed. This lets us get the hardware initialized enough to attach 502 * the bus which is where the real speed configuration is handled. After 503 * the bus is attached, get the configured speed from it. Search the 504 * configuration table for the best speed we can do that doesn't exceed 505 * the requested speed. 506 */ 507 if (sc->sc_iicbus == NULL) 508 busfreq = 100000; 509 else 510 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); 511 for (;;) { 512 if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq) 513 break; 514 clkcfg++; 515 } 516 517 /* 518 * 23.1.4.3 - HS I2C Software Reset 519 * From OMAP4 TRM at page 4068. 520 * 521 * 1. Ensure that the module is disabled. 522 */ 523 sc->sc_con_reg = 0; 524 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 525 526 /* 2. Issue a softreset to the controller. */ 527 bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST); 528 529 /* 530 * 3. Enable the module. 531 * The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module 532 * is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1. 533 */ 534 ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN); 535 536 /* 4. Wait for the software reset to complete. */ 537 timeout = 0; 538 while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) { 539 if (timeout++ > 100) 540 return (EBUSY); 541 DELAY(100); 542 } 543 544 /* 545 * Disable the I2C controller once again, now that the reset has 546 * finished. 547 */ 548 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 549 550 /* 551 * The following sequence is taken from the OMAP4 TRM at page 4077. 552 * 553 * 1. Enable the functional and interface clocks (see Section 554 * 23.1.5.1.1.1.1). Done at ti_i2c_activate(). 555 * 556 * 2. Program the prescaler to obtain an approximately 12MHz internal 557 * sampling clock (I2Ci_INTERNAL_CLK) by programming the 558 * corresponding value in the I2Ci.I2C_PSC[3:0] PSC field. 559 * This value depends on the frequency of the functional clock 560 * (I2Ci_FCLK). Because this frequency is 96MHz, the 561 * I2Ci.I2C_PSC[7:0] PSC field value is 0x7. 562 */ 563 ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc); 564 565 /* 566 * 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH 567 * bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps. 568 * These values depend on the internal sampling clock frequency 569 * (see Table 23-8). 570 */ 571 scll = clkcfg->scll & I2C_SCLL_MASK; 572 sclh = clkcfg->sclh & I2C_SCLH_MASK; 573 574 /* 575 * 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and 576 * I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of 577 * 400K bps or 3.4M bps (for the second phase of HS mode). These 578 * values depend on the internal sampling clock frequency (see 579 * Table 23-8). 580 * 581 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line 582 * capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional 583 * Multiplexing and Configuration). 584 */ 585 switch (ti_chip()) { 586 #ifdef SOC_OMAP4 587 case CHIP_OMAP_4: 588 if ((clkcfg->hsscll + clkcfg->hssclh) > 0) { 589 scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT; 590 sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT; 591 sc->sc_con_reg |= I2C_CON_OPMODE_HS; 592 } 593 break; 594 #endif 595 } 596 597 /* Write the selected bit rate. */ 598 ti_i2c_write_2(sc, I2C_REG_SCLL, scll); 599 ti_i2c_write_2(sc, I2C_REG_SCLH, sclh); 600 601 /* 602 * 6. Configure the Own Address of the I2C controller by storing it in 603 * the I2Ci.I2C_OA0 register. Up to four Own Addresses can be 604 * programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3) 605 * for each I2C controller. 606 * 607 * Note: For a 10-bit address, set the corresponding expand Own Address 608 * bit in the I2Ci.I2C_CON register. 609 * 610 * Driver currently always in single master mode so ignore this step. 611 */ 612 613 /* 614 * 7. Set the TX threshold (in transmitter mode) and the RX threshold 615 * (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to 616 * (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX 617 * threshold - 1), where the TX and RX thresholds are greater than 618 * or equal to 1. 619 * 620 * The threshold is set to 5 for now. 621 */ 622 fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK; 623 reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT); 624 ti_i2c_write_2(sc, I2C_REG_BUF, reg); 625 626 /* 627 * 8. Take the I2C controller out of reset by setting the 628 * I2Ci.I2C_CON[15] I2C_EN bit to 1. 629 * 630 * 23.1.5.1.1.1.2 - Initialize the I2C Controller 631 * 632 * To initialize the I2C controller, perform the following steps: 633 * 634 * 1. Configure the I2Ci.I2C_CON register: 635 * . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit 636 * (0: slave, 1: master). 637 * . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX 638 * bit (0: receiver, 1: transmitter). 639 */ 640 641 /* Enable the I2C controller in master mode. */ 642 sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST; 643 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 644 645 /* 646 * 2. If using an interrupt to transmit/receive data, set the 647 * corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4] 648 * XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY 649 * bit for the receive interrupt). 650 */ 651 652 /* Set the interrupts we want to be notified. */ 653 reg = I2C_IE_XDR | /* Transmit draining interrupt. */ 654 I2C_IE_XRDY | /* Transmit Data Ready interrupt. */ 655 I2C_IE_RDR | /* Receive draining interrupt. */ 656 I2C_IE_RRDY | /* Receive Data Ready interrupt. */ 657 I2C_IE_ARDY | /* Register Access Ready interrupt. */ 658 I2C_IE_NACK | /* No Acknowledgment interrupt. */ 659 I2C_IE_AL; /* Arbitration lost interrupt. */ 660 661 /* Enable the interrupts. */ 662 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg); 663 664 /* 665 * 3. If using DMA to receive/transmit data, set to 1 the corresponding 666 * bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN 667 * bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit 668 * for the transmit DMA channel). 669 * 670 * Not using DMA for now, so ignore this. 671 */ 672 673 return (0); 674 } 675 676 static int 677 ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 678 { 679 struct ti_i2c_softc *sc; 680 int err; 681 682 sc = device_get_softc(dev); 683 TI_I2C_LOCK(sc); 684 err = ti_i2c_reset(sc, speed); 685 TI_I2C_UNLOCK(sc); 686 if (err) 687 return (err); 688 689 return (IIC_ENOADDR); 690 } 691 692 static int 693 ti_i2c_activate(device_t dev) 694 { 695 clk_ident_t clk; 696 int err; 697 struct ti_i2c_softc *sc; 698 699 sc = (struct ti_i2c_softc*)device_get_softc(dev); 700 701 /* 702 * 1. Enable the functional and interface clocks (see Section 703 * 23.1.5.1.1.1.1). 704 */ 705 clk = I2C0_CLK + sc->device_id; 706 err = ti_prcm_clk_enable(clk); 707 if (err) 708 return (err); 709 710 return (ti_i2c_reset(sc, IIC_UNKNOWN)); 711 } 712 713 /** 714 * ti_i2c_deactivate - deactivates the controller and releases resources 715 * @dev: i2c device handle 716 * 717 * 718 * 719 * LOCKING: 720 * Assumed called in an atomic context. 721 * 722 * RETURNS: 723 * nothing 724 */ 725 static void 726 ti_i2c_deactivate(device_t dev) 727 { 728 struct ti_i2c_softc *sc = device_get_softc(dev); 729 clk_ident_t clk; 730 731 /* Disable the controller - cancel all transactions. */ 732 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff); 733 ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff); 734 ti_i2c_write_2(sc, I2C_REG_CON, 0); 735 736 /* Release the interrupt handler. */ 737 if (sc->sc_irq_h != NULL) { 738 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h); 739 sc->sc_irq_h = NULL; 740 } 741 742 bus_generic_detach(sc->sc_dev); 743 744 /* Unmap the I2C controller registers. */ 745 if (sc->sc_mem_res != NULL) { 746 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 747 sc->sc_mem_res = NULL; 748 } 749 750 /* Release the IRQ resource. */ 751 if (sc->sc_irq_res != NULL) { 752 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 753 sc->sc_irq_res = NULL; 754 } 755 756 /* Finally disable the functional and interface clocks. */ 757 clk = I2C0_CLK + sc->device_id; 758 ti_prcm_clk_disable(clk); 759 } 760 761 static int 762 ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS) 763 { 764 device_t dev; 765 int clk, psc, sclh, scll; 766 struct ti_i2c_softc *sc; 767 768 dev = (device_t)arg1; 769 sc = device_get_softc(dev); 770 771 TI_I2C_LOCK(sc); 772 /* Get the system prescaler value. */ 773 psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1; 774 775 /* Get the bitrate. */ 776 scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK; 777 sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK; 778 779 clk = I2C_CLK / psc / (scll + 7 + sclh + 5); 780 TI_I2C_UNLOCK(sc); 781 782 return (sysctl_handle_int(oidp, &clk, 0, req)); 783 } 784 785 static int 786 ti_i2c_probe(device_t dev) 787 { 788 789 if (!ofw_bus_status_okay(dev)) 790 return (ENXIO); 791 if (!ofw_bus_is_compatible(dev, "ti,i2c")) 792 return (ENXIO); 793 device_set_desc(dev, "TI I2C Controller"); 794 795 return (0); 796 } 797 798 static int 799 ti_i2c_attach(device_t dev) 800 { 801 int err, rid; 802 phandle_t node; 803 struct ti_i2c_softc *sc; 804 struct sysctl_ctx_list *ctx; 805 struct sysctl_oid_list *tree; 806 uint16_t fifosz; 807 808 sc = device_get_softc(dev); 809 sc->sc_dev = dev; 810 811 /* Get the i2c device id from FDT. */ 812 node = ofw_bus_get_node(dev); 813 if ((OF_getencprop(node, "i2c-device-id", &sc->device_id, 814 sizeof(sc->device_id))) <= 0) { 815 device_printf(dev, "missing i2c-device-id attribute in FDT\n"); 816 return (ENXIO); 817 } 818 819 /* Get the memory resource for the register mapping. */ 820 rid = 0; 821 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 822 RF_ACTIVE); 823 if (sc->sc_mem_res == NULL) { 824 device_printf(dev, "Cannot map registers.\n"); 825 return (ENXIO); 826 } 827 828 /* Allocate our IRQ resource. */ 829 rid = 0; 830 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 831 RF_ACTIVE | RF_SHAREABLE); 832 if (sc->sc_irq_res == NULL) { 833 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 834 device_printf(dev, "Cannot allocate interrupt.\n"); 835 return (ENXIO); 836 } 837 838 TI_I2C_LOCK_INIT(sc); 839 840 /* First of all, we _must_ activate the H/W. */ 841 err = ti_i2c_activate(dev); 842 if (err) { 843 device_printf(dev, "ti_i2c_activate failed\n"); 844 goto out; 845 } 846 847 /* Read the version number of the I2C module */ 848 sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff; 849 850 /* Get the fifo size. */ 851 fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT); 852 fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT; 853 fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK; 854 855 device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n", 856 sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz); 857 858 /* Set the FIFO threshold to 5 for now. */ 859 sc->sc_fifo_trsh = 5; 860 861 ctx = device_get_sysctl_ctx(dev); 862 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 863 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock", 864 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, dev, 0, 865 ti_i2c_sysctl_clk, "IU", "I2C bus clock"); 866 867 /* Activate the interrupt. */ 868 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 869 NULL, ti_i2c_intr, sc, &sc->sc_irq_h); 870 if (err) 871 goto out; 872 873 /* Attach the iicbus. */ 874 if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { 875 device_printf(dev, "could not allocate iicbus instance\n"); 876 err = ENXIO; 877 goto out; 878 } 879 880 /* Probe and attach the iicbus */ 881 bus_generic_attach(dev); 882 883 out: 884 if (err) { 885 ti_i2c_deactivate(dev); 886 TI_I2C_LOCK_DESTROY(sc); 887 } 888 889 return (err); 890 } 891 892 static int 893 ti_i2c_detach(device_t dev) 894 { 895 struct ti_i2c_softc *sc; 896 int rv; 897 898 sc = device_get_softc(dev); 899 ti_i2c_deactivate(dev); 900 TI_I2C_LOCK_DESTROY(sc); 901 if (sc->sc_iicbus && 902 (rv = device_delete_child(dev, sc->sc_iicbus)) != 0) 903 return (rv); 904 905 return (0); 906 } 907 908 static phandle_t 909 ti_i2c_get_node(device_t bus, device_t dev) 910 { 911 912 /* Share controller node with iibus device. */ 913 return (ofw_bus_get_node(bus)); 914 } 915 916 static device_method_t ti_i2c_methods[] = { 917 /* Device interface */ 918 DEVMETHOD(device_probe, ti_i2c_probe), 919 DEVMETHOD(device_attach, ti_i2c_attach), 920 DEVMETHOD(device_detach, ti_i2c_detach), 921 922 /* OFW methods */ 923 DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node), 924 925 /* iicbus interface */ 926 DEVMETHOD(iicbus_callback, iicbus_null_callback), 927 DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset), 928 DEVMETHOD(iicbus_transfer, ti_i2c_transfer), 929 930 DEVMETHOD_END 931 }; 932 933 static driver_t ti_i2c_driver = { 934 "iichb", 935 ti_i2c_methods, 936 sizeof(struct ti_i2c_softc), 937 }; 938 939 static devclass_t ti_i2c_devclass; 940 941 DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, ti_i2c_devclass, 0, 0); 942 DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, iicbus_devclass, 0, 0); 943 944 MODULE_DEPEND(ti_iic, ti_prcm, 1, 1, 1); 945 MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1); 946