1 /*- 2 * Copyright (c) 2011 3 * Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /** 29 * Driver for the I2C module on the TI SoC. 30 * 31 * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c). 32 * 33 * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses, 34 * 32 bit data access is not allowed and can corrupt register content. 35 * 36 * This driver currently doesn't use DMA for the transfer, although I hope to 37 * incorporate that sometime in the future. The idea being that for transaction 38 * larger than a certain size the DMA engine is used, for anything less the 39 * normal interrupt/fifo driven option is used. 40 * 41 * 42 * WARNING: This driver uses mtx_sleep and interrupts to perform transactions, 43 * which means you can't do a transaction during startup before the interrupts 44 * have been enabled. Hint - the freebsd function config_intrhook_establish(). 45 */ 46 47 #include <sys/cdefs.h> 48 __FBSDID("$FreeBSD$"); 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/bus.h> 53 #include <sys/conf.h> 54 #include <sys/kernel.h> 55 #include <sys/lock.h> 56 #include <sys/mbuf.h> 57 #include <sys/malloc.h> 58 #include <sys/module.h> 59 #include <sys/mutex.h> 60 #include <sys/rman.h> 61 #include <machine/bus.h> 62 63 #include <dev/fdt/fdt_common.h> 64 #include <dev/ofw/openfirm.h> 65 #include <dev/ofw/ofw_bus.h> 66 #include <dev/ofw/ofw_bus_subr.h> 67 68 #include <arm/ti/ti_cpuid.h> 69 #include <arm/ti/ti_prcm.h> 70 #include <arm/ti/ti_i2c.h> 71 72 #include <dev/iicbus/iiconf.h> 73 #include <dev/iicbus/iicbus.h> 74 75 #include "iicbus_if.h" 76 77 /** 78 * I2C device driver context, a pointer to this is stored in the device 79 * driver structure. 80 */ 81 struct ti_i2c_softc 82 { 83 device_t sc_dev; 84 uint32_t device_id; 85 struct resource* sc_irq_res; 86 struct resource* sc_mem_res; 87 device_t sc_iicbus; 88 89 void* sc_irq_h; 90 91 struct mtx sc_mtx; 92 93 volatile uint16_t sc_stat_flags; /* contains the status flags last IRQ */ 94 95 uint16_t sc_i2c_addr; 96 uint16_t sc_rev; 97 }; 98 99 struct ti_i2c_clock_config 100 { 101 int speed; 102 int bitrate; 103 uint8_t psc; /* Fast/Standard mode prescale divider */ 104 uint8_t scll; /* Fast/Standard mode SCL low time */ 105 uint8_t sclh; /* Fast/Standard mode SCL high time */ 106 uint8_t hsscll; /* High Speed mode SCL low time */ 107 uint8_t hssclh; /* High Speed mode SCL high time */ 108 }; 109 110 #if defined(SOC_OMAP4) 111 static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = { 112 { IIC_SLOW, 100000, 23, 13, 15, 0, 0}, 113 { IIC_FAST, 400000, 9, 5, 7, 0, 0}, 114 { IIC_FASTEST, 3310000, 1, 113, 115, 7, 10}, 115 { -1, 0 } 116 }; 117 #endif 118 119 #if defined(SOC_TI_AM335X) 120 static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = { 121 { IIC_SLOW, 100000, 3, 53, 55, 0, 0}, 122 { IIC_FAST, 400000, 3, 8, 10, 0, 0}, 123 { IIC_FASTEST, 400000, 3, 8, 10, 0, 0}, /* This might be higher */ 124 { -1, 0 } 125 }; 126 #endif 127 128 129 #define TI_I2C_REV1 0x003C /* OMAP3 */ 130 #define TI_I2C_REV2 0x000A /* OMAP4 */ 131 132 /** 133 * Locking macros used throughout the driver 134 */ 135 #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 136 #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 137 #define TI_I2C_LOCK_INIT(_sc) \ 138 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 139 "ti_i2c", MTX_DEF) 140 #define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); 141 #define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); 142 #define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); 143 144 #ifdef DEBUG 145 #define ti_i2c_dbg(_sc, fmt, args...) \ 146 device_printf((_sc)->sc_dev, fmt, ##args) 147 #else 148 #define ti_i2c_dbg(_sc, fmt, args...) 149 #endif 150 151 static devclass_t ti_i2c_devclass; 152 153 /* bus entry points */ 154 155 static int ti_i2c_probe(device_t dev); 156 static int ti_i2c_attach(device_t dev); 157 static int ti_i2c_detach(device_t dev); 158 static void ti_i2c_intr(void *); 159 160 /* OFW routine */ 161 static phandle_t ti_i2c_get_node(device_t bus, device_t dev); 162 163 /* helper routines */ 164 static int ti_i2c_activate(device_t dev); 165 static void ti_i2c_deactivate(device_t dev); 166 167 /** 168 * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers 169 * @sc: I2C device context 170 * @off: the byte offset within the register bank to read from. 171 * 172 * 173 * LOCKING: 174 * No locking required 175 * 176 * RETURNS: 177 * 16-bit value read from the register. 178 */ 179 static inline uint16_t 180 ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off) 181 { 182 return bus_read_2(sc->sc_mem_res, off); 183 } 184 185 /** 186 * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers 187 * @sc: I2C device context 188 * @off: the byte offset within the register bank to read from. 189 * @val: the value to write into the register 190 * 191 * LOCKING: 192 * No locking required 193 * 194 * RETURNS: 195 * 16-bit value read from the register. 196 */ 197 static inline void 198 ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val) 199 { 200 bus_write_2(sc->sc_mem_res, off, val); 201 } 202 203 /** 204 * ti_i2c_read_reg - reads a 16-bit value from one of the I2C registers 205 * take into account revision-dependent register offset 206 * @sc: I2C device context 207 * @off: the byte offset within the register bank to read from. 208 * 209 * 210 * LOCKING: 211 * No locking required 212 * 213 * RETURNS: 214 * 16-bit value read from the register. 215 */ 216 static inline uint16_t 217 ti_i2c_read_reg(struct ti_i2c_softc *sc, bus_size_t off) 218 { 219 /* XXXOMAP3: FIXME add registers mapping here */ 220 return bus_read_2(sc->sc_mem_res, off); 221 } 222 223 /** 224 * ti_i2c_write_reg - writes a 16-bit value to one of the I2C registers 225 * take into account revision-dependent register offset 226 * @sc: I2C device context 227 * @off: the byte offset within the register bank to read from. 228 * @val: the value to write into the register 229 * 230 * LOCKING: 231 * No locking required 232 * 233 * RETURNS: 234 * 16-bit value read from the register. 235 */ 236 static inline void 237 ti_i2c_write_reg(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val) 238 { 239 /* XXXOMAP3: FIXME add registers mapping here */ 240 bus_write_2(sc->sc_mem_res, off, val); 241 } 242 243 /** 244 * ti_i2c_set_intr_enable - writes the interrupt enable register 245 * @sc: I2C device context 246 * @ie: bitmask of the interrupts to enable 247 * 248 * This function is needed as writing the I2C_IE register on the OMAP4 devices 249 * doesn't seem to actually enable the interrupt, rather you have to write 250 * through the I2C_IRQENABLE_CLR and I2C_IRQENABLE_SET registers. 251 * 252 * LOCKING: 253 * No locking required 254 * 255 * RETURNS: 256 * Nothing. 257 */ 258 static inline void 259 ti_i2c_set_intr_enable(struct ti_i2c_softc *sc, uint16_t ie) 260 { 261 /* XXXOMAP3: FIXME */ 262 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff); 263 if (ie) 264 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, ie); 265 } 266 267 /** 268 * ti_i2c_reset - attach function for the driver 269 * @dev: i2c device handle 270 * 271 * 272 * 273 * LOCKING: 274 * Called from timer context 275 * 276 * RETURNS: 277 * EH_HANDLED or EH_NOT_HANDLED 278 */ 279 static int 280 ti_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 281 { 282 struct ti_i2c_softc *sc = device_get_softc(dev); 283 struct ti_i2c_clock_config *clkcfg; 284 uint16_t con_reg; 285 286 switch (ti_chip()) { 287 #ifdef SOC_OMAP4 288 case CHIP_OMAP_4: 289 clkcfg = ti_omap4_i2c_clock_configs; 290 break; 291 #endif 292 #ifdef SOC_TI_AM335X 293 case CHIP_AM335X: 294 clkcfg = ti_am335x_i2c_clock_configs; 295 break; 296 #endif 297 default: 298 panic("Unknown Ti SoC, unable to reset the i2c"); 299 } 300 while (clkcfg->speed != -1) { 301 if (clkcfg->speed == speed) 302 break; 303 /* take slow if speed is unknown */ 304 if ((speed == IIC_UNKNOWN) && (clkcfg->speed == IIC_SLOW)) 305 break; 306 clkcfg++; 307 } 308 if (clkcfg->speed == -1) 309 return (EINVAL); 310 311 TI_I2C_LOCK(sc); 312 313 if (oldaddr) 314 *oldaddr = sc->sc_i2c_addr; 315 sc->sc_i2c_addr = addr; 316 317 /* First disable the controller while changing the clocks */ 318 con_reg = ti_i2c_read_reg(sc, I2C_REG_CON); 319 ti_i2c_write_reg(sc, I2C_REG_CON, 0x0000); 320 321 /* Program the prescaler */ 322 ti_i2c_write_reg(sc, I2C_REG_PSC, clkcfg->psc); 323 324 /* Set the bitrate */ 325 ti_i2c_write_reg(sc, I2C_REG_SCLL, clkcfg->scll | (clkcfg->hsscll<<8)); 326 ti_i2c_write_reg(sc, I2C_REG_SCLH, clkcfg->sclh | (clkcfg->hssclh<<8)); 327 328 /* Set the remote slave address */ 329 ti_i2c_write_reg(sc, I2C_REG_SA, addr); 330 331 /* Check if we are dealing with high speed mode */ 332 if ((clkcfg->hsscll + clkcfg->hssclh) > 0) 333 con_reg = I2C_CON_OPMODE_HS; 334 else 335 con_reg = I2C_CON_OPMODE_STD; 336 337 /* Enable the I2C module again */ 338 ti_i2c_write_reg(sc, I2C_REG_CON, I2C_CON_I2C_EN | con_reg); 339 340 TI_I2C_UNLOCK(sc); 341 342 return 0; 343 } 344 345 /** 346 * ti_i2c_intr - interrupt handler for the I2C module 347 * @dev: i2c device handle 348 * 349 * 350 * 351 * LOCKING: 352 * Called from timer context 353 * 354 * RETURNS: 355 * EH_HANDLED or EH_NOT_HANDLED 356 */ 357 static void 358 ti_i2c_intr(void *arg) 359 { 360 struct ti_i2c_softc *sc = (struct ti_i2c_softc*) arg; 361 uint16_t status; 362 363 status = ti_i2c_read_reg(sc, I2C_REG_STAT); 364 if (status == 0) 365 return; 366 367 TI_I2C_LOCK(sc); 368 369 /* save the flags */ 370 sc->sc_stat_flags |= status; 371 372 /* clear the status flags */ 373 ti_i2c_write_reg(sc, I2C_REG_STAT, status); 374 375 /* wakeup the process the started the transaction */ 376 wakeup(sc); 377 378 TI_I2C_UNLOCK(sc); 379 380 return; 381 } 382 383 /** 384 * ti_i2c_wait - waits for the specific event to occur 385 * @sc: i2c driver context 386 * @flags: the event(s) to wait on, this is a bitmask of the I2C_STAT_??? flags 387 * @statp: if not null will contain the status flags upon return 388 * @timo: the number of ticks to wait 389 * 390 * 391 * 392 * LOCKING: 393 * The driver context must be locked before calling this function. Internally 394 * the function sleeps, releasing the lock as it does so, however the lock is 395 * always retaken before this function returns. 396 * 397 * RETURNS: 398 * 0 if the event(s) were tripped within timeout period 399 * EBUSY if timedout waiting for the events 400 * ENXIO if a NACK event was received 401 */ 402 static int 403 ti_i2c_wait(struct ti_i2c_softc *sc, uint16_t flags, uint16_t *statp, int timo) 404 { 405 int waittime = timo; 406 int start_ticks = ticks; 407 int rc; 408 409 TI_I2C_ASSERT_LOCKED(sc); 410 411 /* check if the condition has already occured, the interrupt routine will 412 * clear the status flags. 413 */ 414 if ((sc->sc_stat_flags & flags) == 0) { 415 416 /* condition(s) haven't occured so sleep on the IRQ */ 417 while (waittime > 0) { 418 419 rc = mtx_sleep(sc, &sc->sc_mtx, 0, "I2Cwait", waittime); 420 if (rc == EWOULDBLOCK) { 421 /* timed-out, simply break out of the loop */ 422 break; 423 } else { 424 /* IRQ has been tripped, but need to sanity check we have the 425 * right events in the status flag. 426 */ 427 if ((sc->sc_stat_flags & flags) != 0) 428 break; 429 430 /* event hasn't been tripped so wait some more */ 431 waittime -= (ticks - start_ticks); 432 start_ticks = ticks; 433 } 434 } 435 } 436 437 /* copy the actual status bits */ 438 if (statp != NULL) 439 *statp = sc->sc_stat_flags; 440 441 /* return the status found */ 442 if ((sc->sc_stat_flags & flags) != 0) 443 rc = 0; 444 else 445 rc = EBUSY; 446 447 /* clear the flags set by the interrupt handler */ 448 sc->sc_stat_flags = 0; 449 450 return (rc); 451 } 452 453 /** 454 * ti_i2c_wait_for_free_bus - waits for the bus to become free 455 * @sc: i2c driver context 456 * @timo: the time to wait for the bus to become free 457 * 458 * 459 * 460 * LOCKING: 461 * The driver context must be locked before calling this function. Internally 462 * the function sleeps, releasing the lock as it does so, however the lock is 463 * always taken before this function returns. 464 * 465 * RETURNS: 466 * 0 if the event(s) were tripped within timeout period 467 * EBUSY if timedout waiting for the events 468 * ENXIO if a NACK event was received 469 */ 470 static int 471 ti_i2c_wait_for_free_bus(struct ti_i2c_softc *sc, int timo) 472 { 473 /* check if the bus is free, BB bit = 0 */ 474 if ((ti_i2c_read_reg(sc, I2C_REG_STAT) & I2C_STAT_BB) == 0) 475 return 0; 476 477 /* enable bus free interrupts */ 478 ti_i2c_set_intr_enable(sc, I2C_IE_BF); 479 480 /* wait for the bus free interrupt to be tripped */ 481 return ti_i2c_wait(sc, I2C_STAT_BF, NULL, timo); 482 } 483 484 /** 485 * ti_i2c_read_bytes - attempts to perform a read operation 486 * @sc: i2c driver context 487 * @buf: buffer to hold the received bytes 488 * @len: the number of bytes to read 489 * 490 * This function assumes the slave address is already set 491 * 492 * LOCKING: 493 * The context lock should be held before calling this function 494 * 495 * RETURNS: 496 * 0 on function succeeded 497 * EINVAL if invalid message is passed as an arg 498 */ 499 static int 500 ti_i2c_read_bytes(struct ti_i2c_softc *sc, uint8_t *buf, uint16_t len) 501 { 502 int timo = (hz / 4); 503 int err = 0; 504 uint16_t con_reg; 505 uint16_t events; 506 uint16_t status; 507 uint32_t amount = 0; 508 uint32_t sofar = 0; 509 uint32_t i; 510 511 /* wait for the bus to become free */ 512 err = ti_i2c_wait_for_free_bus(sc, timo); 513 if (err != 0) { 514 device_printf(sc->sc_dev, "bus never freed\n"); 515 return (err); 516 } 517 518 /* set the events to wait for */ 519 events = I2C_IE_RDR | /* Receive draining interrupt */ 520 I2C_IE_RRDY | /* Receive Data Ready interrupt */ 521 I2C_IE_ARDY | /* Register Access Ready interrupt */ 522 I2C_IE_NACK | /* No Acknowledgment interrupt */ 523 I2C_IE_AL; 524 525 /* enable interrupts for the events we want */ 526 ti_i2c_set_intr_enable(sc, events); 527 528 /* write the number of bytes to read */ 529 ti_i2c_write_reg(sc, I2C_REG_CNT, len); 530 531 /* clear the write bit and initiate the read transaction. Setting the STT 532 * (start) bit initiates the transfer. 533 */ 534 con_reg = ti_i2c_read_reg(sc, I2C_REG_CON); 535 con_reg &= ~I2C_CON_TRX; 536 con_reg |= I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; 537 ti_i2c_write_reg(sc, I2C_REG_CON, con_reg); 538 539 /* reading loop */ 540 while (1) { 541 542 /* wait for an event */ 543 err = ti_i2c_wait(sc, events, &status, timo); 544 if (err != 0) { 545 break; 546 } 547 548 /* check for the error conditions */ 549 if (status & I2C_STAT_NACK) { 550 /* no ACK from slave */ 551 ti_i2c_dbg(sc, "NACK\n"); 552 err = ENXIO; 553 break; 554 } 555 if (status & I2C_STAT_AL) { 556 /* arbitration lost */ 557 ti_i2c_dbg(sc, "Arbitration lost\n"); 558 err = ENXIO; 559 break; 560 } 561 562 /* check if we have finished */ 563 if (status & I2C_STAT_ARDY) { 564 /* register access ready - transaction complete basically */ 565 ti_i2c_dbg(sc, "ARDY transaction complete\n"); 566 err = 0; 567 break; 568 } 569 570 /* read some data */ 571 if (status & I2C_STAT_RDR) { 572 /* Receive draining interrupt - last data received */ 573 ti_i2c_dbg(sc, "Receive draining interrupt\n"); 574 575 /* get the number of bytes in the FIFO */ 576 amount = ti_i2c_read_reg(sc, I2C_REG_BUFSTAT); 577 amount >>= 8; 578 amount &= 0x3f; 579 } 580 else if (status & I2C_STAT_RRDY) { 581 /* Receive data ready interrupt - enough data received */ 582 ti_i2c_dbg(sc, "Receive data ready interrupt\n"); 583 584 /* get the number of bytes in the FIFO */ 585 amount = ti_i2c_read_reg(sc, I2C_REG_BUF); 586 amount >>= 8; 587 amount &= 0x3f; 588 amount += 1; 589 } 590 591 /* sanity check we haven't overwritten the array */ 592 if ((sofar + amount) > len) { 593 ti_i2c_dbg(sc, "to many bytes to read\n"); 594 amount = (len - sofar); 595 } 596 597 /* read the bytes from the fifo */ 598 for (i = 0; i < amount; i++) { 599 buf[sofar++] = (uint8_t)(ti_i2c_read_reg(sc, I2C_REG_DATA) & 0xff); 600 } 601 602 /* attempt to clear the receive ready bits */ 603 ti_i2c_write_reg(sc, I2C_REG_STAT, I2C_STAT_RDR | I2C_STAT_RRDY); 604 } 605 606 /* reset the registers regardless if there was an error or not */ 607 ti_i2c_set_intr_enable(sc, 0x0000); 608 ti_i2c_write_reg(sc, I2C_REG_CON, I2C_CON_I2C_EN | I2C_CON_MST | I2C_CON_STP); 609 610 return (err); 611 } 612 613 /** 614 * ti_i2c_write_bytes - attempts to perform a read operation 615 * @sc: i2c driver context 616 * @buf: buffer containing the bytes to write 617 * @len: the number of bytes to write 618 * 619 * This function assumes the slave address is already set 620 * 621 * LOCKING: 622 * The context lock should be held before calling this function 623 * 624 * RETURNS: 625 * 0 on function succeeded 626 * EINVAL if invalid message is passed as an arg 627 */ 628 static int 629 ti_i2c_write_bytes(struct ti_i2c_softc *sc, const uint8_t *buf, uint16_t len) 630 { 631 int timo = (hz / 4); 632 int err = 0; 633 uint16_t con_reg; 634 uint16_t events; 635 uint16_t status; 636 uint32_t amount = 0; 637 uint32_t sofar = 0; 638 uint32_t i; 639 640 /* wait for the bus to become free */ 641 err = ti_i2c_wait_for_free_bus(sc, timo); 642 if (err != 0) 643 return (err); 644 645 /* set the events to wait for */ 646 events = I2C_IE_XDR | /* Transmit draining interrupt */ 647 I2C_IE_XRDY | /* Transmit Data Ready interrupt */ 648 I2C_IE_ARDY | /* Register Access Ready interrupt */ 649 I2C_IE_NACK | /* No Acknowledgment interrupt */ 650 I2C_IE_AL; 651 652 /* enable interrupts for the events we want*/ 653 ti_i2c_set_intr_enable(sc, events); 654 655 /* write the number of bytes to write */ 656 ti_i2c_write_reg(sc, I2C_REG_CNT, len); 657 658 /* set the write bit and initiate the write transaction. Setting the STT 659 * (start) bit initiates the transfer. 660 */ 661 con_reg = ti_i2c_read_reg(sc, I2C_REG_CON); 662 con_reg |= I2C_CON_TRX | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; 663 ti_i2c_write_reg(sc, I2C_REG_CON, con_reg); 664 665 /* writing loop */ 666 while (1) { 667 668 /* wait for an event */ 669 err = ti_i2c_wait(sc, events, &status, timo); 670 if (err != 0) { 671 break; 672 } 673 674 /* check for the error conditions */ 675 if (status & I2C_STAT_NACK) { 676 /* no ACK from slave */ 677 ti_i2c_dbg(sc, "NACK\n"); 678 err = ENXIO; 679 break; 680 } 681 if (status & I2C_STAT_AL) { 682 /* arbitration lost */ 683 ti_i2c_dbg(sc, "Arbitration lost\n"); 684 err = ENXIO; 685 break; 686 } 687 688 /* check if we have finished */ 689 if (status & I2C_STAT_ARDY) { 690 /* register access ready - transaction complete basically */ 691 ti_i2c_dbg(sc, "ARDY transaction complete\n"); 692 err = 0; 693 break; 694 } 695 696 /* read some data */ 697 if (status & I2C_STAT_XDR) { 698 /* Receive draining interrupt - last data received */ 699 ti_i2c_dbg(sc, "Transmit draining interrupt\n"); 700 701 /* get the number of bytes in the FIFO */ 702 amount = ti_i2c_read_reg(sc, I2C_REG_BUFSTAT); 703 amount &= 0x3f; 704 } 705 else if (status & I2C_STAT_XRDY) { 706 /* Receive data ready interrupt - enough data received */ 707 ti_i2c_dbg(sc, "Transmit data ready interrupt\n"); 708 709 /* get the number of bytes in the FIFO */ 710 amount = ti_i2c_read_reg(sc, I2C_REG_BUF); 711 amount &= 0x3f; 712 amount += 1; 713 } 714 715 /* sanity check we haven't overwritten the array */ 716 if ((sofar + amount) > len) { 717 ti_i2c_dbg(sc, "to many bytes to write\n"); 718 amount = (len - sofar); 719 } 720 721 /* write the bytes from the fifo */ 722 for (i = 0; i < amount; i++) { 723 ti_i2c_write_reg(sc, I2C_REG_DATA, buf[sofar++]); 724 } 725 726 /* attempt to clear the transmit ready bits */ 727 ti_i2c_write_reg(sc, I2C_REG_STAT, I2C_STAT_XDR | I2C_STAT_XRDY); 728 } 729 730 /* reset the registers regardless if there was an error or not */ 731 ti_i2c_set_intr_enable(sc, 0x0000); 732 ti_i2c_write_reg(sc, I2C_REG_CON, I2C_CON_I2C_EN | I2C_CON_MST | I2C_CON_STP); 733 734 return (err); 735 } 736 737 /** 738 * ti_i2c_transfer - called to perform the transfer 739 * @dev: i2c device handle 740 * @msgs: the messages to send/receive 741 * @nmsgs: the number of messages in the msgs array 742 * 743 * 744 * LOCKING: 745 * Internally locked 746 * 747 * RETURNS: 748 * 0 on function succeeded 749 * EINVAL if invalid message is passed as an arg 750 */ 751 static int 752 ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 753 { 754 struct ti_i2c_softc *sc = device_get_softc(dev); 755 int err = 0; 756 uint32_t i; 757 uint16_t len; 758 uint8_t *buf; 759 760 TI_I2C_LOCK(sc); 761 762 for (i = 0; i < nmsgs; i++) { 763 764 len = msgs[i].len; 765 buf = msgs[i].buf; 766 767 /* zero byte transfers aren't allowed */ 768 if (len == 0 || buf == NULL) { 769 err = EINVAL; 770 goto out; 771 } 772 773 /* set the slave address */ 774 ti_i2c_write_reg(sc, I2C_REG_SA, msgs[i].slave); 775 776 /* perform the read or write */ 777 if (msgs[i].flags & IIC_M_RD) { 778 err = ti_i2c_read_bytes(sc, buf, len); 779 } else { 780 err = ti_i2c_write_bytes(sc, buf, len); 781 } 782 783 } 784 785 out: 786 TI_I2C_UNLOCK(sc); 787 788 return (err); 789 } 790 791 /** 792 * ti_i2c_callback - not sure about this one 793 * @dev: i2c device handle 794 * 795 * 796 * 797 * LOCKING: 798 * Called from timer context 799 * 800 * RETURNS: 801 * EH_HANDLED or EH_NOT_HANDLED 802 */ 803 static int 804 ti_i2c_callback(device_t dev, int index, caddr_t data) 805 { 806 int error = 0; 807 808 switch (index) { 809 case IIC_REQUEST_BUS: 810 break; 811 812 case IIC_RELEASE_BUS: 813 break; 814 815 default: 816 error = EINVAL; 817 } 818 819 return (error); 820 } 821 822 /** 823 * ti_i2c_activate - initialises and activates an I2C bus 824 * @dev: i2c device handle 825 * @num: the number of the I2C controller to activate; 1, 2 or 3 826 * 827 * 828 * LOCKING: 829 * Assumed called in an atomic context. 830 * 831 * RETURNS: 832 * nothing 833 */ 834 static int 835 ti_i2c_activate(device_t dev) 836 { 837 struct ti_i2c_softc *sc = (struct ti_i2c_softc*) device_get_softc(dev); 838 unsigned int timeout = 0; 839 uint16_t con_reg; 840 int err; 841 clk_ident_t clk; 842 843 /* 844 * The following sequence is taken from the OMAP3530 technical reference 845 * 846 * 1. Enable the functional and interface clocks (see Section 18.3.1.1.1). 847 */ 848 clk = I2C0_CLK + sc->device_id; 849 err = ti_prcm_clk_enable(clk); 850 if (err) 851 return (err); 852 853 /* There seems to be a bug in the I2C reset mechanism, for some reason you 854 * need to disable the I2C module before issuing the reset and then enable 855 * it again after to detect the reset done. 856 * 857 * I found this out by looking at the Linux driver implementation, thanks 858 * linux guys! 859 */ 860 861 /* Disable the I2C controller */ 862 ti_i2c_write_reg(sc, I2C_REG_CON, 0x0000); 863 864 /* Issue a softreset to the controller */ 865 /* XXXOMAP3: FIXME */ 866 bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, 0x0002); 867 868 /* Re-enable the module and then check for the reset done */ 869 ti_i2c_write_reg(sc, I2C_REG_CON, I2C_CON_I2C_EN); 870 871 while ((ti_i2c_read_reg(sc, I2C_REG_SYSS) & 0x01) == 0x00) { 872 if (timeout++ > 100) { 873 return (EBUSY); 874 } 875 DELAY(100); 876 } 877 878 /* Disable the I2C controller once again, now that the reset has finished */ 879 ti_i2c_write_reg(sc, I2C_REG_CON, 0x0000); 880 881 /* 2. Program the prescaler to obtain an approximately 12-MHz internal 882 * sampling clock (I2Ci_INTERNAL_CLK) by programming the corresponding 883 * value in the I2Ci.I2C_PSC[3:0] PSC field. 884 * This value depends on the frequency of the functional clock (I2Ci_FCLK). 885 * Because this frequency is 96MHz, the I2Ci.I2C_PSC[7:0] PSC field value 886 * is 0x7. 887 */ 888 889 /* Program the prescaler to obtain an approximately 12-MHz internal 890 * sampling clock. 891 */ 892 ti_i2c_write_reg(sc, I2C_REG_PSC, 0x0017); 893 894 /* 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH fields 895 * to obtain a bit rate of 100K bps or 400K bps. These values depend on 896 * the internal sampling clock frequency (see Table 18-12). 897 */ 898 899 /* Set the bitrate to 100kbps */ 900 ti_i2c_write_reg(sc, I2C_REG_SCLL, 0x000d); 901 ti_i2c_write_reg(sc, I2C_REG_SCLH, 0x000f); 902 903 /* 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and 904 * I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of 400K bps or 905 * 3.4M bps (for the second phase of HS mode). These values depend on the 906 * internal sampling clock frequency (see Table 18-12). 907 * 908 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line 909 * capacitance exceeds 45 pF, program the CONTROL.CONTROL_DEVCONF1[12] 910 * I2C1HSMASTER bit for I2C1, the CONTROL.CONTROL_DEVCONF1[13] 911 * I2C2HSMASTER bit for I2C2, or the CONTROL.CONTROL_DEVCONF1[14] 912 * I2C3HSMASTER bit for I2C3. 913 */ 914 915 /* 6. Configure the Own Address of the I2C controller by storing it in the 916 * I2Ci.I2C_OA0 register. Up to four Own Addresses can be programmed in 917 * the I2Ci.I2C_OAi registers (with I = 0, 1, 2, 3) for each I2C 918 * controller. 919 * 920 * Note: For a 10-bit address, set the corresponding expand Own Address bit 921 * in the I2Ci.I2C_CON register. 922 */ 923 924 /* Driver currently always in single master mode so ignore this step */ 925 926 /* 7. Set the TX threshold (in transmitter mode) and the RX threshold (in 927 * receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to (TX 928 * threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX threshold 929 * - 1), where the TX and RX thresholds are greater than or equal to 1. 930 */ 931 932 /* Set the FIFO buffer threshold, note I2C1 & I2C2 have 8 byte FIFO, whereas 933 * I2C3 has 64 bytes. Threshold set to 5 for now. 934 */ 935 ti_i2c_write_reg(sc, I2C_REG_BUF, 0x0404); 936 937 /* 938 * 8. Take the I2C controller out of reset by setting the I2Ci.I2C_CON[15] 939 * I2C_EN bit to 1. 940 */ 941 ti_i2c_write_reg(sc, I2C_REG_CON, I2C_CON_I2C_EN | I2C_CON_OPMODE_STD); 942 943 /* 944 * To initialize the I2C controller, perform the following steps: 945 * 946 * 1. Configure the I2Ci.I2C_CON register: 947 * · For master or slave mode, set the I2Ci.I2C_CON[10] MST bit (0: slave, 948 * 1: master). 949 * · For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX bit 950 * (0: receiver, 1: transmitter). 951 */ 952 con_reg = ti_i2c_read_reg(sc, I2C_REG_CON); 953 con_reg |= I2C_CON_MST; 954 ti_i2c_write_reg(sc, I2C_REG_CON, con_reg); 955 956 /* 2. If using an interrupt to transmit/receive data, set to 1 the 957 * corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4] 958 * XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY bit 959 * for the receive interrupt). 960 */ 961 ti_i2c_set_intr_enable(sc, I2C_IE_XRDY | I2C_IE_RRDY); 962 963 /* 3. If using DMA to receive/transmit data, set to 1 the corresponding bit 964 * in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN bit for the 965 * receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit for the transmit 966 * DMA channel). 967 */ 968 969 /* not using DMA for now, so ignore this */ 970 971 return (0); 972 } 973 974 /** 975 * ti_i2c_deactivate - deactivates the controller and releases resources 976 * @dev: i2c device handle 977 * 978 * 979 * 980 * LOCKING: 981 * Assumed called in an atomic context. 982 * 983 * RETURNS: 984 * nothing 985 */ 986 static void 987 ti_i2c_deactivate(device_t dev) 988 { 989 struct ti_i2c_softc *sc = device_get_softc(dev); 990 clk_ident_t clk; 991 992 /* Disable the controller - cancel all transactions */ 993 ti_i2c_write_reg(sc, I2C_REG_CON, 0x0000); 994 995 /* Release the interrupt handler */ 996 if (sc->sc_irq_h) { 997 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h); 998 sc->sc_irq_h = 0; 999 } 1000 1001 bus_generic_detach(sc->sc_dev); 1002 1003 /* Unmap the I2C controller registers */ 1004 if (sc->sc_mem_res != 0) { 1005 bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->sc_irq_res), 1006 sc->sc_mem_res); 1007 sc->sc_mem_res = NULL; 1008 } 1009 1010 /* Release the IRQ resource */ 1011 if (sc->sc_irq_res != NULL) { 1012 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->sc_irq_res), 1013 sc->sc_irq_res); 1014 sc->sc_irq_res = NULL; 1015 } 1016 1017 /* Finally disable the functional and interface clocks */ 1018 clk = I2C0_CLK + sc->device_id; 1019 ti_prcm_clk_disable(clk); 1020 1021 return; 1022 } 1023 1024 /** 1025 * ti_i2c_probe - probe function for the driver 1026 * @dev: i2c device handle 1027 * 1028 * 1029 * 1030 * LOCKING: 1031 * 1032 * 1033 * RETURNS: 1034 * Always returns 0 1035 */ 1036 static int 1037 ti_i2c_probe(device_t dev) 1038 { 1039 1040 if (!ofw_bus_status_okay(dev)) 1041 return (ENXIO); 1042 1043 if (!ofw_bus_is_compatible(dev, "ti,i2c")) 1044 return (ENXIO); 1045 1046 device_set_desc(dev, "TI I2C Controller"); 1047 return (0); 1048 } 1049 1050 /** 1051 * ti_i2c_attach - attach function for the driver 1052 * @dev: i2c device handle 1053 * 1054 * Initialised driver data structures and activates the I2C controller. 1055 * 1056 * LOCKING: 1057 * 1058 * 1059 * RETURNS: 1060 * 1061 */ 1062 static int 1063 ti_i2c_attach(device_t dev) 1064 { 1065 struct ti_i2c_softc *sc = device_get_softc(dev); 1066 phandle_t node; 1067 pcell_t did; 1068 int err; 1069 int rid; 1070 1071 sc->sc_dev = dev; 1072 1073 /* Get the i2c device id from FDT */ 1074 node = ofw_bus_get_node(dev); 1075 if ((OF_getprop(node, "i2c-device-id", &did, sizeof(did))) <= 0) { 1076 device_printf(dev, "missing i2c-device-id attribute in FDT\n"); 1077 return (ENXIO); 1078 } 1079 sc->device_id = fdt32_to_cpu(did); 1080 1081 TI_I2C_LOCK_INIT(sc); 1082 1083 /* Get the memory resource for the register mapping */ 1084 rid = 0; 1085 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1086 RF_ACTIVE); 1087 if (sc->sc_mem_res == NULL) 1088 panic("%s: Cannot map registers", device_get_name(dev)); 1089 1090 /* Allocate an IRQ resource for the MMC controller */ 1091 rid = 0; 1092 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1093 RF_ACTIVE | RF_SHAREABLE); 1094 if (sc->sc_irq_res == NULL) { 1095 err = ENOMEM; 1096 goto out; 1097 } 1098 1099 /* First we _must_ activate the H/W */ 1100 err = ti_i2c_activate(dev); 1101 if (err) { 1102 device_printf(dev, "ti_i2c_activate failed\n"); 1103 goto out; 1104 } 1105 1106 /* XXXOMAP3: FIXME get proper revision here */ 1107 /* Read the version number of the I2C module */ 1108 sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff; 1109 1110 device_printf(dev, "I2C revision %d.%d\n", sc->sc_rev >> 4, 1111 sc->sc_rev & 0xf); 1112 1113 /* activate the interrupt */ 1114 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 1115 NULL, ti_i2c_intr, sc, &sc->sc_irq_h); 1116 if (err) 1117 goto out; 1118 1119 /* Attach to the iicbus */ 1120 if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) 1121 device_printf(dev, "could not allocate iicbus instance\n"); 1122 1123 /* Probe and attach the iicbus */ 1124 bus_generic_attach(dev); 1125 1126 out: 1127 if (err) { 1128 ti_i2c_deactivate(dev); 1129 TI_I2C_LOCK_DESTROY(sc); 1130 } 1131 1132 return (err); 1133 } 1134 1135 /** 1136 * ti_i2c_detach - detach function for the driver 1137 * @dev: i2c device handle 1138 * 1139 * 1140 * 1141 * LOCKING: 1142 * 1143 * 1144 * RETURNS: 1145 * Always returns 0 1146 */ 1147 static int 1148 ti_i2c_detach(device_t dev) 1149 { 1150 struct ti_i2c_softc *sc = device_get_softc(dev); 1151 int rv; 1152 1153 ti_i2c_deactivate(dev); 1154 1155 if (sc->sc_iicbus && (rv = device_delete_child(dev, sc->sc_iicbus)) != 0) 1156 return (rv); 1157 1158 TI_I2C_LOCK_DESTROY(sc); 1159 1160 return (0); 1161 } 1162 1163 1164 static phandle_t 1165 ti_i2c_get_node(device_t bus, device_t dev) 1166 { 1167 /* 1168 * Share controller node with iibus device 1169 */ 1170 return ofw_bus_get_node(bus); 1171 } 1172 1173 static device_method_t ti_i2c_methods[] = { 1174 /* Device interface */ 1175 DEVMETHOD(device_probe, ti_i2c_probe), 1176 DEVMETHOD(device_attach, ti_i2c_attach), 1177 DEVMETHOD(device_detach, ti_i2c_detach), 1178 1179 /* OFW methods */ 1180 DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node), 1181 1182 /* iicbus interface */ 1183 DEVMETHOD(iicbus_callback, ti_i2c_callback), 1184 DEVMETHOD(iicbus_reset, ti_i2c_reset), 1185 DEVMETHOD(iicbus_transfer, ti_i2c_transfer), 1186 { 0, 0 } 1187 }; 1188 1189 static driver_t ti_i2c_driver = { 1190 "iichb", 1191 ti_i2c_methods, 1192 sizeof(struct ti_i2c_softc), 1193 }; 1194 1195 DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, ti_i2c_devclass, 0, 0); 1196 DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, iicbus_devclass, 0, 0); 1197 1198 MODULE_DEPEND(ti_iic, ti_prcm, 1, 1, 1); 1199 MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1); 1200