xref: /freebsd/sys/arm/ti/ti_i2c.c (revision 3dcf5eb70598c88befd62f61f81e283e568ec519)
1 /*-
2  * Copyright (c) 2011
3  *	Ben Gray <ben.r.gray@gmail.com>.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 /**
29  * Driver for the I2C module on the TI SoC.
30  *
31  * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c).
32  *
33  * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses,
34  * 32 bit data access is not allowed and can corrupt register content.
35  *
36  * This driver currently doesn't use DMA for the transfer, although I hope to
37  * incorporate that sometime in the future.  The idea being that for transaction
38  * larger than a certain size the DMA engine is used, for anything less the
39  * normal interrupt/fifo driven option is used.
40  *
41  *
42  * WARNING: This driver uses mtx_sleep and interrupts to perform transactions,
43  * which means you can't do a transaction during startup before the interrupts
44  * have been enabled.  Hint - the freebsd function config_intrhook_establish().
45  */
46 
47 #include <sys/cdefs.h>
48 __FBSDID("$FreeBSD$");
49 
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/bus.h>
53 #include <sys/conf.h>
54 #include <sys/kernel.h>
55 #include <sys/lock.h>
56 #include <sys/mbuf.h>
57 #include <sys/malloc.h>
58 #include <sys/module.h>
59 #include <sys/mutex.h>
60 #include <sys/rman.h>
61 #include <machine/bus.h>
62 
63 #include <dev/fdt/fdt_common.h>
64 #include <dev/ofw/openfirm.h>
65 #include <dev/ofw/ofw_bus.h>
66 #include <dev/ofw/ofw_bus_subr.h>
67 
68 #include <arm/ti/ti_cpuid.h>
69 #include <arm/ti/ti_prcm.h>
70 #include <arm/ti/ti_i2c.h>
71 
72 #include <dev/iicbus/iiconf.h>
73 #include <dev/iicbus/iicbus.h>
74 
75 #include "iicbus_if.h"
76 
77 /**
78  *	I2C device driver context, a pointer to this is stored in the device
79  *	driver structure.
80  */
81 struct ti_i2c_softc
82 {
83 	device_t		sc_dev;
84 	uint32_t		device_id;
85 	struct resource*	sc_irq_res;
86 	struct resource*	sc_mem_res;
87 	device_t		sc_iicbus;
88 
89 	void*			sc_irq_h;
90 
91 	struct mtx		sc_mtx;
92 
93 	volatile uint16_t	sc_stat_flags;	/* contains the status flags last IRQ */
94 
95 	uint16_t		sc_rev;
96 };
97 
98 struct ti_i2c_clock_config
99 {
100 	int speed;
101 	int bitrate;
102 	uint8_t psc;		/* Fast/Standard mode prescale divider */
103 	uint8_t scll;		/* Fast/Standard mode SCL low time */
104 	uint8_t sclh;		/* Fast/Standard mode SCL high time */
105 	uint8_t hsscll;		/* High Speed mode SCL low time */
106 	uint8_t hssclh;		/* High Speed mode SCL high time */
107 };
108 
109 #if defined(SOC_OMAP4)
110 static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = {
111 	{ IIC_SLOW,      100000, 23,  13,  15, 0,  0},
112 	{ IIC_FAST,      400000,  9,   5,   7, 0,  0},
113 	{ IIC_FASTEST,	3310000,  1, 113, 115, 7, 10},
114 	{ -1, 0 }
115 };
116 #endif
117 
118 #if defined(SOC_TI_AM335X)
119 static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = {
120 	{ IIC_SLOW,      100000,  3,  53,  55, 0,  0},
121 	{ IIC_FAST,      400000,  3,   8,  10, 0,  0},
122 	{ IIC_FASTEST,   400000,  3,   8,  10, 0,  0}, /* This might be higher */
123 	{ -1, 0 }
124 };
125 #endif
126 
127 
128 #define TI_I2C_REV1  0x003C      /* OMAP3 */
129 #define TI_I2C_REV2  0x000A      /* OMAP4 */
130 
131 /**
132  *	Locking macros used throughout the driver
133  */
134 #define TI_I2C_LOCK(_sc)             mtx_lock(&(_sc)->sc_mtx)
135 #define	TI_I2C_UNLOCK(_sc)           mtx_unlock(&(_sc)->sc_mtx)
136 #define TI_I2C_LOCK_INIT(_sc) \
137 	mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
138 	         "ti_i2c", MTX_DEF)
139 #define TI_I2C_LOCK_DESTROY(_sc)      mtx_destroy(&_sc->sc_mtx);
140 #define TI_I2C_ASSERT_LOCKED(_sc)     mtx_assert(&_sc->sc_mtx, MA_OWNED);
141 #define TI_I2C_ASSERT_UNLOCKED(_sc)   mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
142 
143 #ifdef DEBUG
144 #define ti_i2c_dbg(_sc, fmt, args...) \
145     device_printf((_sc)->sc_dev, fmt, ##args)
146 #else
147 #define ti_i2c_dbg(_sc, fmt, args...)
148 #endif
149 
150 static devclass_t ti_i2c_devclass;
151 
152 /* bus entry points */
153 
154 static int ti_i2c_probe(device_t dev);
155 static int ti_i2c_attach(device_t dev);
156 static int ti_i2c_detach(device_t dev);
157 static void ti_i2c_intr(void *);
158 
159 /* OFW routine */
160 static phandle_t ti_i2c_get_node(device_t bus, device_t dev);
161 
162 /* helper routines */
163 static int ti_i2c_activate(device_t dev);
164 static void ti_i2c_deactivate(device_t dev);
165 
166 /**
167  *	ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers
168  *	@sc: I2C device context
169  *	@off: the byte offset within the register bank to read from.
170  *
171  *
172  *	LOCKING:
173  *	No locking required
174  *
175  *	RETURNS:
176  *	16-bit value read from the register.
177  */
178 static inline uint16_t
179 ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off)
180 {
181 	return bus_read_2(sc->sc_mem_res, off);
182 }
183 
184 /**
185  *	ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers
186  *	@sc: I2C device context
187  *	@off: the byte offset within the register bank to read from.
188  *	@val: the value to write into the register
189  *
190  *	LOCKING:
191  *	No locking required
192  *
193  *	RETURNS:
194  *	16-bit value read from the register.
195  */
196 static inline void
197 ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val)
198 {
199 	bus_write_2(sc->sc_mem_res, off, val);
200 }
201 
202 /**
203  *	ti_i2c_read_reg - reads a 16-bit value from one of the I2C registers
204  *	    take into account revision-dependent register offset
205  *	@sc: I2C device context
206  *	@off: the byte offset within the register bank to read from.
207  *
208  *
209  *	LOCKING:
210  *	No locking required
211  *
212  *	RETURNS:
213  *	16-bit value read from the register.
214  */
215 static inline uint16_t
216 ti_i2c_read_reg(struct ti_i2c_softc *sc, bus_size_t off)
217 {
218 	/* XXXOMAP3: FIXME add registers mapping here */
219 	return bus_read_2(sc->sc_mem_res, off);
220 }
221 
222 /**
223  *	ti_i2c_write_reg - writes a 16-bit value to one of the I2C registers
224  *	    take into account revision-dependent register offset
225  *	@sc: I2C device context
226  *	@off: the byte offset within the register bank to read from.
227  *	@val: the value to write into the register
228  *
229  *	LOCKING:
230  *	No locking required
231  *
232  *	RETURNS:
233  *	16-bit value read from the register.
234  */
235 static inline void
236 ti_i2c_write_reg(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val)
237 {
238 	/* XXXOMAP3: FIXME add registers mapping here */
239 	bus_write_2(sc->sc_mem_res, off, val);
240 }
241 
242 /**
243  *	ti_i2c_set_intr_enable - writes the interrupt enable register
244  *	@sc: I2C device context
245  *	@ie: bitmask of the interrupts to enable
246  *
247  *	This function is needed as writing the I2C_IE register on the OMAP4 devices
248  *	doesn't seem to actually enable the interrupt, rather you have to write
249  *	through the I2C_IRQENABLE_CLR and I2C_IRQENABLE_SET registers.
250  *
251  *	LOCKING:
252  *	No locking required
253  *
254  *	RETURNS:
255  *	Nothing.
256  */
257 static inline void
258 ti_i2c_set_intr_enable(struct ti_i2c_softc *sc, uint16_t ie)
259 {
260 	/* XXXOMAP3: FIXME */
261 	ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff);
262 	if (ie)
263 		ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, ie);
264 }
265 
266 /**
267  *	ti_i2c_reset - attach function for the driver
268  *	@dev: i2c device handle
269  *
270  *
271  *
272  *	LOCKING:
273  *	Called from timer context
274  *
275  *	RETURNS:
276  *	EH_HANDLED or EH_NOT_HANDLED
277  */
278 static int
279 ti_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
280 {
281 	struct ti_i2c_softc *sc = device_get_softc(dev);
282 	struct ti_i2c_clock_config *clkcfg;
283 	uint16_t con_reg;
284 
285 	switch (ti_chip()) {
286 #ifdef SOC_OMAP4
287 	case CHIP_OMAP_4:
288 		clkcfg = ti_omap4_i2c_clock_configs;
289 		break;
290 #endif
291 #ifdef SOC_TI_AM335X
292 	case CHIP_AM335X:
293 		clkcfg = ti_am335x_i2c_clock_configs;
294 		break;
295 #endif
296 	default:
297 		panic("Unknown Ti SoC, unable to reset the i2c");
298 	}
299 	while (clkcfg->speed != -1) {
300 		if (clkcfg->speed == speed)
301 			break;
302 		/* take slow if speed is unknown */
303 		if ((speed == IIC_UNKNOWN) && (clkcfg->speed == IIC_SLOW))
304 			break;
305 		clkcfg++;
306 	}
307 	if (clkcfg->speed == -1)
308 		return (EINVAL);
309 
310 	TI_I2C_LOCK(sc);
311 
312 	/* First disable the controller while changing the clocks */
313 	con_reg = ti_i2c_read_reg(sc, I2C_REG_CON);
314 	ti_i2c_write_reg(sc, I2C_REG_CON, 0x0000);
315 
316 	/* Program the prescaler */
317 	ti_i2c_write_reg(sc, I2C_REG_PSC, clkcfg->psc);
318 
319 	/* Set the bitrate */
320 	ti_i2c_write_reg(sc, I2C_REG_SCLL, clkcfg->scll | (clkcfg->hsscll<<8));
321 	ti_i2c_write_reg(sc, I2C_REG_SCLH, clkcfg->sclh | (clkcfg->hssclh<<8));
322 
323 	/* Check if we are dealing with high speed mode */
324 	if ((clkcfg->hsscll + clkcfg->hssclh) > 0)
325 		con_reg  = I2C_CON_OPMODE_HS;
326 	else
327 		con_reg  = I2C_CON_OPMODE_STD;
328 
329 	/* Enable the I2C module again */
330 	ti_i2c_write_reg(sc, I2C_REG_CON, I2C_CON_I2C_EN | con_reg);
331 
332 	TI_I2C_UNLOCK(sc);
333 
334 	return (IIC_ENOADDR);
335 }
336 
337 /**
338  *	ti_i2c_intr - interrupt handler for the I2C module
339  *	@dev: i2c device handle
340  *
341  *
342  *
343  *	LOCKING:
344  *	Called from timer context
345  *
346  *	RETURNS:
347  *	EH_HANDLED or EH_NOT_HANDLED
348  */
349 static void
350 ti_i2c_intr(void *arg)
351 {
352 	struct ti_i2c_softc *sc = (struct ti_i2c_softc*) arg;
353 	uint16_t status;
354 
355 	status = ti_i2c_read_reg(sc, I2C_REG_STAT);
356 	if (status == 0)
357 		return;
358 
359 	TI_I2C_LOCK(sc);
360 
361 	/* save the flags */
362 	sc->sc_stat_flags |= status;
363 
364 	/* clear the status flags */
365 	ti_i2c_write_reg(sc, I2C_REG_STAT, status);
366 
367 	/* wakeup the process the started the transaction */
368 	wakeup(sc);
369 
370 	TI_I2C_UNLOCK(sc);
371 
372 	return;
373 }
374 
375 /**
376  *	ti_i2c_wait - waits for the specific event to occur
377  *	@sc: i2c driver context
378  *	@flags: the event(s) to wait on, this is a bitmask of the I2C_STAT_??? flags
379  *	@statp: if not null will contain the status flags upon return
380  *	@timo: the number of ticks to wait
381  *
382  *
383  *
384  *	LOCKING:
385  *	The driver context must be locked before calling this function. Internally
386  *	the function sleeps, releasing the lock as it does so, however the lock is
387  *	always retaken before this function returns.
388  *
389  *	RETURNS:
390  *	0 if the event(s) were tripped within timeout period
391  *	EBUSY if timedout waiting for the events
392  *	ENXIO if a NACK event was received
393  */
394 static int
395 ti_i2c_wait(struct ti_i2c_softc *sc, uint16_t flags, uint16_t *statp, int timo)
396 {
397 	int waittime = timo;
398 	int start_ticks = ticks;
399 	int rc;
400 
401 	TI_I2C_ASSERT_LOCKED(sc);
402 
403 	/* check if the condition has already occured, the interrupt routine will
404 	 * clear the status flags.
405 	 */
406 	if ((sc->sc_stat_flags & flags) == 0) {
407 
408 		/* condition(s) haven't occured so sleep on the IRQ */
409 		while (waittime > 0) {
410 
411 			rc = mtx_sleep(sc, &sc->sc_mtx, 0, "I2Cwait", waittime);
412 			if (rc == EWOULDBLOCK) {
413 				/* timed-out, simply break out of the loop */
414 				break;
415 			} else {
416 				/* IRQ has been tripped, but need to sanity check we have the
417 				 * right events in the status flag.
418 				 */
419 				if ((sc->sc_stat_flags & flags) != 0)
420 					break;
421 
422 				/* event hasn't been tripped so wait some more */
423 				waittime -= (ticks - start_ticks);
424 				start_ticks = ticks;
425 			}
426 		}
427 	}
428 
429 	/* copy the actual status bits */
430 	if (statp != NULL)
431 		*statp = sc->sc_stat_flags;
432 
433 	/* return the status found */
434 	if ((sc->sc_stat_flags & flags) != 0)
435 		rc = 0;
436 	else
437 		rc = EBUSY;
438 
439 	/* clear the flags set by the interrupt handler */
440 	sc->sc_stat_flags = 0;
441 
442 	return (rc);
443 }
444 
445 /**
446  *	ti_i2c_wait_for_free_bus - waits for the bus to become free
447  *	@sc: i2c driver context
448  *	@timo: the time to wait for the bus to become free
449  *
450  *
451  *
452  *	LOCKING:
453  *	The driver context must be locked before calling this function. Internally
454  *	the function sleeps, releasing the lock as it does so, however the lock is
455  *	always taken before this function returns.
456  *
457  *	RETURNS:
458  *	0 if the event(s) were tripped within timeout period
459  *	EBUSY if timedout waiting for the events
460  *	ENXIO if a NACK event was received
461  */
462 static int
463 ti_i2c_wait_for_free_bus(struct ti_i2c_softc *sc, int timo)
464 {
465 	/* check if the bus is free, BB bit = 0 */
466 	if ((ti_i2c_read_reg(sc, I2C_REG_STAT) & I2C_STAT_BB) == 0)
467 		return 0;
468 
469 	/* enable bus free interrupts */
470 	ti_i2c_set_intr_enable(sc, I2C_IE_BF);
471 
472 	/* wait for the bus free interrupt to be tripped */
473 	return ti_i2c_wait(sc, I2C_STAT_BF, NULL, timo);
474 }
475 
476 /**
477  *	ti_i2c_read_bytes - attempts to perform a read operation
478  *	@sc: i2c driver context
479  *	@buf: buffer to hold the received bytes
480  *	@len: the number of bytes to read
481  *
482  *	This function assumes the slave address is already set
483  *
484  *	LOCKING:
485  *	The context lock should be held before calling this function
486  *
487  *	RETURNS:
488  *	0 on function succeeded
489  *	EINVAL if invalid message is passed as an arg
490  */
491 static int
492 ti_i2c_read_bytes(struct ti_i2c_softc *sc, uint8_t *buf, uint16_t len)
493 {
494 	int      timo = (hz / 4);
495 	int      err = 0;
496 	uint16_t con_reg;
497 	uint16_t events;
498 	uint16_t status;
499 	uint32_t amount = 0;
500 	uint32_t sofar = 0;
501 	uint32_t i;
502 
503 	/* wait for the bus to become free */
504 	err = ti_i2c_wait_for_free_bus(sc, timo);
505 	if (err != 0) {
506 		device_printf(sc->sc_dev, "bus never freed\n");
507 		return (err);
508 	}
509 
510 	/* set the events to wait for */
511 	events = I2C_IE_RDR |   /* Receive draining interrupt */
512 	         I2C_IE_RRDY |  /* Receive Data Ready interrupt */
513 	         I2C_IE_ARDY |  /* Register Access Ready interrupt */
514 	         I2C_IE_NACK |  /* No Acknowledgment interrupt */
515 	         I2C_IE_AL;
516 
517 	/* enable interrupts for the events we want */
518 	ti_i2c_set_intr_enable(sc, events);
519 
520 	/* write the number of bytes to read */
521 	ti_i2c_write_reg(sc, I2C_REG_CNT, len);
522 
523 	/* clear the write bit and initiate the read transaction. Setting the STT
524 	 * (start) bit initiates the transfer.
525 	 */
526 	con_reg = ti_i2c_read_reg(sc, I2C_REG_CON);
527 	con_reg &= ~I2C_CON_TRX;
528 	con_reg |=  I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
529 	ti_i2c_write_reg(sc, I2C_REG_CON, con_reg);
530 
531 	/* reading loop */
532 	while (1) {
533 
534 		/* wait for an event */
535 		err = ti_i2c_wait(sc, events, &status, timo);
536 		if (err != 0) {
537 			break;
538 		}
539 
540 		/* check for the error conditions */
541 		if (status & I2C_STAT_NACK) {
542 			/* no ACK from slave */
543 			ti_i2c_dbg(sc, "NACK\n");
544 			err = ENXIO;
545 			break;
546 		}
547 		if (status & I2C_STAT_AL) {
548 			/* arbitration lost */
549 			ti_i2c_dbg(sc, "Arbitration lost\n");
550 			err = ENXIO;
551 			break;
552 		}
553 
554 		/* check if we have finished */
555 		if (status & I2C_STAT_ARDY) {
556 			/* register access ready - transaction complete basically */
557 			ti_i2c_dbg(sc, "ARDY transaction complete\n");
558 			err = 0;
559 			break;
560 		}
561 
562 		/* read some data */
563 		if (status & I2C_STAT_RDR) {
564 			/* Receive draining interrupt - last data received */
565 			ti_i2c_dbg(sc, "Receive draining interrupt\n");
566 
567 			/* get the number of bytes in the FIFO */
568 			amount = ti_i2c_read_reg(sc, I2C_REG_BUFSTAT);
569 			amount >>= 8;
570 			amount &= 0x3f;
571 		}
572 		else if (status & I2C_STAT_RRDY) {
573 			/* Receive data ready interrupt - enough data received */
574 			ti_i2c_dbg(sc, "Receive data ready interrupt\n");
575 
576 			/* get the number of bytes in the FIFO */
577 			amount = ti_i2c_read_reg(sc, I2C_REG_BUF);
578 			amount >>= 8;
579 			amount &= 0x3f;
580 			amount += 1;
581 		}
582 
583 		/* sanity check we haven't overwritten the array */
584 		if ((sofar + amount) > len) {
585 			ti_i2c_dbg(sc, "to many bytes to read\n");
586 			amount = (len - sofar);
587 		}
588 
589 		/* read the bytes from the fifo */
590 		for (i = 0; i < amount; i++) {
591 			buf[sofar++] = (uint8_t)(ti_i2c_read_reg(sc, I2C_REG_DATA) & 0xff);
592 		}
593 
594 		/* attempt to clear the receive ready bits */
595 		ti_i2c_write_reg(sc, I2C_REG_STAT, I2C_STAT_RDR | I2C_STAT_RRDY);
596 	}
597 
598 	/* reset the registers regardless if there was an error or not */
599 	ti_i2c_set_intr_enable(sc, 0x0000);
600 	ti_i2c_write_reg(sc, I2C_REG_CON, I2C_CON_I2C_EN | I2C_CON_MST | I2C_CON_STP);
601 
602 	return (err);
603 }
604 
605 /**
606  *	ti_i2c_write_bytes - attempts to perform a read operation
607  *	@sc: i2c driver context
608  *	@buf: buffer containing the bytes to write
609  *	@len: the number of bytes to write
610  *
611  *	This function assumes the slave address is already set
612  *
613  *	LOCKING:
614  *	The context lock should be held before calling this function
615  *
616  *	RETURNS:
617  *	0 on function succeeded
618  *	EINVAL if invalid message is passed as an arg
619  */
620 static int
621 ti_i2c_write_bytes(struct ti_i2c_softc *sc, const uint8_t *buf, uint16_t len)
622 {
623 	int      timo = (hz / 4);
624 	int      err = 0;
625 	uint16_t con_reg;
626 	uint16_t events;
627 	uint16_t status;
628 	uint32_t amount = 0;
629 	uint32_t sofar = 0;
630 	uint32_t i;
631 
632 	/* wait for the bus to become free */
633 	err = ti_i2c_wait_for_free_bus(sc, timo);
634 	if (err != 0)
635 		return (err);
636 
637 	/* set the events to wait for */
638 	events = I2C_IE_XDR |   /* Transmit draining interrupt */
639 	         I2C_IE_XRDY |  /* Transmit Data Ready interrupt */
640 	         I2C_IE_ARDY |  /* Register Access Ready interrupt */
641 	         I2C_IE_NACK |  /* No Acknowledgment interrupt */
642 	         I2C_IE_AL;
643 
644 	/* enable interrupts for the events we want*/
645 	ti_i2c_set_intr_enable(sc, events);
646 
647 	/* write the number of bytes to write */
648 	ti_i2c_write_reg(sc, I2C_REG_CNT, len);
649 
650 	/* set the write bit and initiate the write transaction. Setting the STT
651 	 * (start) bit initiates the transfer.
652 	 */
653 	con_reg = ti_i2c_read_reg(sc, I2C_REG_CON);
654 	con_reg |= I2C_CON_TRX | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
655 	ti_i2c_write_reg(sc, I2C_REG_CON, con_reg);
656 
657 	/* writing loop */
658 	while (1) {
659 
660 		/* wait for an event */
661 		err = ti_i2c_wait(sc, events, &status, timo);
662 		if (err != 0) {
663 			break;
664 		}
665 
666 		/* check for the error conditions */
667 		if (status & I2C_STAT_NACK) {
668 			/* no ACK from slave */
669 			ti_i2c_dbg(sc, "NACK\n");
670 			err = ENXIO;
671 			break;
672 		}
673 		if (status & I2C_STAT_AL) {
674 			/* arbitration lost */
675 			ti_i2c_dbg(sc, "Arbitration lost\n");
676 			err = ENXIO;
677 			break;
678 		}
679 
680 		/* check if we have finished */
681 		if (status & I2C_STAT_ARDY) {
682 			/* register access ready - transaction complete basically */
683 			ti_i2c_dbg(sc, "ARDY transaction complete\n");
684 			err = 0;
685 			break;
686 		}
687 
688 		/* read some data */
689 		if (status & I2C_STAT_XDR) {
690 			/* Receive draining interrupt - last data received */
691 			ti_i2c_dbg(sc, "Transmit draining interrupt\n");
692 
693 			/* get the number of bytes in the FIFO */
694 			amount = ti_i2c_read_reg(sc, I2C_REG_BUFSTAT);
695 			amount &= 0x3f;
696 		}
697 		else if (status & I2C_STAT_XRDY) {
698 			/* Receive data ready interrupt - enough data received */
699 			ti_i2c_dbg(sc, "Transmit data ready interrupt\n");
700 
701 			/* get the number of bytes in the FIFO */
702 			amount = ti_i2c_read_reg(sc, I2C_REG_BUF);
703 			amount &= 0x3f;
704 			amount += 1;
705 		}
706 
707 		/* sanity check we haven't overwritten the array */
708 		if ((sofar + amount) > len) {
709 			ti_i2c_dbg(sc, "to many bytes to write\n");
710 			amount = (len - sofar);
711 		}
712 
713 		/* write the bytes from the fifo */
714 		for (i = 0; i < amount; i++) {
715 			ti_i2c_write_reg(sc, I2C_REG_DATA, buf[sofar++]);
716 		}
717 
718 		/* attempt to clear the transmit ready bits */
719 		ti_i2c_write_reg(sc, I2C_REG_STAT, I2C_STAT_XDR | I2C_STAT_XRDY);
720 	}
721 
722 	/* reset the registers regardless if there was an error or not */
723 	ti_i2c_set_intr_enable(sc, 0x0000);
724 	ti_i2c_write_reg(sc, I2C_REG_CON, I2C_CON_I2C_EN | I2C_CON_MST | I2C_CON_STP);
725 
726 	return (err);
727 }
728 
729 /**
730  *	ti_i2c_transfer - called to perform the transfer
731  *	@dev: i2c device handle
732  *	@msgs: the messages to send/receive
733  *	@nmsgs: the number of messages in the msgs array
734  *
735  *
736  *	LOCKING:
737  *	Internally locked
738  *
739  *	RETURNS:
740  *	0 on function succeeded
741  *	EINVAL if invalid message is passed as an arg
742  */
743 static int
744 ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
745 {
746 	struct ti_i2c_softc *sc = device_get_softc(dev);
747 	int err = 0;
748 	uint32_t i;
749 	uint16_t len;
750 	uint8_t *buf;
751 
752 	TI_I2C_LOCK(sc);
753 
754 	for (i = 0; i < nmsgs; i++) {
755 
756 		len = msgs[i].len;
757 		buf = msgs[i].buf;
758 
759 		/* zero byte transfers aren't allowed */
760 		if (len == 0 || buf == NULL) {
761 			err = EINVAL;
762 			goto out;
763 		}
764 
765 		/* set the slave address */
766 		ti_i2c_write_reg(sc, I2C_REG_SA, msgs[i].slave >> 1);
767 
768 		/* perform the read or write */
769 		if (msgs[i].flags & IIC_M_RD) {
770 			err = ti_i2c_read_bytes(sc, buf, len);
771 		} else {
772 			err = ti_i2c_write_bytes(sc, buf, len);
773 		}
774 
775 	}
776 
777 out:
778 	TI_I2C_UNLOCK(sc);
779 
780 	return (err);
781 }
782 
783 /**
784  *	ti_i2c_callback - not sure about this one
785  *	@dev: i2c device handle
786  *
787  *
788  *
789  *	LOCKING:
790  *	Called from timer context
791  *
792  *	RETURNS:
793  *	EH_HANDLED or EH_NOT_HANDLED
794  */
795 static int
796 ti_i2c_callback(device_t dev, int index, caddr_t data)
797 {
798 	int error = 0;
799 
800 	switch (index) {
801 		case IIC_REQUEST_BUS:
802 			break;
803 
804 		case IIC_RELEASE_BUS:
805 			break;
806 
807 		default:
808 			error = EINVAL;
809 	}
810 
811 	return (error);
812 }
813 
814 /**
815  *	ti_i2c_activate - initialises and activates an I2C bus
816  *	@dev: i2c device handle
817  *	@num: the number of the I2C controller to activate; 1, 2 or 3
818  *
819  *
820  *	LOCKING:
821  *	Assumed called in an atomic context.
822  *
823  *	RETURNS:
824  *	nothing
825  */
826 static int
827 ti_i2c_activate(device_t dev)
828 {
829 	struct ti_i2c_softc *sc = (struct ti_i2c_softc*) device_get_softc(dev);
830 	unsigned int timeout = 0;
831 	uint16_t con_reg;
832 	int err;
833 	clk_ident_t clk;
834 
835 	/*
836 	 * The following sequence is taken from the OMAP3530 technical reference
837 	 *
838 	 * 1. Enable the functional and interface clocks (see Section 18.3.1.1.1).
839 	 */
840 	clk = I2C0_CLK + sc->device_id;
841 	err = ti_prcm_clk_enable(clk);
842 	if (err)
843 		return (err);
844 
845 	/* There seems to be a bug in the I2C reset mechanism, for some reason you
846 	 * need to disable the I2C module before issuing the reset and then enable
847 	 * it again after to detect the reset done.
848 	 *
849 	 * I found this out by looking at the Linux driver implementation, thanks
850 	 * linux guys!
851 	 */
852 
853 	/* Disable the I2C controller */
854 	ti_i2c_write_reg(sc, I2C_REG_CON, 0x0000);
855 
856 	/* Issue a softreset to the controller */
857 	/* XXXOMAP3: FIXME */
858 	bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, 0x0002);
859 
860 	/* Re-enable the module and then check for the reset done */
861 	ti_i2c_write_reg(sc, I2C_REG_CON, I2C_CON_I2C_EN);
862 
863 	while ((ti_i2c_read_reg(sc, I2C_REG_SYSS) & 0x01) == 0x00) {
864 		if (timeout++ > 100) {
865 			return (EBUSY);
866 		}
867 		DELAY(100);
868 	}
869 
870 	/* Disable the I2C controller once again, now that the reset has finished */
871 	ti_i2c_write_reg(sc, I2C_REG_CON, 0x0000);
872 
873 	/* 2. Program the prescaler to obtain an approximately 12-MHz internal
874 	 *    sampling clock (I2Ci_INTERNAL_CLK) by programming the corresponding
875 	 *    value in the I2Ci.I2C_PSC[3:0] PSC field.
876 	 *    This value depends on the frequency of the functional clock (I2Ci_FCLK).
877 	 *    Because this frequency is 96MHz, the I2Ci.I2C_PSC[7:0] PSC field value
878 	 *    is 0x7.
879 	 */
880 
881 	/* Program the prescaler to obtain an approximately 12-MHz internal
882 	 * sampling clock.
883 	 */
884 	ti_i2c_write_reg(sc, I2C_REG_PSC, 0x0017);
885 
886 	/* 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH fields
887 	 *    to obtain a bit rate of 100K bps or 400K bps. These values depend on
888 	 *    the internal sampling clock frequency (see Table 18-12).
889 	 */
890 
891 	/* Set the bitrate to 100kbps */
892 	ti_i2c_write_reg(sc, I2C_REG_SCLL, 0x000d);
893 	ti_i2c_write_reg(sc, I2C_REG_SCLH, 0x000f);
894 
895 	/* 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and
896 	 *    I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of 400K bps or
897 	 *    3.4M bps (for the second phase of HS mode). These values depend on the
898 	 *    internal sampling clock frequency (see Table 18-12).
899 	 *
900 	 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line
901 	 *    capacitance exceeds 45 pF, program the CONTROL.CONTROL_DEVCONF1[12]
902 	 *    I2C1HSMASTER bit for I2C1, the CONTROL.CONTROL_DEVCONF1[13]
903 	 *    I2C2HSMASTER bit for I2C2, or the CONTROL.CONTROL_DEVCONF1[14]
904 	 *    I2C3HSMASTER bit for I2C3.
905 	 */
906 
907 	/* 6. Configure the Own Address of the I2C controller by storing it in the
908 	 *    I2Ci.I2C_OA0 register. Up to four Own Addresses can be programmed in
909 	 *    the I2Ci.I2C_OAi registers (with I = 0, 1, 2, 3) for each I2C
910 	 *    controller.
911 	 *
912 	 * Note: For a 10-bit address, set the corresponding expand Own Address bit
913 	 * in the I2Ci.I2C_CON register.
914 	 */
915 
916 	/* Driver currently always in single master mode so ignore this step */
917 
918 	/* 7. Set the TX threshold (in transmitter mode) and the RX threshold (in
919 	 *    receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to (TX
920 	 *    threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX threshold
921 	 *    - 1), where the TX and RX thresholds are greater than or equal to 1.
922 	 */
923 
924 	/* Set the FIFO buffer threshold, note I2C1 & I2C2 have 8 byte FIFO, whereas
925 	 * I2C3 has 64 bytes.  Threshold set to 5 for now.
926 	 */
927 	ti_i2c_write_reg(sc, I2C_REG_BUF, 0x0404);
928 
929 	/*
930 	 * 8. Take the I2C controller out of reset by setting the I2Ci.I2C_CON[15]
931 	 *    I2C_EN bit to 1.
932 	 */
933 	ti_i2c_write_reg(sc, I2C_REG_CON, I2C_CON_I2C_EN | I2C_CON_OPMODE_STD);
934 
935 	/*
936 	 * To initialize the I2C controller, perform the following steps:
937 	 *
938 	 * 1. Configure the I2Ci.I2C_CON register:
939 	 *    · For master or slave mode, set the I2Ci.I2C_CON[10] MST bit (0: slave,
940 	 *      1: master).
941 	 *    · For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX bit
942 	 *      (0: receiver, 1: transmitter).
943 	 */
944 	con_reg = ti_i2c_read_reg(sc, I2C_REG_CON);
945 	con_reg |= I2C_CON_MST;
946 	ti_i2c_write_reg(sc, I2C_REG_CON, con_reg);
947 
948 	/* 2. If using an interrupt to transmit/receive data, set to 1 the
949 	 *    corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4]
950 	 *    XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY bit
951 	 *    for the receive interrupt).
952 	 */
953 	ti_i2c_set_intr_enable(sc, I2C_IE_XRDY | I2C_IE_RRDY);
954 
955 	/* 3. If using DMA to receive/transmit data, set to 1 the corresponding bit
956 	 *    in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN bit for the
957 	 *    receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit for the transmit
958 	 *    DMA channel).
959 	 */
960 
961 	/* not using DMA for now, so ignore this */
962 
963 	return (0);
964 }
965 
966 /**
967  *	ti_i2c_deactivate - deactivates the controller and releases resources
968  *	@dev: i2c device handle
969  *
970  *
971  *
972  *	LOCKING:
973  *	Assumed called in an atomic context.
974  *
975  *	RETURNS:
976  *	nothing
977  */
978 static void
979 ti_i2c_deactivate(device_t dev)
980 {
981 	struct ti_i2c_softc *sc = device_get_softc(dev);
982 	clk_ident_t clk;
983 
984 	/* Disable the controller - cancel all transactions */
985 	ti_i2c_write_reg(sc, I2C_REG_CON, 0x0000);
986 
987 	/* Release the interrupt handler */
988 	if (sc->sc_irq_h) {
989 		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
990 		sc->sc_irq_h = 0;
991 	}
992 
993 	bus_generic_detach(sc->sc_dev);
994 
995 	/* Unmap the I2C controller registers */
996 	if (sc->sc_mem_res != 0) {
997 		bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->sc_irq_res),
998 							 sc->sc_mem_res);
999 		sc->sc_mem_res = NULL;
1000 	}
1001 
1002 	/* Release the IRQ resource */
1003 	if (sc->sc_irq_res != NULL) {
1004 		bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->sc_irq_res),
1005 							 sc->sc_irq_res);
1006 		sc->sc_irq_res = NULL;
1007 	}
1008 
1009 	/* Finally disable the functional and interface clocks */
1010 	clk = I2C0_CLK + sc->device_id;
1011 	ti_prcm_clk_disable(clk);
1012 
1013 	return;
1014 }
1015 
1016 /**
1017  *	ti_i2c_probe - probe function for the driver
1018  *	@dev: i2c device handle
1019  *
1020  *
1021  *
1022  *	LOCKING:
1023  *
1024  *
1025  *	RETURNS:
1026  *	Always returns 0
1027  */
1028 static int
1029 ti_i2c_probe(device_t dev)
1030 {
1031 
1032 	if (!ofw_bus_status_okay(dev))
1033 		return (ENXIO);
1034 
1035 	if (!ofw_bus_is_compatible(dev, "ti,i2c"))
1036 		return (ENXIO);
1037 
1038 	device_set_desc(dev, "TI I2C Controller");
1039 	return (0);
1040 }
1041 
1042 /**
1043  *	ti_i2c_attach - attach function for the driver
1044  *	@dev: i2c device handle
1045  *
1046  *	Initialised driver data structures and activates the I2C controller.
1047  *
1048  *	LOCKING:
1049  *
1050  *
1051  *	RETURNS:
1052  *
1053  */
1054 static int
1055 ti_i2c_attach(device_t dev)
1056 {
1057 	struct ti_i2c_softc *sc = device_get_softc(dev);
1058 	phandle_t node;
1059 	pcell_t did;
1060 	int err;
1061 	int rid;
1062 
1063 	sc->sc_dev = dev;
1064 
1065 	/* Get the i2c device id from FDT */
1066 	node = ofw_bus_get_node(dev);
1067 	if ((OF_getprop(node, "i2c-device-id", &did, sizeof(did))) <= 0) {
1068 		device_printf(dev, "missing i2c-device-id attribute in FDT\n");
1069 		return (ENXIO);
1070 	}
1071 	sc->device_id = fdt32_to_cpu(did);
1072 
1073 	TI_I2C_LOCK_INIT(sc);
1074 
1075 	/* Get the memory resource for the register mapping */
1076 	rid = 0;
1077 	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1078 	                                        RF_ACTIVE);
1079 	if (sc->sc_mem_res == NULL)
1080 		panic("%s: Cannot map registers", device_get_name(dev));
1081 
1082 	/* Allocate an IRQ resource for the MMC controller */
1083 	rid = 0;
1084 	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1085 	                                        RF_ACTIVE | RF_SHAREABLE);
1086 	if (sc->sc_irq_res == NULL) {
1087 		err = ENOMEM;
1088 		goto out;
1089 	}
1090 
1091 	/* First we _must_ activate the H/W */
1092 	err = ti_i2c_activate(dev);
1093 	if (err) {
1094 		device_printf(dev, "ti_i2c_activate failed\n");
1095 		goto out;
1096 	}
1097 
1098 	/* XXXOMAP3: FIXME get proper revision here */
1099 	/* Read the version number of the I2C module */
1100 	sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff;
1101 
1102 	device_printf(dev, "I2C revision %d.%d\n", sc->sc_rev >> 4,
1103 	    sc->sc_rev & 0xf);
1104 
1105 	/* activate the interrupt */
1106 	err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
1107 				NULL, ti_i2c_intr, sc, &sc->sc_irq_h);
1108 	if (err)
1109 		goto out;
1110 
1111 	/* Attach to the iicbus */
1112 	if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL)
1113 		device_printf(dev, "could not allocate iicbus instance\n");
1114 
1115 	/* Probe and attach the iicbus */
1116 	bus_generic_attach(dev);
1117 
1118 out:
1119 	if (err) {
1120 		ti_i2c_deactivate(dev);
1121 		TI_I2C_LOCK_DESTROY(sc);
1122 	}
1123 
1124 	return (err);
1125 }
1126 
1127 /**
1128  *	ti_i2c_detach - detach function for the driver
1129  *	@dev: i2c device handle
1130  *
1131  *
1132  *
1133  *	LOCKING:
1134  *
1135  *
1136  *	RETURNS:
1137  *	Always returns 0
1138  */
1139 static int
1140 ti_i2c_detach(device_t dev)
1141 {
1142 	struct ti_i2c_softc *sc = device_get_softc(dev);
1143 	int rv;
1144 
1145 	ti_i2c_deactivate(dev);
1146 
1147 	if (sc->sc_iicbus && (rv = device_delete_child(dev, sc->sc_iicbus)) != 0)
1148 		return (rv);
1149 
1150 	TI_I2C_LOCK_DESTROY(sc);
1151 
1152 	return (0);
1153 }
1154 
1155 
1156 static phandle_t
1157 ti_i2c_get_node(device_t bus, device_t dev)
1158 {
1159 	/*
1160 	 * Share controller node with iibus device
1161 	 */
1162 	return ofw_bus_get_node(bus);
1163 }
1164 
1165 static device_method_t ti_i2c_methods[] = {
1166 	/* Device interface */
1167 	DEVMETHOD(device_probe,		ti_i2c_probe),
1168 	DEVMETHOD(device_attach,	ti_i2c_attach),
1169 	DEVMETHOD(device_detach,	ti_i2c_detach),
1170 
1171 	/* OFW methods */
1172 	DEVMETHOD(ofw_bus_get_node,	ti_i2c_get_node),
1173 
1174 	/* iicbus interface */
1175 	DEVMETHOD(iicbus_callback,	ti_i2c_callback),
1176 	DEVMETHOD(iicbus_reset,		ti_i2c_reset),
1177 	DEVMETHOD(iicbus_transfer,	ti_i2c_transfer),
1178 	{ 0, 0 }
1179 };
1180 
1181 static driver_t ti_i2c_driver = {
1182 	"iichb",
1183 	ti_i2c_methods,
1184 	sizeof(struct ti_i2c_softc),
1185 };
1186 
1187 DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, ti_i2c_devclass, 0, 0);
1188 DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, iicbus_devclass, 0, 0);
1189 
1190 MODULE_DEPEND(ti_iic, ti_prcm, 1, 1, 1);
1191 MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1);
1192