xref: /freebsd/sys/arm/ti/ti_i2c.c (revision 39ee7a7a6bdd1557b1c3532abf60d139798ac88b)
1 /*-
2  * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
3  * Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 /**
29  * Driver for the I2C module on the TI SoC.
30  *
31  * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c).
32  *
33  * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses,
34  * 32 bit data access is not allowed and can corrupt register content.
35  *
36  * This driver currently doesn't use DMA for the transfer, although I hope to
37  * incorporate that sometime in the future.  The idea being that for transaction
38  * larger than a certain size the DMA engine is used, for anything less the
39  * normal interrupt/fifo driven option is used.
40  *
41  *
42  * WARNING: This driver uses mtx_sleep and interrupts to perform transactions,
43  * which means you can't do a transaction during startup before the interrupts
44  * have been enabled.  Hint - the freebsd function config_intrhook_establish().
45  */
46 
47 #include <sys/cdefs.h>
48 __FBSDID("$FreeBSD$");
49 
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/bus.h>
53 #include <sys/conf.h>
54 #include <sys/kernel.h>
55 #include <sys/lock.h>
56 #include <sys/mbuf.h>
57 #include <sys/malloc.h>
58 #include <sys/module.h>
59 #include <sys/mutex.h>
60 #include <sys/rman.h>
61 #include <sys/sysctl.h>
62 #include <machine/bus.h>
63 
64 #include <dev/ofw/openfirm.h>
65 #include <dev/ofw/ofw_bus.h>
66 #include <dev/ofw/ofw_bus_subr.h>
67 
68 #include <arm/ti/ti_cpuid.h>
69 #include <arm/ti/ti_prcm.h>
70 #include <arm/ti/ti_hwmods.h>
71 #include <arm/ti/ti_i2c.h>
72 
73 #include <dev/iicbus/iiconf.h>
74 #include <dev/iicbus/iicbus.h>
75 
76 #include "iicbus_if.h"
77 
78 /**
79  *	I2C device driver context, a pointer to this is stored in the device
80  *	driver structure.
81  */
82 struct ti_i2c_softc
83 {
84 	device_t		sc_dev;
85 	clk_ident_t		clk_id;
86 	struct resource*	sc_irq_res;
87 	struct resource*	sc_mem_res;
88 	device_t		sc_iicbus;
89 
90 	void*			sc_irq_h;
91 
92 	struct mtx		sc_mtx;
93 
94 	struct iic_msg*		sc_buffer;
95 	int			sc_bus_inuse;
96 	int			sc_buffer_pos;
97 	int			sc_error;
98 	int			sc_fifo_trsh;
99 	int			sc_timeout;
100 
101 	uint16_t		sc_con_reg;
102 	uint16_t		sc_rev;
103 };
104 
105 struct ti_i2c_clock_config
106 {
107 	u_int   frequency;	/* Bus frequency in Hz */
108 	uint8_t psc;		/* Fast/Standard mode prescale divider */
109 	uint8_t scll;		/* Fast/Standard mode SCL low time */
110 	uint8_t sclh;		/* Fast/Standard mode SCL high time */
111 	uint8_t hsscll;		/* High Speed mode SCL low time */
112 	uint8_t hssclh;		/* High Speed mode SCL high time */
113 };
114 
115 #if defined(SOC_OMAP4)
116 /*
117  * OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)).
118  * The prescaler values for 100KHz and 400KHz modes come from the table in the
119  * OMAP4 TRM.  The table doesn't list 1MHz; these values should give that speed.
120  */
121 static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = {
122 	{  100000, 23,  13,  15,  0,  0},
123 	{  400000,  9,   5,   7,  0,  0},
124 	{ 1000000,  3,   5,   7,  0,  0},
125 /*	{ 3200000,  1, 113, 115,  7, 10}, - HS mode */
126 	{       0 /* Table terminator */ }
127 };
128 #endif
129 
130 #if defined(SOC_TI_AM335X)
131 /*
132  * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5))
133  * In all cases we prescale the clock to 24MHz as recommended in the manual.
134  */
135 static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = {
136 	{  100000, 1, 111, 117, 0, 0},
137 	{  400000, 1,  23,  25, 0, 0},
138 	{ 1000000, 1,   5,   7, 0, 0},
139 	{       0 /* Table terminator */ }
140 };
141 #endif
142 
143 /**
144  *	Locking macros used throughout the driver
145  */
146 #define	TI_I2C_LOCK(_sc)		mtx_lock(&(_sc)->sc_mtx)
147 #define	TI_I2C_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
148 #define	TI_I2C_LOCK_INIT(_sc)						\
149 	mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev),	\
150 	    "ti_i2c", MTX_DEF)
151 #define	TI_I2C_LOCK_DESTROY(_sc)	mtx_destroy(&_sc->sc_mtx)
152 #define	TI_I2C_ASSERT_LOCKED(_sc)	mtx_assert(&_sc->sc_mtx, MA_OWNED)
153 #define	TI_I2C_ASSERT_UNLOCKED(_sc)	mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
154 
155 #ifdef DEBUG
156 #define	ti_i2c_dbg(_sc, fmt, args...)					\
157 	device_printf((_sc)->sc_dev, fmt, ##args)
158 #else
159 #define	ti_i2c_dbg(_sc, fmt, args...)
160 #endif
161 
162 /**
163  *	ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers
164  *	@sc: I2C device context
165  *	@off: the byte offset within the register bank to read from.
166  *
167  *
168  *	LOCKING:
169  *	No locking required
170  *
171  *	RETURNS:
172  *	16-bit value read from the register.
173  */
174 static inline uint16_t
175 ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off)
176 {
177 
178 	return (bus_read_2(sc->sc_mem_res, off));
179 }
180 
181 /**
182  *	ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers
183  *	@sc: I2C device context
184  *	@off: the byte offset within the register bank to read from.
185  *	@val: the value to write into the register
186  *
187  *	LOCKING:
188  *	No locking required
189  *
190  *	RETURNS:
191  *	16-bit value read from the register.
192  */
193 static inline void
194 ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val)
195 {
196 
197 	bus_write_2(sc->sc_mem_res, off, val);
198 }
199 
200 static int
201 ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status)
202 {
203 	int amount, done, i;
204 
205 	done = 0;
206 	amount = 0;
207 	/* Check for the error conditions. */
208 	if (status & I2C_STAT_NACK) {
209 		/* No ACK from slave. */
210 		ti_i2c_dbg(sc, "NACK\n");
211 		ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK);
212 		sc->sc_error = ENXIO;
213 	} else if (status & I2C_STAT_AL) {
214 		/* Arbitration lost. */
215 		ti_i2c_dbg(sc, "Arbitration lost\n");
216 		ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL);
217 		sc->sc_error = ENXIO;
218 	}
219 
220 	/* Check if we have finished. */
221 	if (status & I2C_STAT_ARDY) {
222 		/* Register access ready - transaction complete basically. */
223 		ti_i2c_dbg(sc, "ARDY transaction complete\n");
224 		if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) {
225 			ti_i2c_write_2(sc, I2C_REG_CON,
226 			    sc->sc_con_reg | I2C_CON_STP);
227 		}
228 		ti_i2c_write_2(sc, I2C_REG_STATUS,
229 		    I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY |
230 		    I2C_STAT_XDR | I2C_STAT_XRDY);
231 		return (1);
232 	}
233 
234 	if (sc->sc_buffer->flags & IIC_M_RD) {
235 		/* Read some data. */
236 		if (status & I2C_STAT_RDR) {
237 			/*
238 			 * Receive draining interrupt - last data received.
239 			 * The set FIFO threshold wont be reached to trigger
240 			 * RRDY.
241 			 */
242 			ti_i2c_dbg(sc, "Receive draining interrupt\n");
243 
244 			/*
245 			 * Drain the FIFO.  Read the pending data in the FIFO.
246 			 */
247 			amount = sc->sc_buffer->len - sc->sc_buffer_pos;
248 		} else if (status & I2C_STAT_RRDY) {
249 			/*
250 			 * Receive data ready interrupt - FIFO has reached the
251 			 * set threshold.
252 			 */
253 			ti_i2c_dbg(sc, "Receive data ready interrupt\n");
254 
255 			amount = min(sc->sc_fifo_trsh,
256 			    sc->sc_buffer->len - sc->sc_buffer_pos);
257 		}
258 
259 		/* Read the bytes from the fifo. */
260 		for (i = 0; i < amount; i++)
261 			sc->sc_buffer->buf[sc->sc_buffer_pos++] =
262 			    (uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff);
263 
264 		if (status & I2C_STAT_RDR)
265 			ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR);
266 		if (status & I2C_STAT_RRDY)
267 			ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY);
268 
269 	} else {
270 		/* Write some data. */
271 		if (status & I2C_STAT_XDR) {
272 			/*
273 			 * Transmit draining interrupt - FIFO level is below
274 			 * the set threshold and the amount of data still to
275 			 * be transferred wont reach the set FIFO threshold.
276 			 */
277 			ti_i2c_dbg(sc, "Transmit draining interrupt\n");
278 
279 			/*
280 			 * Drain the TX data.  Write the pending data in the
281 			 * FIFO.
282 			 */
283 			amount = sc->sc_buffer->len - sc->sc_buffer_pos;
284 		} else if (status & I2C_STAT_XRDY) {
285 			/*
286 			 * Transmit data ready interrupt - the FIFO level
287 			 * is below the set threshold.
288 			 */
289 			ti_i2c_dbg(sc, "Transmit data ready interrupt\n");
290 
291 			amount = min(sc->sc_fifo_trsh,
292 			    sc->sc_buffer->len - sc->sc_buffer_pos);
293 		}
294 
295 		/* Write the bytes from the fifo. */
296 		for (i = 0; i < amount; i++)
297 			ti_i2c_write_2(sc, I2C_REG_DATA,
298 			    sc->sc_buffer->buf[sc->sc_buffer_pos++]);
299 
300 		if (status & I2C_STAT_XDR)
301 			ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR);
302 		if (status & I2C_STAT_XRDY)
303 			ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY);
304 	}
305 
306 	return (done);
307 }
308 
309 /**
310  *	ti_i2c_intr - interrupt handler for the I2C module
311  *	@dev: i2c device handle
312  *
313  *
314  *
315  *	LOCKING:
316  *	Called from timer context
317  *
318  *	RETURNS:
319  *	EH_HANDLED or EH_NOT_HANDLED
320  */
321 static void
322 ti_i2c_intr(void *arg)
323 {
324 	int done;
325 	struct ti_i2c_softc *sc;
326 	uint16_t events, status;
327 
328  	sc = (struct ti_i2c_softc *)arg;
329 
330 	TI_I2C_LOCK(sc);
331 
332 	status = ti_i2c_read_2(sc, I2C_REG_STATUS);
333 	if (status == 0) {
334 		TI_I2C_UNLOCK(sc);
335 		return;
336 	}
337 
338 	/* Save enabled interrupts. */
339 	events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET);
340 
341 	/* We only care about enabled interrupts. */
342 	status &= events;
343 
344 	done = 0;
345 
346 	if (sc->sc_buffer != NULL)
347 		done = ti_i2c_transfer_intr(sc, status);
348 	else {
349 		ti_i2c_dbg(sc, "Transfer interrupt without buffer\n");
350 		sc->sc_error = EINVAL;
351 		done = 1;
352 	}
353 
354 	if (done)
355 		/* Wakeup the process that started the transaction. */
356 		wakeup(sc);
357 
358 	TI_I2C_UNLOCK(sc);
359 }
360 
361 /**
362  *	ti_i2c_transfer - called to perform the transfer
363  *	@dev: i2c device handle
364  *	@msgs: the messages to send/receive
365  *	@nmsgs: the number of messages in the msgs array
366  *
367  *
368  *	LOCKING:
369  *	Internally locked
370  *
371  *	RETURNS:
372  *	0 on function succeeded
373  *	EINVAL if invalid message is passed as an arg
374  */
375 static int
376 ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
377 {
378 	int err, i, repstart, timeout;
379 	struct ti_i2c_softc *sc;
380 	uint16_t reg;
381 
382  	sc = device_get_softc(dev);
383 	TI_I2C_LOCK(sc);
384 
385 	/* If the controller is busy wait until it is available. */
386 	while (sc->sc_bus_inuse == 1)
387 		mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0);
388 
389 	/* Now we have control over the I2C controller. */
390 	sc->sc_bus_inuse = 1;
391 
392 	err = 0;
393 	repstart = 0;
394 	for (i = 0; i < nmsgs; i++) {
395 
396 		sc->sc_buffer = &msgs[i];
397 		sc->sc_buffer_pos = 0;
398 		sc->sc_error = 0;
399 
400 		/* Zero byte transfers aren't allowed. */
401 		if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL ||
402 		    sc->sc_buffer->len == 0) {
403 			err = EINVAL;
404 			break;
405 		}
406 
407 		/* Check if the i2c bus is free. */
408 		if (repstart == 0) {
409 			/*
410 			 * On repeated start we send the START condition while
411 			 * the bus _is_ busy.
412 			 */
413 			timeout = 0;
414 			while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
415 				if (timeout++ > 100) {
416 					err = EBUSY;
417 					goto out;
418 				}
419 				DELAY(1000);
420 			}
421 			timeout = 0;
422 		} else
423 			repstart = 0;
424 
425 		if (sc->sc_buffer->flags & IIC_M_NOSTOP)
426 			repstart = 1;
427 
428 		/* Set the slave address. */
429 		ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1);
430 
431 		/* Write the data length. */
432 		ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len);
433 
434 		/* Clear the RX and the TX FIFO. */
435 		reg = ti_i2c_read_2(sc, I2C_REG_BUF);
436 		reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR;
437 		ti_i2c_write_2(sc, I2C_REG_BUF, reg);
438 
439 		reg = sc->sc_con_reg | I2C_CON_STT;
440 		if (repstart == 0)
441 			reg |= I2C_CON_STP;
442 		if ((sc->sc_buffer->flags & IIC_M_RD) == 0)
443 			reg |= I2C_CON_TRX;
444 		ti_i2c_write_2(sc, I2C_REG_CON, reg);
445 
446 		/* Wait for an event. */
447 		err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", sc->sc_timeout);
448 		if (err == 0)
449 			err = sc->sc_error;
450 
451 		if (err)
452 			break;
453 	}
454 
455 out:
456 	if (timeout == 0) {
457 		while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
458 			if (timeout++ > 100)
459 				break;
460 			DELAY(1000);
461 		}
462 	}
463 	/* Put the controller in master mode again. */
464 	if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0)
465 		ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
466 
467 	sc->sc_buffer = NULL;
468 	sc->sc_bus_inuse = 0;
469 
470 	/* Wake up the processes that are waiting for the bus. */
471 	wakeup(sc);
472 
473 	TI_I2C_UNLOCK(sc);
474 
475 	return (err);
476 }
477 
478 static int
479 ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed)
480 {
481 	int timeout;
482 	struct ti_i2c_clock_config *clkcfg;
483 	u_int busfreq;
484 	uint16_t fifo_trsh, reg, scll, sclh;
485 
486 	switch (ti_chip()) {
487 #ifdef SOC_OMAP4
488 	case CHIP_OMAP_4:
489 		clkcfg = ti_omap4_i2c_clock_configs;
490 		break;
491 #endif
492 #ifdef SOC_TI_AM335X
493 	case CHIP_AM335X:
494 		clkcfg = ti_am335x_i2c_clock_configs;
495 		break;
496 #endif
497 	default:
498 		panic("Unknown Ti SoC, unable to reset the i2c");
499 	}
500 
501 	/*
502 	 * If we haven't attached the bus yet, just init at the default slow
503 	 * speed.  This lets us get the hardware initialized enough to attach
504 	 * the bus which is where the real speed configuration is handled. After
505 	 * the bus is attached, get the configured speed from it.  Search the
506 	 * configuration table for the best speed we can do that doesn't exceed
507 	 * the requested speed.
508 	 */
509 	if (sc->sc_iicbus == NULL)
510 		busfreq = 100000;
511 	else
512 		busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
513 	for (;;) {
514 		if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq)
515 			break;
516 		clkcfg++;
517 	}
518 
519 	/*
520 	 * 23.1.4.3 - HS I2C Software Reset
521 	 *    From OMAP4 TRM at page 4068.
522 	 *
523 	 * 1. Ensure that the module is disabled.
524 	 */
525 	sc->sc_con_reg = 0;
526 	ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
527 
528 	/* 2. Issue a softreset to the controller. */
529 	bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST);
530 
531 	/*
532 	 * 3. Enable the module.
533 	 *    The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module
534 	 *    is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1.
535 	 */
536 	ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN);
537 
538  	/* 4. Wait for the software reset to complete. */
539 	timeout = 0;
540 	while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) {
541 		if (timeout++ > 100)
542 			return (EBUSY);
543 		DELAY(100);
544 	}
545 
546 	/*
547 	 * Disable the I2C controller once again, now that the reset has
548 	 * finished.
549 	 */
550 	ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
551 
552 	/*
553 	 * The following sequence is taken from the OMAP4 TRM at page 4077.
554 	 *
555 	 * 1. Enable the functional and interface clocks (see Section
556 	 *    23.1.5.1.1.1.1).  Done at ti_i2c_activate().
557 	 *
558 	 * 2. Program the prescaler to obtain an approximately 12MHz internal
559 	 *    sampling clock (I2Ci_INTERNAL_CLK) by programming the
560 	 *    corresponding value in the I2Ci.I2C_PSC[3:0] PSC field.
561 	 *    This value depends on the frequency of the functional clock
562 	 *    (I2Ci_FCLK).  Because this frequency is 96MHz, the
563 	 *    I2Ci.I2C_PSC[7:0] PSC field value is 0x7.
564 	 */
565 	ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc);
566 
567 	/*
568 	 * 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH
569 	 *    bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps.
570 	 *    These values depend on the internal sampling clock frequency
571 	 *    (see Table 23-8).
572 	 */
573 	scll = clkcfg->scll & I2C_SCLL_MASK;
574 	sclh = clkcfg->sclh & I2C_SCLH_MASK;
575 
576 	/*
577 	 * 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and
578 	 *    I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of
579 	 *    400K bps or 3.4M bps (for the second phase of HS mode).  These
580 	 *    values depend on the internal sampling clock frequency (see
581 	 *    Table 23-8).
582 	 *
583 	 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line
584 	 *    capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional
585 	 *    Multiplexing and Configuration).
586 	 */
587 	switch (ti_chip()) {
588 #ifdef SOC_OMAP4
589 	case CHIP_OMAP_4:
590 		if ((clkcfg->hsscll + clkcfg->hssclh) > 0) {
591 			scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT;
592 			sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT;
593 			sc->sc_con_reg |= I2C_CON_OPMODE_HS;
594 		}
595 		break;
596 #endif
597 	}
598 
599 	/* Write the selected bit rate. */
600 	ti_i2c_write_2(sc, I2C_REG_SCLL, scll);
601 	ti_i2c_write_2(sc, I2C_REG_SCLH, sclh);
602 
603 	/*
604 	 * 6. Configure the Own Address of the I2C controller by storing it in
605 	 *    the I2Ci.I2C_OA0 register.  Up to four Own Addresses can be
606 	 *    programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3)
607 	 *    for each I2C controller.
608 	 *
609 	 * Note: For a 10-bit address, set the corresponding expand Own Address
610 	 * bit in the I2Ci.I2C_CON register.
611 	 *
612 	 * Driver currently always in single master mode so ignore this step.
613 	 */
614 
615 	/*
616 	 * 7. Set the TX threshold (in transmitter mode) and the RX threshold
617 	 *    (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to
618 	 *    (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX
619 	 *    threshold - 1), where the TX and RX thresholds are greater than
620 	 *    or equal to 1.
621 	 *
622 	 * The threshold is set to 5 for now.
623 	 */
624 	fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK;
625 	reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT);
626 	ti_i2c_write_2(sc, I2C_REG_BUF, reg);
627 
628 	/*
629 	 * 8. Take the I2C controller out of reset by setting the
630 	 *    I2Ci.I2C_CON[15] I2C_EN bit to 1.
631 	 *
632 	 * 23.1.5.1.1.1.2 - Initialize the I2C Controller
633 	 *
634 	 * To initialize the I2C controller, perform the following steps:
635 	 *
636 	 * 1. Configure the I2Ci.I2C_CON register:
637 	 *     . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit
638 	 *       (0: slave, 1: master).
639 	 *     . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX
640 	 *       bit (0: receiver, 1: transmitter).
641 	 */
642 
643 	/* Enable the I2C controller in master mode. */
644 	sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST;
645 	ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
646 
647 	/*
648 	 * 2. If using an interrupt to transmit/receive data, set the
649 	 *    corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4]
650 	 *    XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY
651 	 *    bit for the receive interrupt).
652 	 */
653 
654 	/* Set the interrupts we want to be notified. */
655 	reg = I2C_IE_XDR |	/* Transmit draining interrupt. */
656 	    I2C_IE_XRDY |	/* Transmit Data Ready interrupt. */
657 	    I2C_IE_RDR |	/* Receive draining interrupt. */
658 	    I2C_IE_RRDY |	/* Receive Data Ready interrupt. */
659 	    I2C_IE_ARDY |	/* Register Access Ready interrupt. */
660 	    I2C_IE_NACK |	/* No Acknowledgment interrupt. */
661 	    I2C_IE_AL;		/* Arbitration lost interrupt. */
662 
663 	/* Enable the interrupts. */
664 	ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg);
665 
666 	/*
667 	 * 3. If using DMA to receive/transmit data, set to 1 the corresponding
668 	 *    bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN
669 	 *    bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit
670 	 *    for the transmit DMA channel).
671 	 *
672 	 * Not using DMA for now, so ignore this.
673 	 */
674 
675 	return (0);
676 }
677 
678 static int
679 ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
680 {
681 	struct ti_i2c_softc *sc;
682 	int err;
683 
684 	sc = device_get_softc(dev);
685 	TI_I2C_LOCK(sc);
686 	err = ti_i2c_reset(sc, speed);
687 	TI_I2C_UNLOCK(sc);
688 	if (err)
689 		return (err);
690 
691 	return (IIC_ENOADDR);
692 }
693 
694 static int
695 ti_i2c_activate(device_t dev)
696 {
697 	int err;
698 	struct ti_i2c_softc *sc;
699 
700 	sc = (struct ti_i2c_softc*)device_get_softc(dev);
701 
702 	/*
703 	 * 1. Enable the functional and interface clocks (see Section
704 	 * 23.1.5.1.1.1.1).
705 	 */
706 	err = ti_prcm_clk_enable(sc->clk_id);
707 	if (err)
708 		return (err);
709 
710 	return (ti_i2c_reset(sc, IIC_UNKNOWN));
711 }
712 
713 /**
714  *	ti_i2c_deactivate - deactivates the controller and releases resources
715  *	@dev: i2c device handle
716  *
717  *
718  *
719  *	LOCKING:
720  *	Assumed called in an atomic context.
721  *
722  *	RETURNS:
723  *	nothing
724  */
725 static void
726 ti_i2c_deactivate(device_t dev)
727 {
728 	struct ti_i2c_softc *sc = device_get_softc(dev);
729 
730 	/* Disable the controller - cancel all transactions. */
731 	ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff);
732 	ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff);
733 	ti_i2c_write_2(sc, I2C_REG_CON, 0);
734 
735 	/* Release the interrupt handler. */
736 	if (sc->sc_irq_h != NULL) {
737 		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
738 		sc->sc_irq_h = NULL;
739 	}
740 
741 	bus_generic_detach(sc->sc_dev);
742 
743 	/* Unmap the I2C controller registers. */
744 	if (sc->sc_mem_res != NULL) {
745 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
746 		sc->sc_mem_res = NULL;
747 	}
748 
749 	/* Release the IRQ resource. */
750 	if (sc->sc_irq_res != NULL) {
751 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
752 		sc->sc_irq_res = NULL;
753 	}
754 
755 	/* Finally disable the functional and interface clocks. */
756 	ti_prcm_clk_disable(sc->clk_id);
757 }
758 
759 static int
760 ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS)
761 {
762 	int clk, psc, sclh, scll;
763 	struct ti_i2c_softc *sc;
764 
765 	sc = arg1;
766 
767 	TI_I2C_LOCK(sc);
768 	/* Get the system prescaler value. */
769 	psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1;
770 
771 	/* Get the bitrate. */
772 	scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK;
773 	sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK;
774 
775 	clk = I2C_CLK / psc / (scll + 7 + sclh + 5);
776 	TI_I2C_UNLOCK(sc);
777 
778 	return (sysctl_handle_int(oidp, &clk, 0, req));
779 }
780 
781 static int
782 ti_i2c_sysctl_timeout(SYSCTL_HANDLER_ARGS)
783 {
784 	struct ti_i2c_softc *sc;
785 	unsigned int val;
786 	int err;
787 
788 	sc = arg1;
789 
790 	/*
791 	 * MTX_DEF lock can't be held while doing uimove in
792 	 * sysctl_handle_int
793 	 */
794 	TI_I2C_LOCK(sc);
795 	val = sc->sc_timeout;
796 	TI_I2C_UNLOCK(sc);
797 
798 	err = sysctl_handle_int(oidp, &val, 0, req);
799 	/* Write request? */
800 	if ((err == 0) && (req->newptr != NULL)) {
801 		TI_I2C_LOCK(sc);
802 		sc->sc_timeout = val;
803 		TI_I2C_UNLOCK(sc);
804 	}
805 
806 	return (err);
807 }
808 
809 static int
810 ti_i2c_probe(device_t dev)
811 {
812 
813 	if (!ofw_bus_status_okay(dev))
814 		return (ENXIO);
815 	if (!ofw_bus_is_compatible(dev, "ti,omap4-i2c"))
816 		return (ENXIO);
817 	device_set_desc(dev, "TI I2C Controller");
818 
819 	return (0);
820 }
821 
822 static int
823 ti_i2c_attach(device_t dev)
824 {
825 	int err, rid;
826 	phandle_t node;
827 	struct ti_i2c_softc *sc;
828 	struct sysctl_ctx_list *ctx;
829 	struct sysctl_oid_list *tree;
830 	uint16_t fifosz;
831 
832  	sc = device_get_softc(dev);
833 	sc->sc_dev = dev;
834 
835 	/* Get the i2c device id from FDT. */
836 	node = ofw_bus_get_node(dev);
837 	/* i2c ti,hwmods bindings is special: it start with index 1 */
838 	sc->clk_id = ti_hwmods_get_clock(dev);
839 	if (sc->clk_id == INVALID_CLK_IDENT) {
840 		device_printf(dev, "failed to get device id using ti,hwmod\n");
841 		return (ENXIO);
842 	}
843 
844 	/* Get the memory resource for the register mapping. */
845 	rid = 0;
846 	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
847 	    RF_ACTIVE);
848 	if (sc->sc_mem_res == NULL) {
849 		device_printf(dev, "Cannot map registers.\n");
850 		return (ENXIO);
851 	}
852 
853 	/* Allocate our IRQ resource. */
854 	rid = 0;
855 	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
856 	    RF_ACTIVE | RF_SHAREABLE);
857 	if (sc->sc_irq_res == NULL) {
858 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
859 		device_printf(dev, "Cannot allocate interrupt.\n");
860 		return (ENXIO);
861 	}
862 
863 	TI_I2C_LOCK_INIT(sc);
864 
865 	/* First of all, we _must_ activate the H/W. */
866 	err = ti_i2c_activate(dev);
867 	if (err) {
868 		device_printf(dev, "ti_i2c_activate failed\n");
869 		goto out;
870 	}
871 
872 	/* Read the version number of the I2C module */
873 	sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff;
874 
875 	/* Get the fifo size. */
876 	fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT);
877 	fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT;
878 	fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK;
879 
880 	device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n",
881 	    sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz);
882 
883 	/* Set the FIFO threshold to 5 for now. */
884 	sc->sc_fifo_trsh = 5;
885 
886 	/* Set I2C bus timeout */
887 	sc->sc_timeout = 5*hz;
888 
889 	ctx = device_get_sysctl_ctx(dev);
890 	tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
891 	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock",
892 	    CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
893 	    ti_i2c_sysctl_clk, "IU", "I2C bus clock");
894 
895 	SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_timeout",
896 	    CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
897 	    ti_i2c_sysctl_timeout, "IU", "I2C bus timeout (in ticks)");
898 
899 	/* Activate the interrupt. */
900 	err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
901 	    NULL, ti_i2c_intr, sc, &sc->sc_irq_h);
902 	if (err)
903 		goto out;
904 
905 	/* Attach the iicbus. */
906 	if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
907 		device_printf(dev, "could not allocate iicbus instance\n");
908 		err = ENXIO;
909 		goto out;
910 	}
911 
912 	/* Probe and attach the iicbus */
913 	bus_generic_attach(dev);
914 
915 out:
916 	if (err) {
917 		ti_i2c_deactivate(dev);
918 		TI_I2C_LOCK_DESTROY(sc);
919 	}
920 
921 	return (err);
922 }
923 
924 static int
925 ti_i2c_detach(device_t dev)
926 {
927 	struct ti_i2c_softc *sc;
928 	int rv;
929 
930  	sc = device_get_softc(dev);
931 	ti_i2c_deactivate(dev);
932 	TI_I2C_LOCK_DESTROY(sc);
933 	if (sc->sc_iicbus &&
934 	    (rv = device_delete_child(dev, sc->sc_iicbus)) != 0)
935 		return (rv);
936 
937 	return (0);
938 }
939 
940 static phandle_t
941 ti_i2c_get_node(device_t bus, device_t dev)
942 {
943 
944 	/* Share controller node with iibus device. */
945 	return (ofw_bus_get_node(bus));
946 }
947 
948 static device_method_t ti_i2c_methods[] = {
949 	/* Device interface */
950 	DEVMETHOD(device_probe,		ti_i2c_probe),
951 	DEVMETHOD(device_attach,	ti_i2c_attach),
952 	DEVMETHOD(device_detach,	ti_i2c_detach),
953 
954 	/* Bus interface */
955 	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
956 	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
957 	DEVMETHOD(bus_alloc_resource,	bus_generic_alloc_resource),
958 	DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
959 	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
960 	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
961 	DEVMETHOD(bus_adjust_resource,	bus_generic_adjust_resource),
962 	DEVMETHOD(bus_set_resource,	bus_generic_rl_set_resource),
963 	DEVMETHOD(bus_get_resource,	bus_generic_rl_get_resource),
964 
965 	/* OFW methods */
966 	DEVMETHOD(ofw_bus_get_node,	ti_i2c_get_node),
967 
968 	/* iicbus interface */
969 	DEVMETHOD(iicbus_callback,	iicbus_null_callback),
970 	DEVMETHOD(iicbus_reset,		ti_i2c_iicbus_reset),
971 	DEVMETHOD(iicbus_transfer,	ti_i2c_transfer),
972 
973 	DEVMETHOD_END
974 };
975 
976 static driver_t ti_i2c_driver = {
977 	"iichb",
978 	ti_i2c_methods,
979 	sizeof(struct ti_i2c_softc),
980 };
981 
982 static devclass_t ti_i2c_devclass;
983 
984 DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, ti_i2c_devclass, 0, 0);
985 DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, iicbus_devclass, 0, 0);
986 
987 MODULE_DEPEND(ti_iic, ti_prcm, 1, 1, 1);
988 MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1);
989