1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 5 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /** 31 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code 32 * here uses 0-5. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include "opt_platform.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/proc.h> 47 #include <sys/rman.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <sys/gpio.h> 51 #include <sys/interrupt.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 #include <machine/resource.h> 56 57 #include <arm/ti/ti_cpuid.h> 58 #include <arm/ti/ti_gpio.h> 59 #include <arm/ti/ti_scm.h> 60 #include <arm/ti/ti_prcm.h> 61 #include <arm/ti/ti_hwmods.h> 62 63 #include <dev/gpio/gpiobusvar.h> 64 #include <dev/ofw/openfirm.h> 65 #include <dev/ofw/ofw_bus.h> 66 #include <dev/ofw/ofw_bus_subr.h> 67 68 #include "gpio_if.h" 69 #include "ti_gpio_if.h" 70 #include "pic_if.h" 71 72 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X) 73 #error "Unknown SoC" 74 #endif 75 76 /* Register definitions */ 77 #define TI_GPIO_REVISION 0x0000 78 #define TI_GPIO_SYSCONFIG 0x0010 79 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024 80 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028 81 #define TI_GPIO_IRQSTATUS_0 0x002C /* writing a 0 has no effect */ 82 #define TI_GPIO_IRQSTATUS_1 0x0030 /* writing a 0 has no effect */ 83 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 /* writing a 0 has no effect */ 84 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 /* writing a 0 has no effect */ 85 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C /* writing a 0 has no effect */ 86 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 /* writing a 0 has no effect */ 87 #define TI_GPIO_IRQWAKEN_0 0x0044 88 #define TI_GPIO_IRQWAKEN_1 0x0048 89 #define TI_GPIO_SYSSTATUS 0x0114 90 #define TI_GPIO_IRQSTATUS1 0x0118 91 #define TI_GPIO_IRQENABLE1 0x011C 92 #define TI_GPIO_WAKEUPENABLE 0x0120 93 #define TI_GPIO_IRQSTATUS2 0x0128 94 #define TI_GPIO_IRQENABLE2 0x012C 95 #define TI_GPIO_CTRL 0x0130 96 #define TI_GPIO_OE 0x0134 97 #define TI_GPIO_DATAIN 0x0138 98 #define TI_GPIO_DATAOUT 0x013C 99 #define TI_GPIO_LEVELDETECT0 0x0140 /* RW register */ 100 #define TI_GPIO_LEVELDETECT1 0x0144 /* RW register */ 101 #define TI_GPIO_RISINGDETECT 0x0148 /* RW register */ 102 #define TI_GPIO_FALLINGDETECT 0x014C /* RW register */ 103 #define TI_GPIO_DEBOUNCENABLE 0x0150 104 #define TI_GPIO_DEBOUNCINGTIME 0x0154 105 #define TI_GPIO_CLEARWKUPENA 0x0180 106 #define TI_GPIO_SETWKUENA 0x0184 107 #define TI_GPIO_CLEARDATAOUT 0x0190 108 #define TI_GPIO_SETDATAOUT 0x0194 109 110 /* Other SoC Specific definitions */ 111 #define OMAP4_FIRST_GPIO_BANK 1 112 #define OMAP4_INTR_PER_BANK 1 113 #define OMAP4_GPIO_REV 0x50600801 114 #define AM335X_FIRST_GPIO_BANK 0 115 #define AM335X_INTR_PER_BANK 2 116 #define AM335X_GPIO_REV 0x50600801 117 #define PINS_PER_BANK 32 118 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK)) 119 120 static int ti_gpio_intr(void *arg); 121 static int ti_gpio_detach(device_t); 122 123 static int ti_gpio_pic_attach(struct ti_gpio_softc *sc); 124 static int ti_gpio_pic_detach(struct ti_gpio_softc *sc); 125 126 static u_int 127 ti_first_gpio_bank(void) 128 { 129 switch(ti_chip()) { 130 #ifdef SOC_OMAP4 131 case CHIP_OMAP_4: 132 return (OMAP4_FIRST_GPIO_BANK); 133 #endif 134 #ifdef SOC_TI_AM335X 135 case CHIP_AM335X: 136 return (AM335X_FIRST_GPIO_BANK); 137 #endif 138 } 139 return (0); 140 } 141 142 static uint32_t 143 ti_gpio_rev(void) 144 { 145 switch(ti_chip()) { 146 #ifdef SOC_OMAP4 147 case CHIP_OMAP_4: 148 return (OMAP4_GPIO_REV); 149 #endif 150 #ifdef SOC_TI_AM335X 151 case CHIP_AM335X: 152 return (AM335X_GPIO_REV); 153 #endif 154 } 155 return (0); 156 } 157 158 /** 159 * Macros for driver mutex locking 160 */ 161 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 162 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 163 #define TI_GPIO_LOCK_INIT(_sc) \ 164 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 165 "ti_gpio", MTX_SPIN) 166 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 167 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 168 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 169 170 /** 171 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers 172 * @sc: GPIO device context 173 * @bank: The bank to read from 174 * @off: The offset of a register from the GPIO register address range 175 * 176 * 177 * RETURNS: 178 * 32-bit value read from the register. 179 */ 180 static inline uint32_t 181 ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off) 182 { 183 return (bus_read_4(sc->sc_mem_res, off)); 184 } 185 186 /** 187 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers 188 * @sc: GPIO device context 189 * @bank: The bank to write to 190 * @off: The offset of a register from the GPIO register address range 191 * @val: The value to write into the register 192 * 193 * RETURNS: 194 * nothing 195 */ 196 static inline void 197 ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off, 198 uint32_t val) 199 { 200 bus_write_4(sc->sc_mem_res, off, val); 201 } 202 203 static inline void 204 ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask) 205 { 206 207 /* We clear both set of registers. */ 208 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask); 209 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask); 210 } 211 212 static inline void 213 ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask) 214 { 215 216 /* 217 * On OMAP4 we unmask only the MPU interrupt and on AM335x we 218 * also activate only the first interrupt. 219 */ 220 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask); 221 } 222 223 static inline void 224 ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask) 225 { 226 227 /* 228 * Acknowledge the interrupt on both registers even if we use only 229 * the first one. 230 */ 231 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask); 232 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask); 233 } 234 235 static inline uint32_t 236 ti_gpio_intr_status(struct ti_gpio_softc *sc) 237 { 238 uint32_t reg; 239 240 /* Get the status from both registers. */ 241 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0); 242 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1); 243 244 return (reg); 245 } 246 247 static device_t 248 ti_gpio_get_bus(device_t dev) 249 { 250 struct ti_gpio_softc *sc; 251 252 sc = device_get_softc(dev); 253 254 return (sc->sc_busdev); 255 } 256 257 /** 258 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 259 * @dev: gpio device handle 260 * @maxpin: pointer to a value that upon return will contain the maximum number 261 * of pins in the device. 262 * 263 * 264 * LOCKING: 265 * No locking required, returns static data. 266 * 267 * RETURNS: 268 * Returns 0 on success otherwise an error code 269 */ 270 static int 271 ti_gpio_pin_max(device_t dev, int *maxpin) 272 { 273 274 *maxpin = PINS_PER_BANK - 1; 275 276 return (0); 277 } 278 279 static int 280 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin) 281 { 282 283 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL) 284 return (EINVAL); 285 286 return (0); 287 } 288 289 /** 290 * ti_gpio_pin_getcaps - Gets the capabilities of a given pin 291 * @dev: gpio device handle 292 * @pin: the number of the pin 293 * @caps: pointer to a value that upon return will contain the capabilities 294 * 295 * Currently all pins have the same capability, notably: 296 * - GPIO_PIN_INPUT 297 * - GPIO_PIN_OUTPUT 298 * - GPIO_PIN_PULLUP 299 * - GPIO_PIN_PULLDOWN 300 * - GPIO_INTR_LEVEL_LOW 301 * - GPIO_INTR_LEVEL_HIGH 302 * - GPIO_INTR_EDGE_RISING 303 * - GPIO_INTR_EDGE_FALLING 304 * - GPIO_INTR_EDGE_BOTH 305 * 306 * LOCKING: 307 * No locking required, returns static data. 308 * 309 * RETURNS: 310 * Returns 0 on success otherwise an error code 311 */ 312 static int 313 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 314 { 315 struct ti_gpio_softc *sc; 316 317 sc = device_get_softc(dev); 318 if (ti_gpio_valid_pin(sc, pin) != 0) 319 return (EINVAL); 320 321 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP | 322 GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | 323 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | 324 GPIO_INTR_EDGE_BOTH); 325 326 return (0); 327 } 328 329 /** 330 * ti_gpio_pin_getflags - Gets the current flags of a given pin 331 * @dev: gpio device handle 332 * @pin: the number of the pin 333 * @flags: upon return will contain the current flags of the pin 334 * 335 * Reads the current flags of a given pin, here we actually read the H/W 336 * registers to determine the flags, rather than storing the value in the 337 * setflags call. 338 * 339 * LOCKING: 340 * Internally locks the context 341 * 342 * RETURNS: 343 * Returns 0 on success otherwise an error code 344 */ 345 static int 346 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 347 { 348 struct ti_gpio_softc *sc; 349 350 sc = device_get_softc(dev); 351 if (ti_gpio_valid_pin(sc, pin) != 0) 352 return (EINVAL); 353 354 /* Get the current pin state */ 355 TI_GPIO_LOCK(sc); 356 TI_GPIO_GET_FLAGS(dev, pin, flags); 357 TI_GPIO_UNLOCK(sc); 358 359 return (0); 360 } 361 362 /** 363 * ti_gpio_pin_getname - Gets the name of a given pin 364 * @dev: gpio device handle 365 * @pin: the number of the pin 366 * @name: buffer to put the name in 367 * 368 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 369 * of the pin. 370 * 371 * LOCKING: 372 * No locking required, returns static data. 373 * 374 * RETURNS: 375 * Returns 0 on success otherwise an error code 376 */ 377 static int 378 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 379 { 380 struct ti_gpio_softc *sc; 381 382 sc = device_get_softc(dev); 383 if (ti_gpio_valid_pin(sc, pin) != 0) 384 return (EINVAL); 385 386 /* Set a very simple name */ 387 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 388 name[GPIOMAXNAME - 1] = '\0'; 389 390 return (0); 391 } 392 393 /** 394 * ti_gpio_pin_setflags - Sets the flags for a given pin 395 * @dev: gpio device handle 396 * @pin: the number of the pin 397 * @flags: the flags to set 398 * 399 * The flags of the pin correspond to things like input/output mode, pull-ups, 400 * pull-downs, etc. This driver doesn't support all flags, only the following: 401 * - GPIO_PIN_INPUT 402 * - GPIO_PIN_OUTPUT 403 * - GPIO_PIN_PULLUP 404 * - GPIO_PIN_PULLDOWN 405 * 406 * LOCKING: 407 * Internally locks the context 408 * 409 * RETURNS: 410 * Returns 0 on success otherwise an error code 411 */ 412 static int 413 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 414 { 415 struct ti_gpio_softc *sc; 416 uint32_t oe; 417 418 sc = device_get_softc(dev); 419 if (ti_gpio_valid_pin(sc, pin) != 0) 420 return (EINVAL); 421 422 /* Set the GPIO mode and state */ 423 TI_GPIO_LOCK(sc); 424 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) { 425 TI_GPIO_UNLOCK(sc); 426 return (EINVAL); 427 } 428 429 /* If configuring as an output set the "output enable" bit */ 430 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 431 if (flags & GPIO_PIN_INPUT) 432 oe |= TI_GPIO_MASK(pin); 433 else 434 oe &= ~TI_GPIO_MASK(pin); 435 ti_gpio_write_4(sc, TI_GPIO_OE, oe); 436 TI_GPIO_UNLOCK(sc); 437 438 return (0); 439 } 440 441 /** 442 * ti_gpio_pin_set - Sets the current level on a GPIO pin 443 * @dev: gpio device handle 444 * @pin: the number of the pin 445 * @value: non-zero value will drive the pin high, otherwise the pin is 446 * driven low. 447 * 448 * 449 * LOCKING: 450 * Internally locks the context 451 * 452 * RETURNS: 453 * Returns 0 on success otherwise a error code 454 */ 455 static int 456 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 457 { 458 struct ti_gpio_softc *sc; 459 uint32_t reg; 460 461 sc = device_get_softc(dev); 462 if (ti_gpio_valid_pin(sc, pin) != 0) 463 return (EINVAL); 464 465 TI_GPIO_LOCK(sc); 466 if (value == GPIO_PIN_LOW) 467 reg = TI_GPIO_CLEARDATAOUT; 468 else 469 reg = TI_GPIO_SETDATAOUT; 470 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 471 TI_GPIO_UNLOCK(sc); 472 473 return (0); 474 } 475 476 /** 477 * ti_gpio_pin_get - Gets the current level on a GPIO pin 478 * @dev: gpio device handle 479 * @pin: the number of the pin 480 * @value: pointer to a value that upond return will contain the pin value 481 * 482 * The pin must be configured as an input pin beforehand, otherwise this 483 * function will fail. 484 * 485 * LOCKING: 486 * Internally locks the context 487 * 488 * RETURNS: 489 * Returns 0 on success otherwise a error code 490 */ 491 static int 492 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 493 { 494 struct ti_gpio_softc *sc; 495 uint32_t oe, reg, val; 496 497 sc = device_get_softc(dev); 498 if (ti_gpio_valid_pin(sc, pin) != 0) 499 return (EINVAL); 500 501 /* 502 * Return data from output latch when set as output and from the 503 * input register otherwise. 504 */ 505 TI_GPIO_LOCK(sc); 506 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 507 if (oe & TI_GPIO_MASK(pin)) 508 reg = TI_GPIO_DATAIN; 509 else 510 reg = TI_GPIO_DATAOUT; 511 val = ti_gpio_read_4(sc, reg); 512 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0; 513 TI_GPIO_UNLOCK(sc); 514 515 return (0); 516 } 517 518 /** 519 * ti_gpio_pin_toggle - Toggles a given GPIO pin 520 * @dev: gpio device handle 521 * @pin: the number of the pin 522 * 523 * 524 * LOCKING: 525 * Internally locks the context 526 * 527 * RETURNS: 528 * Returns 0 on success otherwise a error code 529 */ 530 static int 531 ti_gpio_pin_toggle(device_t dev, uint32_t pin) 532 { 533 struct ti_gpio_softc *sc; 534 uint32_t reg, val; 535 536 sc = device_get_softc(dev); 537 if (ti_gpio_valid_pin(sc, pin) != 0) 538 return (EINVAL); 539 540 /* Toggle the pin */ 541 TI_GPIO_LOCK(sc); 542 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT); 543 if (val & TI_GPIO_MASK(pin)) 544 reg = TI_GPIO_CLEARDATAOUT; 545 else 546 reg = TI_GPIO_SETDATAOUT; 547 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 548 TI_GPIO_UNLOCK(sc); 549 550 return (0); 551 } 552 553 static int 554 ti_gpio_bank_init(device_t dev) 555 { 556 int pin; 557 struct ti_gpio_softc *sc; 558 uint32_t flags, reg_oe, reg_set, rev; 559 clk_ident_t clk; 560 561 sc = device_get_softc(dev); 562 563 /* Enable the interface and functional clocks for the module. */ 564 clk = ti_hwmods_get_clock(dev); 565 if (clk == INVALID_CLK_IDENT) { 566 device_printf(dev, "failed to get device id based on ti,hwmods\n"); 567 return (EINVAL); 568 } 569 570 sc->sc_bank = clk - GPIO1_CLK + ti_first_gpio_bank(); 571 ti_prcm_clk_enable(clk); 572 573 /* 574 * Read the revision number of the module. TI don't publish the 575 * actual revision numbers, so instead the values have been 576 * determined by experimentation. 577 */ 578 rev = ti_gpio_read_4(sc, TI_GPIO_REVISION); 579 580 /* Check the revision. */ 581 if (rev != ti_gpio_rev()) { 582 device_printf(dev, "Warning: could not determine the revision " 583 "of GPIO module (revision:0x%08x)\n", rev); 584 return (EINVAL); 585 } 586 587 /* Disable interrupts for all pins. */ 588 ti_gpio_intr_clr(sc, 0xffffffff); 589 590 /* Init OE register based on pads configuration. */ 591 reg_oe = 0xffffffff; 592 reg_set = 0; 593 for (pin = 0; pin < PINS_PER_BANK; pin++) { 594 TI_GPIO_GET_FLAGS(dev, pin, &flags); 595 if (flags & GPIO_PIN_OUTPUT) { 596 reg_oe &= ~(1UL << pin); 597 if (flags & GPIO_PIN_PULLUP) 598 reg_set |= (1UL << pin); 599 } 600 } 601 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe); 602 if (reg_set) 603 ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set); 604 605 return (0); 606 } 607 608 /** 609 * ti_gpio_attach - attach function for the driver 610 * @dev: gpio device handle 611 * 612 * Allocates and sets up the driver context for all GPIO banks. This function 613 * expects the memory ranges and IRQs to already be allocated to the driver. 614 * 615 * LOCKING: 616 * None 617 * 618 * RETURNS: 619 * Always returns 0 620 */ 621 static int 622 ti_gpio_attach(device_t dev) 623 { 624 struct ti_gpio_softc *sc; 625 int err; 626 627 sc = device_get_softc(dev); 628 sc->sc_dev = dev; 629 TI_GPIO_LOCK_INIT(sc); 630 ti_gpio_pin_max(dev, &sc->sc_maxpin); 631 sc->sc_maxpin++; 632 633 sc->sc_mem_rid = 0; 634 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 635 &sc->sc_mem_rid, RF_ACTIVE); 636 if (!sc->sc_mem_res) { 637 device_printf(dev, "Error: could not allocate mem resources\n"); 638 ti_gpio_detach(dev); 639 return (ENXIO); 640 } 641 642 sc->sc_irq_rid = 0; 643 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 644 &sc->sc_irq_rid, RF_ACTIVE); 645 if (!sc->sc_irq_res) { 646 device_printf(dev, "Error: could not allocate irq resources\n"); 647 ti_gpio_detach(dev); 648 return (ENXIO); 649 } 650 651 /* 652 * Register our interrupt filter for each of the IRQ resources. 653 */ 654 if (bus_setup_intr(dev, sc->sc_irq_res, 655 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc, 656 &sc->sc_irq_hdl) != 0) { 657 device_printf(dev, 658 "WARNING: unable to register interrupt filter\n"); 659 ti_gpio_detach(dev); 660 return (ENXIO); 661 } 662 663 if (ti_gpio_pic_attach(sc) != 0) { 664 device_printf(dev, "WARNING: unable to attach PIC\n"); 665 ti_gpio_detach(dev); 666 return (ENXIO); 667 } 668 669 /* We need to go through each block and ensure the clocks are running and 670 * the module is enabled. It might be better to do this only when the 671 * pins are configured which would result in less power used if the GPIO 672 * pins weren't used ... 673 */ 674 if (sc->sc_mem_res != NULL) { 675 /* Initialize the GPIO module. */ 676 err = ti_gpio_bank_init(dev); 677 if (err != 0) { 678 ti_gpio_detach(dev); 679 return (err); 680 } 681 } 682 683 sc->sc_busdev = gpiobus_attach_bus(dev); 684 if (sc->sc_busdev == NULL) { 685 ti_gpio_detach(dev); 686 return (ENXIO); 687 } 688 689 return (0); 690 } 691 692 /** 693 * ti_gpio_detach - detach function for the driver 694 * @dev: scm device handle 695 * 696 * Allocates and sets up the driver context, this simply entails creating a 697 * bus mappings for the SCM register set. 698 * 699 * LOCKING: 700 * None 701 * 702 * RETURNS: 703 * Always returns 0 704 */ 705 static int 706 ti_gpio_detach(device_t dev) 707 { 708 struct ti_gpio_softc *sc = device_get_softc(dev); 709 710 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 711 712 /* Disable all interrupts */ 713 if (sc->sc_mem_res != NULL) 714 ti_gpio_intr_clr(sc, 0xffffffff); 715 if (sc->sc_busdev != NULL) 716 gpiobus_detach_bus(dev); 717 if (sc->sc_isrcs != NULL) 718 ti_gpio_pic_detach(sc); 719 /* Release the memory and IRQ resources. */ 720 if (sc->sc_irq_hdl) { 721 bus_teardown_intr(dev, sc->sc_irq_res, 722 sc->sc_irq_hdl); 723 } 724 if (sc->sc_irq_res) 725 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 726 sc->sc_irq_res); 727 if (sc->sc_mem_res) 728 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 729 sc->sc_mem_res); 730 TI_GPIO_LOCK_DESTROY(sc); 731 732 return (0); 733 } 734 735 static inline void 736 ti_gpio_rwreg_modify(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask, 737 bool set_bits) 738 { 739 uint32_t value; 740 741 value = ti_gpio_read_4(sc, reg); 742 ti_gpio_write_4(sc, reg, set_bits ? value | mask : value & ~mask); 743 } 744 745 static inline void 746 ti_gpio_isrc_mask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 747 { 748 749 /* Writing a 0 has no effect. */ 750 ti_gpio_intr_clr(sc, tgi->tgi_mask); 751 } 752 753 static inline void 754 ti_gpio_isrc_unmask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 755 { 756 757 /* Writing a 0 has no effect. */ 758 ti_gpio_intr_set(sc, tgi->tgi_mask); 759 } 760 761 static inline void 762 ti_gpio_isrc_eoi(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 763 { 764 765 /* Writing a 0 has no effect. */ 766 ti_gpio_intr_ack(sc, tgi->tgi_mask); 767 } 768 769 static inline bool 770 ti_gpio_isrc_is_level(struct ti_gpio_irqsrc *tgi) 771 { 772 773 return (tgi->tgi_mode == GPIO_INTR_LEVEL_LOW || 774 tgi->tgi_mode == GPIO_INTR_LEVEL_HIGH); 775 } 776 777 static int 778 ti_gpio_intr(void *arg) 779 { 780 u_int irq; 781 uint32_t reg; 782 struct ti_gpio_softc *sc; 783 struct trapframe *tf; 784 struct ti_gpio_irqsrc *tgi; 785 786 sc = (struct ti_gpio_softc *)arg; 787 tf = curthread->td_intr_frame; 788 789 reg = ti_gpio_intr_status(sc); 790 for (irq = 0; irq < sc->sc_maxpin; irq++) { 791 tgi = &sc->sc_isrcs[irq]; 792 if ((reg & tgi->tgi_mask) == 0) 793 continue; 794 if (!ti_gpio_isrc_is_level(tgi)) 795 ti_gpio_isrc_eoi(sc, tgi); 796 if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) { 797 ti_gpio_isrc_mask(sc, tgi); 798 if (ti_gpio_isrc_is_level(tgi)) 799 ti_gpio_isrc_eoi(sc, tgi); 800 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 801 irq); 802 } 803 } 804 return (FILTER_HANDLED); 805 } 806 807 static int 808 ti_gpio_pic_attach(struct ti_gpio_softc *sc) 809 { 810 int error; 811 uint32_t irq; 812 const char *name; 813 814 sc->sc_isrcs = malloc(sizeof(*sc->sc_isrcs) * sc->sc_maxpin, M_DEVBUF, 815 M_WAITOK | M_ZERO); 816 817 name = device_get_nameunit(sc->sc_dev); 818 for (irq = 0; irq < sc->sc_maxpin; irq++) { 819 sc->sc_isrcs[irq].tgi_irq = irq; 820 sc->sc_isrcs[irq].tgi_mask = TI_GPIO_MASK(irq); 821 sc->sc_isrcs[irq].tgi_mode = GPIO_INTR_CONFORM; 822 823 error = intr_isrc_register(&sc->sc_isrcs[irq].tgi_isrc, 824 sc->sc_dev, 0, "%s,%u", name, irq); 825 if (error != 0) 826 return (error); /* XXX deregister ISRCs */ 827 } 828 if (intr_pic_register(sc->sc_dev, 829 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL) 830 return (ENXIO); 831 832 return (0); 833 } 834 835 static int 836 ti_gpio_pic_detach(struct ti_gpio_softc *sc) 837 { 838 839 /* 840 * There has not been established any procedure yet 841 * how to detach PIC from living system correctly. 842 */ 843 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 844 return (EBUSY); 845 } 846 847 static void 848 ti_gpio_pic_config_intr(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi, 849 uint32_t mode) 850 { 851 852 TI_GPIO_LOCK(sc); 853 ti_gpio_rwreg_modify(sc, TI_GPIO_RISINGDETECT, tgi->tgi_mask, 854 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH); 855 ti_gpio_rwreg_modify(sc, TI_GPIO_FALLINGDETECT, tgi->tgi_mask, 856 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH); 857 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT1, tgi->tgi_mask, 858 mode == GPIO_INTR_LEVEL_HIGH); 859 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT0, tgi->tgi_mask, 860 mode == GPIO_INTR_LEVEL_LOW); 861 tgi->tgi_mode = mode; 862 TI_GPIO_UNLOCK(sc); 863 } 864 865 static void 866 ti_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 867 { 868 struct ti_gpio_softc *sc = device_get_softc(dev); 869 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 870 871 ti_gpio_isrc_mask(sc, tgi); 872 } 873 874 static void 875 ti_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 876 { 877 struct ti_gpio_softc *sc = device_get_softc(dev); 878 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 879 880 arm_irq_memory_barrier(tgi->tgi_irq); 881 ti_gpio_isrc_unmask(sc, tgi); 882 } 883 884 static int 885 ti_gpio_pic_map_fdt(struct ti_gpio_softc *sc, struct intr_map_data_fdt *daf, 886 u_int *irqp, uint32_t *modep) 887 { 888 uint32_t mode; 889 890 /* 891 * The first cell is the interrupt number. 892 * The second cell is used to specify flags: 893 * bits[3:0] trigger type and level flags: 894 * 1 = low-to-high edge triggered. 895 * 2 = high-to-low edge triggered. 896 * 4 = active high level-sensitive. 897 * 8 = active low level-sensitive. 898 */ 899 if (daf->ncells != 2 || daf->cells[0] >= sc->sc_maxpin) 900 return (EINVAL); 901 902 /* Only reasonable modes are supported. */ 903 if (daf->cells[1] == 1) 904 mode = GPIO_INTR_EDGE_RISING; 905 else if (daf->cells[1] == 2) 906 mode = GPIO_INTR_EDGE_FALLING; 907 else if (daf->cells[1] == 3) 908 mode = GPIO_INTR_EDGE_BOTH; 909 else if (daf->cells[1] == 4) 910 mode = GPIO_INTR_LEVEL_HIGH; 911 else if (daf->cells[1] == 8) 912 mode = GPIO_INTR_LEVEL_LOW; 913 else 914 return (EINVAL); 915 916 *irqp = daf->cells[0]; 917 if (modep != NULL) 918 *modep = mode; 919 return (0); 920 } 921 922 static int 923 ti_gpio_pic_map_gpio(struct ti_gpio_softc *sc, struct intr_map_data_gpio *dag, 924 u_int *irqp, uint32_t *modep) 925 { 926 uint32_t mode; 927 928 if (dag->gpio_pin_num >= sc->sc_maxpin) 929 return (EINVAL); 930 931 mode = dag->gpio_intr_mode; 932 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH && 933 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING && 934 mode != GPIO_INTR_EDGE_BOTH) 935 return (EINVAL); 936 937 *irqp = dag->gpio_pin_num; 938 if (modep != NULL) 939 *modep = mode; 940 return (0); 941 } 942 943 static int 944 ti_gpio_pic_map(struct ti_gpio_softc *sc, struct intr_map_data *data, 945 u_int *irqp, uint32_t *modep) 946 { 947 948 switch (data->type) { 949 case INTR_MAP_DATA_FDT: 950 return (ti_gpio_pic_map_fdt(sc, 951 (struct intr_map_data_fdt *)data, irqp, modep)); 952 case INTR_MAP_DATA_GPIO: 953 return (ti_gpio_pic_map_gpio(sc, 954 (struct intr_map_data_gpio *)data, irqp, modep)); 955 default: 956 return (ENOTSUP); 957 } 958 } 959 960 static int 961 ti_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 962 struct intr_irqsrc **isrcp) 963 { 964 int error; 965 u_int irq; 966 struct ti_gpio_softc *sc = device_get_softc(dev); 967 968 error = ti_gpio_pic_map(sc, data, &irq, NULL); 969 if (error == 0) 970 *isrcp = &sc->sc_isrcs[irq].tgi_isrc; 971 return (error); 972 } 973 974 static void 975 ti_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 976 { 977 struct ti_gpio_softc *sc = device_get_softc(dev); 978 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 979 980 if (ti_gpio_isrc_is_level(tgi)) 981 ti_gpio_isrc_eoi(sc, tgi); 982 } 983 984 static void 985 ti_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 986 { 987 988 ti_gpio_pic_enable_intr(dev, isrc); 989 } 990 991 static void 992 ti_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 993 { 994 struct ti_gpio_softc *sc = device_get_softc(dev); 995 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 996 997 ti_gpio_isrc_mask(sc, tgi); 998 if (ti_gpio_isrc_is_level(tgi)) 999 ti_gpio_isrc_eoi(sc, tgi); 1000 } 1001 1002 static int 1003 ti_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1004 struct resource *res, struct intr_map_data *data) 1005 { 1006 u_int irq; 1007 uint32_t mode; 1008 struct ti_gpio_softc *sc; 1009 struct ti_gpio_irqsrc *tgi; 1010 1011 if (data == NULL) 1012 return (ENOTSUP); 1013 1014 sc = device_get_softc(dev); 1015 tgi = (struct ti_gpio_irqsrc *)isrc; 1016 1017 /* Get and check config for an interrupt. */ 1018 if (ti_gpio_pic_map(sc, data, &irq, &mode) != 0 || tgi->tgi_irq != irq) 1019 return (EINVAL); 1020 1021 /* 1022 * If this is a setup for another handler, 1023 * only check that its configuration match. 1024 */ 1025 if (isrc->isrc_handlers != 0) 1026 return (tgi->tgi_mode == mode ? 0 : EINVAL); 1027 1028 ti_gpio_pic_config_intr(sc, tgi, mode); 1029 return (0); 1030 } 1031 1032 static int 1033 ti_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1034 struct resource *res, struct intr_map_data *data) 1035 { 1036 struct ti_gpio_softc *sc = device_get_softc(dev); 1037 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1038 1039 if (isrc->isrc_handlers == 0) 1040 ti_gpio_pic_config_intr(sc, tgi, GPIO_INTR_CONFORM); 1041 return (0); 1042 } 1043 1044 static phandle_t 1045 ti_gpio_get_node(device_t bus, device_t dev) 1046 { 1047 1048 /* We only have one child, the GPIO bus, which needs our own node. */ 1049 return (ofw_bus_get_node(bus)); 1050 } 1051 1052 static device_method_t ti_gpio_methods[] = { 1053 DEVMETHOD(device_attach, ti_gpio_attach), 1054 DEVMETHOD(device_detach, ti_gpio_detach), 1055 1056 /* GPIO protocol */ 1057 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus), 1058 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 1059 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 1060 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 1061 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 1062 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 1063 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 1064 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 1065 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 1066 1067 /* Interrupt controller interface */ 1068 DEVMETHOD(pic_disable_intr, ti_gpio_pic_disable_intr), 1069 DEVMETHOD(pic_enable_intr, ti_gpio_pic_enable_intr), 1070 DEVMETHOD(pic_map_intr, ti_gpio_pic_map_intr), 1071 DEVMETHOD(pic_setup_intr, ti_gpio_pic_setup_intr), 1072 DEVMETHOD(pic_teardown_intr, ti_gpio_pic_teardown_intr), 1073 DEVMETHOD(pic_post_filter, ti_gpio_pic_post_filter), 1074 DEVMETHOD(pic_post_ithread, ti_gpio_pic_post_ithread), 1075 DEVMETHOD(pic_pre_ithread, ti_gpio_pic_pre_ithread), 1076 1077 /* ofw_bus interface */ 1078 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 1079 1080 {0, 0}, 1081 }; 1082 1083 driver_t ti_gpio_driver = { 1084 "gpio", 1085 ti_gpio_methods, 1086 sizeof(struct ti_gpio_softc), 1087 }; 1088