1 /*- 2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /** 29 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code 30 * here uses 0-5. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/proc.h> 45 #include <sys/rman.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/gpio.h> 49 #include <sys/interrupt.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 #include <machine/resource.h> 54 55 #include <arm/ti/ti_cpuid.h> 56 #include <arm/ti/ti_gpio.h> 57 #include <arm/ti/ti_scm.h> 58 #include <arm/ti/ti_prcm.h> 59 #include <arm/ti/ti_hwmods.h> 60 61 #include <dev/fdt/fdt_common.h> 62 #include <dev/gpio/gpiobusvar.h> 63 #include <dev/ofw/openfirm.h> 64 #include <dev/ofw/ofw_bus.h> 65 #include <dev/ofw/ofw_bus_subr.h> 66 67 #include "gpio_if.h" 68 #include "ti_gpio_if.h" 69 #ifdef INTRNG 70 #include "pic_if.h" 71 #endif 72 73 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X) 74 #error "Unknown SoC" 75 #endif 76 77 /* Register definitions */ 78 #define TI_GPIO_REVISION 0x0000 79 #define TI_GPIO_SYSCONFIG 0x0010 80 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024 81 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028 82 #define TI_GPIO_IRQSTATUS_0 0x002C /* writing a 0 has no effect */ 83 #define TI_GPIO_IRQSTATUS_1 0x0030 /* writing a 0 has no effect */ 84 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 /* writing a 0 has no effect */ 85 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 /* writing a 0 has no effect */ 86 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C /* writing a 0 has no effect */ 87 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 /* writing a 0 has no effect */ 88 #define TI_GPIO_IRQWAKEN_0 0x0044 89 #define TI_GPIO_IRQWAKEN_1 0x0048 90 #define TI_GPIO_SYSSTATUS 0x0114 91 #define TI_GPIO_IRQSTATUS1 0x0118 92 #define TI_GPIO_IRQENABLE1 0x011C 93 #define TI_GPIO_WAKEUPENABLE 0x0120 94 #define TI_GPIO_IRQSTATUS2 0x0128 95 #define TI_GPIO_IRQENABLE2 0x012C 96 #define TI_GPIO_CTRL 0x0130 97 #define TI_GPIO_OE 0x0134 98 #define TI_GPIO_DATAIN 0x0138 99 #define TI_GPIO_DATAOUT 0x013C 100 #define TI_GPIO_LEVELDETECT0 0x0140 /* RW register */ 101 #define TI_GPIO_LEVELDETECT1 0x0144 /* RW register */ 102 #define TI_GPIO_RISINGDETECT 0x0148 /* RW register */ 103 #define TI_GPIO_FALLINGDETECT 0x014C /* RW register */ 104 #define TI_GPIO_DEBOUNCENABLE 0x0150 105 #define TI_GPIO_DEBOUNCINGTIME 0x0154 106 #define TI_GPIO_CLEARWKUPENA 0x0180 107 #define TI_GPIO_SETWKUENA 0x0184 108 #define TI_GPIO_CLEARDATAOUT 0x0190 109 #define TI_GPIO_SETDATAOUT 0x0194 110 111 /* Other SoC Specific definitions */ 112 #define OMAP4_FIRST_GPIO_BANK 1 113 #define OMAP4_INTR_PER_BANK 1 114 #define OMAP4_GPIO_REV 0x50600801 115 #define AM335X_FIRST_GPIO_BANK 0 116 #define AM335X_INTR_PER_BANK 2 117 #define AM335X_GPIO_REV 0x50600801 118 #define PINS_PER_BANK 32 119 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK)) 120 121 static int ti_gpio_intr(void *arg); 122 static int ti_gpio_detach(device_t); 123 124 #ifdef INTRNG 125 static int ti_gpio_pic_attach(struct ti_gpio_softc *sc); 126 static int ti_gpio_pic_detach(struct ti_gpio_softc *sc); 127 #endif 128 129 static u_int 130 ti_first_gpio_bank(void) 131 { 132 switch(ti_chip()) { 133 #ifdef SOC_OMAP4 134 case CHIP_OMAP_4: 135 return (OMAP4_FIRST_GPIO_BANK); 136 #endif 137 #ifdef SOC_TI_AM335X 138 case CHIP_AM335X: 139 return (AM335X_FIRST_GPIO_BANK); 140 #endif 141 } 142 return (0); 143 } 144 145 static uint32_t 146 ti_gpio_rev(void) 147 { 148 switch(ti_chip()) { 149 #ifdef SOC_OMAP4 150 case CHIP_OMAP_4: 151 return (OMAP4_GPIO_REV); 152 #endif 153 #ifdef SOC_TI_AM335X 154 case CHIP_AM335X: 155 return (AM335X_GPIO_REV); 156 #endif 157 } 158 return (0); 159 } 160 161 /** 162 * Macros for driver mutex locking 163 */ 164 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 165 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 166 #define TI_GPIO_LOCK_INIT(_sc) \ 167 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 168 "ti_gpio", MTX_SPIN) 169 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 170 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 171 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 172 173 /** 174 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers 175 * @sc: GPIO device context 176 * @bank: The bank to read from 177 * @off: The offset of a register from the GPIO register address range 178 * 179 * 180 * RETURNS: 181 * 32-bit value read from the register. 182 */ 183 static inline uint32_t 184 ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off) 185 { 186 return (bus_read_4(sc->sc_mem_res, off)); 187 } 188 189 /** 190 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers 191 * @sc: GPIO device context 192 * @bank: The bank to write to 193 * @off: The offset of a register from the GPIO register address range 194 * @val: The value to write into the register 195 * 196 * RETURNS: 197 * nothing 198 */ 199 static inline void 200 ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off, 201 uint32_t val) 202 { 203 bus_write_4(sc->sc_mem_res, off, val); 204 } 205 206 static inline void 207 ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask) 208 { 209 210 /* We clear both set of registers. */ 211 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask); 212 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask); 213 } 214 215 static inline void 216 ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask) 217 { 218 219 /* 220 * On OMAP4 we unmask only the MPU interrupt and on AM335x we 221 * also activate only the first interrupt. 222 */ 223 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask); 224 } 225 226 static inline void 227 ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask) 228 { 229 230 /* 231 * Acknowledge the interrupt on both registers even if we use only 232 * the first one. 233 */ 234 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask); 235 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask); 236 } 237 238 static inline uint32_t 239 ti_gpio_intr_status(struct ti_gpio_softc *sc) 240 { 241 uint32_t reg; 242 243 /* Get the status from both registers. */ 244 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0); 245 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1); 246 247 return (reg); 248 } 249 250 static device_t 251 ti_gpio_get_bus(device_t dev) 252 { 253 struct ti_gpio_softc *sc; 254 255 sc = device_get_softc(dev); 256 257 return (sc->sc_busdev); 258 } 259 260 /** 261 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 262 * @dev: gpio device handle 263 * @maxpin: pointer to a value that upon return will contain the maximum number 264 * of pins in the device. 265 * 266 * 267 * LOCKING: 268 * No locking required, returns static data. 269 * 270 * RETURNS: 271 * Returns 0 on success otherwise an error code 272 */ 273 static int 274 ti_gpio_pin_max(device_t dev, int *maxpin) 275 { 276 277 *maxpin = PINS_PER_BANK - 1; 278 279 return (0); 280 } 281 282 static int 283 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin) 284 { 285 286 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL) 287 return (EINVAL); 288 289 return (0); 290 } 291 292 /** 293 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin 294 * @dev: gpio device handle 295 * @pin: the number of the pin 296 * @caps: pointer to a value that upon return will contain the capabilities 297 * 298 * Currently all pins have the same capability, notably: 299 * - GPIO_PIN_INPUT 300 * - GPIO_PIN_OUTPUT 301 * - GPIO_PIN_PULLUP 302 * - GPIO_PIN_PULLDOWN 303 * 304 * LOCKING: 305 * No locking required, returns static data. 306 * 307 * RETURNS: 308 * Returns 0 on success otherwise an error code 309 */ 310 static int 311 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 312 { 313 struct ti_gpio_softc *sc; 314 315 sc = device_get_softc(dev); 316 if (ti_gpio_valid_pin(sc, pin) != 0) 317 return (EINVAL); 318 319 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP | 320 GPIO_PIN_PULLDOWN); 321 322 return (0); 323 } 324 325 /** 326 * ti_gpio_pin_getflags - Gets the current flags of a given pin 327 * @dev: gpio device handle 328 * @pin: the number of the pin 329 * @flags: upon return will contain the current flags of the pin 330 * 331 * Reads the current flags of a given pin, here we actually read the H/W 332 * registers to determine the flags, rather than storing the value in the 333 * setflags call. 334 * 335 * LOCKING: 336 * Internally locks the context 337 * 338 * RETURNS: 339 * Returns 0 on success otherwise an error code 340 */ 341 static int 342 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 343 { 344 struct ti_gpio_softc *sc; 345 346 sc = device_get_softc(dev); 347 if (ti_gpio_valid_pin(sc, pin) != 0) 348 return (EINVAL); 349 350 /* Get the current pin state */ 351 TI_GPIO_LOCK(sc); 352 TI_GPIO_GET_FLAGS(dev, pin, flags); 353 TI_GPIO_UNLOCK(sc); 354 355 return (0); 356 } 357 358 /** 359 * ti_gpio_pin_getname - Gets the name of a given pin 360 * @dev: gpio device handle 361 * @pin: the number of the pin 362 * @name: buffer to put the name in 363 * 364 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 365 * of the pin. 366 * 367 * LOCKING: 368 * No locking required, returns static data. 369 * 370 * RETURNS: 371 * Returns 0 on success otherwise an error code 372 */ 373 static int 374 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 375 { 376 struct ti_gpio_softc *sc; 377 378 sc = device_get_softc(dev); 379 if (ti_gpio_valid_pin(sc, pin) != 0) 380 return (EINVAL); 381 382 /* Set a very simple name */ 383 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 384 name[GPIOMAXNAME - 1] = '\0'; 385 386 return (0); 387 } 388 389 /** 390 * ti_gpio_pin_setflags - Sets the flags for a given pin 391 * @dev: gpio device handle 392 * @pin: the number of the pin 393 * @flags: the flags to set 394 * 395 * The flags of the pin correspond to things like input/output mode, pull-ups, 396 * pull-downs, etc. This driver doesn't support all flags, only the following: 397 * - GPIO_PIN_INPUT 398 * - GPIO_PIN_OUTPUT 399 * - GPIO_PIN_PULLUP 400 * - GPIO_PIN_PULLDOWN 401 * 402 * LOCKING: 403 * Internally locks the context 404 * 405 * RETURNS: 406 * Returns 0 on success otherwise an error code 407 */ 408 static int 409 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 410 { 411 struct ti_gpio_softc *sc; 412 uint32_t oe; 413 414 sc = device_get_softc(dev); 415 if (ti_gpio_valid_pin(sc, pin) != 0) 416 return (EINVAL); 417 418 /* Set the GPIO mode and state */ 419 TI_GPIO_LOCK(sc); 420 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) { 421 TI_GPIO_UNLOCK(sc); 422 return (EINVAL); 423 } 424 425 /* If configuring as an output set the "output enable" bit */ 426 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 427 if (flags & GPIO_PIN_INPUT) 428 oe |= TI_GPIO_MASK(pin); 429 else 430 oe &= ~TI_GPIO_MASK(pin); 431 ti_gpio_write_4(sc, TI_GPIO_OE, oe); 432 TI_GPIO_UNLOCK(sc); 433 434 return (0); 435 } 436 437 /** 438 * ti_gpio_pin_set - Sets the current level on a GPIO pin 439 * @dev: gpio device handle 440 * @pin: the number of the pin 441 * @value: non-zero value will drive the pin high, otherwise the pin is 442 * driven low. 443 * 444 * 445 * LOCKING: 446 * Internally locks the context 447 * 448 * RETURNS: 449 * Returns 0 on success otherwise a error code 450 */ 451 static int 452 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 453 { 454 struct ti_gpio_softc *sc; 455 uint32_t reg; 456 457 sc = device_get_softc(dev); 458 if (ti_gpio_valid_pin(sc, pin) != 0) 459 return (EINVAL); 460 461 TI_GPIO_LOCK(sc); 462 if (value == GPIO_PIN_LOW) 463 reg = TI_GPIO_CLEARDATAOUT; 464 else 465 reg = TI_GPIO_SETDATAOUT; 466 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 467 TI_GPIO_UNLOCK(sc); 468 469 return (0); 470 } 471 472 /** 473 * ti_gpio_pin_get - Gets the current level on a GPIO pin 474 * @dev: gpio device handle 475 * @pin: the number of the pin 476 * @value: pointer to a value that upond return will contain the pin value 477 * 478 * The pin must be configured as an input pin beforehand, otherwise this 479 * function will fail. 480 * 481 * LOCKING: 482 * Internally locks the context 483 * 484 * RETURNS: 485 * Returns 0 on success otherwise a error code 486 */ 487 static int 488 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 489 { 490 struct ti_gpio_softc *sc; 491 uint32_t oe, reg, val; 492 493 sc = device_get_softc(dev); 494 if (ti_gpio_valid_pin(sc, pin) != 0) 495 return (EINVAL); 496 497 /* 498 * Return data from output latch when set as output and from the 499 * input register otherwise. 500 */ 501 TI_GPIO_LOCK(sc); 502 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 503 if (oe & TI_GPIO_MASK(pin)) 504 reg = TI_GPIO_DATAIN; 505 else 506 reg = TI_GPIO_DATAOUT; 507 val = ti_gpio_read_4(sc, reg); 508 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0; 509 TI_GPIO_UNLOCK(sc); 510 511 return (0); 512 } 513 514 /** 515 * ti_gpio_pin_toggle - Toggles a given GPIO pin 516 * @dev: gpio device handle 517 * @pin: the number of the pin 518 * 519 * 520 * LOCKING: 521 * Internally locks the context 522 * 523 * RETURNS: 524 * Returns 0 on success otherwise a error code 525 */ 526 static int 527 ti_gpio_pin_toggle(device_t dev, uint32_t pin) 528 { 529 struct ti_gpio_softc *sc; 530 uint32_t reg, val; 531 532 sc = device_get_softc(dev); 533 if (ti_gpio_valid_pin(sc, pin) != 0) 534 return (EINVAL); 535 536 /* Toggle the pin */ 537 TI_GPIO_LOCK(sc); 538 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT); 539 if (val & TI_GPIO_MASK(pin)) 540 reg = TI_GPIO_CLEARDATAOUT; 541 else 542 reg = TI_GPIO_SETDATAOUT; 543 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 544 TI_GPIO_UNLOCK(sc); 545 546 return (0); 547 } 548 549 #ifndef INTRNG 550 /** 551 * ti_gpio_intr - ISR for all GPIO modules 552 * @arg: the soft context pointer 553 * 554 * LOCKING: 555 * Internally locks the context 556 * 557 */ 558 static int 559 ti_gpio_intr(void *arg) 560 { 561 int bank_last, irq; 562 struct intr_event *event; 563 struct ti_gpio_softc *sc; 564 uint32_t reg; 565 566 sc = (struct ti_gpio_softc *)arg; 567 bank_last = -1; 568 reg = 0; /* squelch bogus gcc warning */ 569 reg = ti_gpio_intr_status(sc); 570 for (irq = 0; irq < sc->sc_maxpin; irq++) { 571 if ((reg & TI_GPIO_MASK(irq)) == 0) 572 continue; 573 event = sc->sc_events[irq]; 574 if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers)) 575 intr_event_handle(event, NULL); 576 else 577 device_printf(sc->sc_dev, "Stray IRQ %d\n", irq); 578 /* Ack the IRQ Status bit. */ 579 ti_gpio_intr_ack(sc, TI_GPIO_MASK(irq)); 580 } 581 582 return (FILTER_HANDLED); 583 } 584 #endif 585 586 static int 587 ti_gpio_bank_init(device_t dev) 588 { 589 int pin; 590 struct ti_gpio_softc *sc; 591 uint32_t flags, reg_oe, reg_set, rev; 592 clk_ident_t clk; 593 594 sc = device_get_softc(dev); 595 596 /* Enable the interface and functional clocks for the module. */ 597 clk = ti_hwmods_get_clock(dev); 598 if (clk == INVALID_CLK_IDENT) { 599 device_printf(dev, "failed to get device id based on ti,hwmods\n"); 600 return (EINVAL); 601 } 602 603 sc->sc_bank = clk - GPIO1_CLK + ti_first_gpio_bank(); 604 ti_prcm_clk_enable(clk); 605 606 /* 607 * Read the revision number of the module. TI don't publish the 608 * actual revision numbers, so instead the values have been 609 * determined by experimentation. 610 */ 611 rev = ti_gpio_read_4(sc, TI_GPIO_REVISION); 612 613 /* Check the revision. */ 614 if (rev != ti_gpio_rev()) { 615 device_printf(dev, "Warning: could not determine the revision " 616 "of GPIO module (revision:0x%08x)\n", rev); 617 return (EINVAL); 618 } 619 620 /* Disable interrupts for all pins. */ 621 ti_gpio_intr_clr(sc, 0xffffffff); 622 623 /* Init OE register based on pads configuration. */ 624 reg_oe = 0xffffffff; 625 reg_set = 0; 626 for (pin = 0; pin < PINS_PER_BANK; pin++) { 627 TI_GPIO_GET_FLAGS(dev, pin, &flags); 628 if (flags & GPIO_PIN_OUTPUT) { 629 reg_oe &= ~(1UL << pin); 630 if (flags & GPIO_PIN_PULLUP) 631 reg_set |= (1UL << pin); 632 } 633 } 634 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe); 635 if (reg_set) 636 ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set); 637 638 return (0); 639 } 640 641 /** 642 * ti_gpio_attach - attach function for the driver 643 * @dev: gpio device handle 644 * 645 * Allocates and sets up the driver context for all GPIO banks. This function 646 * expects the memory ranges and IRQs to already be allocated to the driver. 647 * 648 * LOCKING: 649 * None 650 * 651 * RETURNS: 652 * Always returns 0 653 */ 654 static int 655 ti_gpio_attach(device_t dev) 656 { 657 struct ti_gpio_softc *sc; 658 #ifndef INTRNG 659 unsigned int i; 660 #endif 661 int err; 662 663 sc = device_get_softc(dev); 664 sc->sc_dev = dev; 665 TI_GPIO_LOCK_INIT(sc); 666 ti_gpio_pin_max(dev, &sc->sc_maxpin); 667 sc->sc_maxpin++; 668 669 sc->sc_mem_rid = 0; 670 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 671 &sc->sc_mem_rid, RF_ACTIVE); 672 if (!sc->sc_mem_res) { 673 device_printf(dev, "Error: could not allocate mem resources\n"); 674 ti_gpio_detach(dev); 675 return (ENXIO); 676 } 677 678 sc->sc_irq_rid = 0; 679 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 680 &sc->sc_irq_rid, RF_ACTIVE); 681 if (!sc->sc_irq_res) { 682 device_printf(dev, "Error: could not allocate irq resources\n"); 683 ti_gpio_detach(dev); 684 return (ENXIO); 685 } 686 687 /* 688 * Register our interrupt filter for each of the IRQ resources. 689 */ 690 if (bus_setup_intr(dev, sc->sc_irq_res, 691 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc, 692 &sc->sc_irq_hdl) != 0) { 693 device_printf(dev, 694 "WARNING: unable to register interrupt filter\n"); 695 ti_gpio_detach(dev); 696 return (ENXIO); 697 } 698 699 #ifdef INTRNG 700 if (ti_gpio_pic_attach(sc) != 0) { 701 device_printf(dev, "WARNING: unable to attach PIC\n"); 702 ti_gpio_detach(dev); 703 return (ENXIO); 704 } 705 #else 706 /* 707 * Initialize the interrupt settings. The default is active-low 708 * interrupts. 709 */ 710 sc->sc_irq_trigger = malloc( 711 sizeof(*sc->sc_irq_trigger) * sc->sc_maxpin, 712 M_DEVBUF, M_WAITOK | M_ZERO); 713 sc->sc_irq_polarity = malloc( 714 sizeof(*sc->sc_irq_polarity) * sc->sc_maxpin, 715 M_DEVBUF, M_WAITOK | M_ZERO); 716 for (i = 0; i < sc->sc_maxpin; i++) { 717 sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL; 718 sc->sc_irq_polarity[i] = INTR_POLARITY_LOW; 719 } 720 721 sc->sc_events = malloc(sizeof(struct intr_event *) * sc->sc_maxpin, 722 M_DEVBUF, M_WAITOK | M_ZERO); 723 724 sc->sc_mask_args = malloc(sizeof(struct ti_gpio_mask_arg) * sc->sc_maxpin, 725 M_DEVBUF, M_WAITOK | M_ZERO); 726 #endif 727 /* We need to go through each block and ensure the clocks are running and 728 * the module is enabled. It might be better to do this only when the 729 * pins are configured which would result in less power used if the GPIO 730 * pins weren't used ... 731 */ 732 if (sc->sc_mem_res != NULL) { 733 /* Initialize the GPIO module. */ 734 err = ti_gpio_bank_init(dev); 735 if (err != 0) { 736 ti_gpio_detach(dev); 737 return (err); 738 } 739 } 740 741 sc->sc_busdev = gpiobus_attach_bus(dev); 742 if (sc->sc_busdev == NULL) { 743 ti_gpio_detach(dev); 744 return (ENXIO); 745 } 746 747 return (0); 748 } 749 750 /** 751 * ti_gpio_detach - detach function for the driver 752 * @dev: scm device handle 753 * 754 * Allocates and sets up the driver context, this simply entails creating a 755 * bus mappings for the SCM register set. 756 * 757 * LOCKING: 758 * None 759 * 760 * RETURNS: 761 * Always returns 0 762 */ 763 static int 764 ti_gpio_detach(device_t dev) 765 { 766 struct ti_gpio_softc *sc = device_get_softc(dev); 767 768 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 769 770 /* Disable all interrupts */ 771 if (sc->sc_mem_res != NULL) 772 ti_gpio_intr_clr(sc, 0xffffffff); 773 gpiobus_detach_bus(dev); 774 #ifdef INTRNG 775 if (sc->sc_isrcs != NULL) 776 ti_gpio_pic_detach(sc); 777 #else 778 if (sc->sc_events) 779 free(sc->sc_events, M_DEVBUF); 780 if (sc->sc_mask_args) 781 free(sc->sc_mask_args, M_DEVBUF); 782 if (sc->sc_irq_polarity) 783 free(sc->sc_irq_polarity, M_DEVBUF); 784 if (sc->sc_irq_trigger) 785 free(sc->sc_irq_trigger, M_DEVBUF); 786 #endif 787 /* Release the memory and IRQ resources. */ 788 if (sc->sc_irq_hdl) { 789 bus_teardown_intr(dev, sc->sc_irq_res, 790 sc->sc_irq_hdl); 791 } 792 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 793 sc->sc_irq_res); 794 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 795 sc->sc_mem_res); 796 TI_GPIO_LOCK_DESTROY(sc); 797 798 return (0); 799 } 800 801 #ifdef INTRNG 802 static inline void 803 ti_gpio_rwreg_set(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask) 804 { 805 806 ti_gpio_write_4(sc, reg, ti_gpio_read_4(sc, reg) | mask); 807 } 808 809 static inline void 810 ti_gpio_rwreg_clr(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask) 811 { 812 813 ti_gpio_write_4(sc, reg, ti_gpio_read_4(sc, reg) & ~mask); 814 } 815 816 static inline void 817 ti_gpio_isrc_mask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 818 { 819 820 /* Writing a 0 has no effect. */ 821 ti_gpio_intr_clr(sc, tgi->tgi_mask); 822 } 823 824 static inline void 825 ti_gpio_isrc_unmask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 826 { 827 828 /* Writing a 0 has no effect. */ 829 ti_gpio_intr_set(sc, tgi->tgi_mask); 830 } 831 832 static inline void 833 ti_gpio_isrc_eoi(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 834 { 835 836 /* Writing a 0 has no effect. */ 837 ti_gpio_intr_ack(sc, tgi->tgi_mask); 838 } 839 840 static inline bool 841 ti_gpio_isrc_is_level(struct ti_gpio_irqsrc *tgi) 842 { 843 844 return (tgi->tgi_cfgreg == TI_GPIO_LEVELDETECT0 || 845 tgi->tgi_cfgreg == TI_GPIO_LEVELDETECT1); 846 } 847 848 static int 849 ti_gpio_intr(void *arg) 850 { 851 u_int irq; 852 uint32_t reg; 853 struct ti_gpio_softc *sc; 854 struct trapframe *tf; 855 struct ti_gpio_irqsrc *tgi; 856 857 sc = (struct ti_gpio_softc *)arg; 858 tf = curthread->td_intr_frame; 859 860 reg = ti_gpio_intr_status(sc); 861 for (irq = 0; irq < sc->sc_maxpin; irq++) { 862 tgi = &sc->sc_isrcs[irq]; 863 if ((reg & tgi->tgi_mask) == 0) 864 continue; 865 if (!ti_gpio_isrc_is_level(tgi)) 866 ti_gpio_isrc_eoi(sc, tgi); 867 if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) { 868 ti_gpio_isrc_mask(sc, tgi); 869 if (ti_gpio_isrc_is_level(tgi)) 870 ti_gpio_isrc_eoi(sc, tgi); 871 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 872 irq); 873 } 874 } 875 return (FILTER_HANDLED); 876 } 877 878 static int 879 ti_gpio_pic_attach(struct ti_gpio_softc *sc) 880 { 881 int error; 882 uint32_t irq; 883 const char *name; 884 885 sc->sc_isrcs = malloc(sizeof(*sc->sc_isrcs) * sc->sc_maxpin, M_DEVBUF, 886 M_WAITOK | M_ZERO); 887 888 name = device_get_nameunit(sc->sc_dev); 889 for (irq = 0; irq < sc->sc_maxpin; irq++) { 890 sc->sc_isrcs[irq].tgi_irq = irq; 891 sc->sc_isrcs[irq].tgi_mask = TI_GPIO_MASK(irq); 892 sc->sc_isrcs[irq].tgi_cfgreg = 0; 893 894 error = intr_isrc_register(&sc->sc_isrcs[irq].tgi_isrc, 895 sc->sc_dev, 0, "%s,%u", name, irq); 896 if (error != 0) 897 return (error); /* XXX deregister ISRCs */ 898 } 899 return (intr_pic_register(sc->sc_dev, 900 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev)))); 901 } 902 903 static int 904 ti_gpio_pic_detach(struct ti_gpio_softc *sc) 905 { 906 907 /* 908 * There has not been established any procedure yet 909 * how to detach PIC from living system correctly. 910 */ 911 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 912 return (EBUSY); 913 } 914 915 static void 916 ti_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 917 { 918 struct ti_gpio_softc *sc = device_get_softc(dev); 919 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 920 921 ti_gpio_isrc_mask(sc, tgi); 922 } 923 924 static void 925 ti_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 926 { 927 struct ti_gpio_softc *sc = device_get_softc(dev); 928 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 929 930 arm_irq_memory_barrier(tgi->tgi_irq); 931 ti_gpio_isrc_unmask(sc, tgi); 932 } 933 934 static int 935 ti_gpio_pic_map_fdt(struct ti_gpio_softc *sc, u_int ncells, pcell_t *cells, 936 u_int *irqp, uint32_t *regp) 937 { 938 uint32_t reg; 939 940 /* 941 * The first cell is the interrupt number. 942 * The second cell is used to specify flags: 943 * bits[3:0] trigger type and level flags: 944 * 1 = low-to-high edge triggered. 945 * 2 = high-to-low edge triggered. 946 * 4 = active high level-sensitive. 947 * 8 = active low level-sensitive. 948 */ 949 if (ncells != 2 || cells[0] >= sc->sc_maxpin) 950 return (EINVAL); 951 952 /* 953 * All interrupt types could be set for an interrupt at one moment. 954 * At least, the combination of 'low-to-high' and 'high-to-low' edge 955 * triggered interrupt types can make a sense. However, no combo is 956 * supported now. 957 */ 958 if (cells[1] == 1) 959 reg = TI_GPIO_RISINGDETECT; 960 else if (cells[1] == 2) 961 reg = TI_GPIO_FALLINGDETECT; 962 else if (cells[1] == 4) 963 reg = TI_GPIO_LEVELDETECT1; 964 else if (cells[1] == 8) 965 reg = TI_GPIO_LEVELDETECT0; 966 else 967 return (EINVAL); 968 969 *irqp = cells[0]; 970 if (regp != NULL) 971 *regp = reg; 972 return (0); 973 } 974 975 static int 976 ti_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 977 struct intr_irqsrc **isrcp) 978 { 979 int error; 980 u_int irq; 981 struct ti_gpio_softc *sc; 982 983 if (data->type != INTR_MAP_DATA_FDT) 984 return (ENOTSUP); 985 986 sc = device_get_softc(dev); 987 error = ti_gpio_pic_map_fdt(sc, data->fdt.ncells, data->fdt.cells, &irq, 988 NULL); 989 if (error == 0) 990 *isrcp = &sc->sc_isrcs[irq].tgi_isrc; 991 return (error); 992 } 993 994 static void 995 ti_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 996 { 997 struct ti_gpio_softc *sc = device_get_softc(dev); 998 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 999 1000 if (ti_gpio_isrc_is_level(tgi)) 1001 ti_gpio_isrc_eoi(sc, tgi); 1002 } 1003 1004 static void 1005 ti_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 1006 { 1007 1008 ti_gpio_pic_enable_intr(dev, isrc); 1009 } 1010 1011 static void 1012 ti_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 1013 { 1014 struct ti_gpio_softc *sc = device_get_softc(dev); 1015 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1016 1017 ti_gpio_isrc_mask(sc, tgi); 1018 if (ti_gpio_isrc_is_level(tgi)) 1019 ti_gpio_isrc_eoi(sc, tgi); 1020 } 1021 1022 static int 1023 ti_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1024 struct resource *res, struct intr_map_data *data) 1025 { 1026 u_int irq; 1027 uint32_t cfgreg; 1028 struct ti_gpio_softc *sc; 1029 struct ti_gpio_irqsrc *tgi; 1030 1031 if (data == NULL || data->type != INTR_MAP_DATA_FDT) 1032 return (ENOTSUP); 1033 1034 sc = device_get_softc(dev); 1035 tgi = (struct ti_gpio_irqsrc *)isrc; 1036 1037 /* Get and check config for an interrupt. */ 1038 if (ti_gpio_pic_map_fdt(sc, data->fdt.ncells, data->fdt.cells, &irq, 1039 &cfgreg) != 0 || tgi->tgi_irq != irq) 1040 return (EINVAL); 1041 1042 /* 1043 * If this is a setup for another handler, 1044 * only check that its configuration match. 1045 */ 1046 if (isrc->isrc_handlers != 0) 1047 return (tgi->tgi_cfgreg == cfgreg ? 0 : EINVAL); 1048 1049 TI_GPIO_LOCK(sc); 1050 ti_gpio_rwreg_clr(sc, TI_GPIO_RISINGDETECT, tgi->tgi_mask); 1051 ti_gpio_rwreg_clr(sc, TI_GPIO_FALLINGDETECT, tgi->tgi_mask); 1052 ti_gpio_rwreg_clr(sc, TI_GPIO_LEVELDETECT1, tgi->tgi_mask); 1053 ti_gpio_rwreg_clr(sc, TI_GPIO_LEVELDETECT0, tgi->tgi_mask); 1054 tgi->tgi_cfgreg = cfgreg; 1055 ti_gpio_rwreg_set(sc, cfgreg, tgi->tgi_mask); 1056 TI_GPIO_UNLOCK(sc); 1057 return (0); 1058 } 1059 1060 static int 1061 ti_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1062 struct resource *res, struct intr_map_data *data) 1063 { 1064 struct ti_gpio_softc *sc = device_get_softc(dev); 1065 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1066 1067 if (isrc->isrc_handlers == 0) { 1068 TI_GPIO_LOCK(sc); 1069 ti_gpio_rwreg_clr(sc, tgi->tgi_cfgreg, tgi->tgi_mask); 1070 tgi->tgi_cfgreg = 0; 1071 TI_GPIO_UNLOCK(sc); 1072 } 1073 return (0); 1074 } 1075 1076 #else 1077 static uint32_t 1078 ti_gpio_intr_reg(struct ti_gpio_softc *sc, int irq) 1079 { 1080 1081 if (ti_gpio_valid_pin(sc, irq) != 0) 1082 return (0); 1083 1084 if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) { 1085 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 1086 return (TI_GPIO_LEVELDETECT0); 1087 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 1088 return (TI_GPIO_LEVELDETECT1); 1089 } else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) { 1090 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 1091 return (TI_GPIO_FALLINGDETECT); 1092 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 1093 return (TI_GPIO_RISINGDETECT); 1094 } 1095 1096 return (0); 1097 } 1098 1099 static void 1100 ti_gpio_mask_irq_internal(struct ti_gpio_softc *sc, int irq) 1101 { 1102 uint32_t reg, val; 1103 1104 if (ti_gpio_valid_pin(sc, irq) != 0) 1105 return; 1106 1107 TI_GPIO_LOCK(sc); 1108 ti_gpio_intr_clr(sc, TI_GPIO_MASK(irq)); 1109 reg = ti_gpio_intr_reg(sc, irq); 1110 if (reg != 0) { 1111 val = ti_gpio_read_4(sc, reg); 1112 val &= ~TI_GPIO_MASK(irq); 1113 ti_gpio_write_4(sc, reg, val); 1114 } 1115 TI_GPIO_UNLOCK(sc); 1116 } 1117 1118 static void 1119 ti_gpio_unmask_irq_internal(struct ti_gpio_softc *sc, int irq) 1120 { 1121 uint32_t reg, val; 1122 1123 if (ti_gpio_valid_pin(sc, irq) != 0) 1124 return; 1125 1126 TI_GPIO_LOCK(sc); 1127 reg = ti_gpio_intr_reg(sc, irq); 1128 if (reg != 0) { 1129 val = ti_gpio_read_4(sc, reg); 1130 val |= TI_GPIO_MASK(irq); 1131 ti_gpio_write_4(sc, reg, val); 1132 ti_gpio_intr_set(sc, TI_GPIO_MASK(irq)); 1133 } 1134 TI_GPIO_UNLOCK(sc); 1135 } 1136 1137 static void 1138 ti_gpio_mask_irq(void *source) 1139 { 1140 struct ti_gpio_mask_arg *arg = source; 1141 1142 ti_gpio_mask_irq_internal(arg->softc, arg->pin); 1143 } 1144 1145 static void 1146 ti_gpio_unmask_irq(void *source) 1147 { 1148 struct ti_gpio_mask_arg *arg = source; 1149 1150 ti_gpio_unmask_irq_internal(arg->softc, arg->pin); 1151 } 1152 1153 static int 1154 ti_gpio_activate_resource(device_t dev, device_t child, int type, int rid, 1155 struct resource *res) 1156 { 1157 struct ti_gpio_mask_arg mask_arg; 1158 1159 if (type != SYS_RES_IRQ) 1160 return (ENXIO); 1161 1162 /* Unmask the interrupt. */ 1163 mask_arg.pin = rman_get_start(res); 1164 mask_arg.softc = device_get_softc(dev); 1165 1166 ti_gpio_unmask_irq((void *)&mask_arg); 1167 1168 return (0); 1169 } 1170 1171 static int 1172 ti_gpio_deactivate_resource(device_t dev, device_t child, int type, int rid, 1173 struct resource *res) 1174 { 1175 int pin; 1176 1177 if (type != SYS_RES_IRQ) 1178 return (ENXIO); 1179 1180 /* Mask the interrupt. */ 1181 pin = rman_get_start(res); 1182 ti_gpio_mask_irq((void *)(uintptr_t)pin); 1183 1184 return (0); 1185 } 1186 1187 static int 1188 ti_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig, 1189 enum intr_polarity pol) 1190 { 1191 struct ti_gpio_softc *sc; 1192 uint32_t oldreg, reg, val; 1193 1194 sc = device_get_softc(dev); 1195 if (ti_gpio_valid_pin(sc, irq) != 0) 1196 return (EINVAL); 1197 1198 /* There is no standard trigger or polarity. */ 1199 if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM) 1200 return (EINVAL); 1201 1202 TI_GPIO_LOCK(sc); 1203 /* 1204 * TRM recommends add the new event before remove the old one to 1205 * avoid losing interrupts. 1206 */ 1207 oldreg = ti_gpio_intr_reg(sc, irq); 1208 sc->sc_irq_trigger[irq] = trig; 1209 sc->sc_irq_polarity[irq] = pol; 1210 reg = ti_gpio_intr_reg(sc, irq); 1211 if (reg != 0) { 1212 /* Apply the new settings. */ 1213 val = ti_gpio_read_4(sc, reg); 1214 val |= TI_GPIO_MASK(irq); 1215 ti_gpio_write_4(sc, reg, val); 1216 } 1217 if (reg != oldreg && oldreg != 0) { 1218 /* Remove the old settings. */ 1219 val = ti_gpio_read_4(sc, oldreg); 1220 val &= ~TI_GPIO_MASK(irq); 1221 ti_gpio_write_4(sc, oldreg, val); 1222 } 1223 TI_GPIO_UNLOCK(sc); 1224 1225 return (0); 1226 } 1227 1228 static int 1229 ti_gpio_setup_intr(device_t dev, device_t child, struct resource *ires, 1230 int flags, driver_filter_t *filt, driver_intr_t *handler, 1231 void *arg, void **cookiep) 1232 { 1233 struct ti_gpio_softc *sc; 1234 struct intr_event *event; 1235 int pin, error; 1236 1237 sc = device_get_softc(dev); 1238 pin = rman_get_start(ires); 1239 if (ti_gpio_valid_pin(sc, pin) != 0) 1240 panic("%s: bad pin %d", __func__, pin); 1241 1242 event = sc->sc_events[pin]; 1243 if (event == NULL) { 1244 sc->sc_mask_args[pin].softc = sc; 1245 sc->sc_mask_args[pin].pin = pin; 1246 error = intr_event_create(&event, (void *)&sc->sc_mask_args[pin], 0, 1247 pin, ti_gpio_mask_irq, ti_gpio_unmask_irq, NULL, NULL, 1248 "gpio%d pin%d:", device_get_unit(dev), pin); 1249 if (error != 0) 1250 return (error); 1251 sc->sc_events[pin] = event; 1252 } 1253 intr_event_add_handler(event, device_get_nameunit(child), filt, 1254 handler, arg, intr_priority(flags), flags, cookiep); 1255 1256 return (0); 1257 } 1258 1259 static int 1260 ti_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires, 1261 void *cookie) 1262 { 1263 struct ti_gpio_softc *sc; 1264 int pin, err; 1265 1266 sc = device_get_softc(dev); 1267 pin = rman_get_start(ires); 1268 if (ti_gpio_valid_pin(sc, pin) != 0) 1269 panic("%s: bad pin %d", __func__, pin); 1270 if (sc->sc_events[pin] == NULL) 1271 panic("Trying to teardown unoccupied IRQ"); 1272 err = intr_event_remove_handler(cookie); 1273 if (!err) 1274 sc->sc_events[pin] = NULL; 1275 1276 return (err); 1277 } 1278 #endif 1279 1280 static phandle_t 1281 ti_gpio_get_node(device_t bus, device_t dev) 1282 { 1283 1284 /* We only have one child, the GPIO bus, which needs our own node. */ 1285 return (ofw_bus_get_node(bus)); 1286 } 1287 1288 static device_method_t ti_gpio_methods[] = { 1289 DEVMETHOD(device_attach, ti_gpio_attach), 1290 DEVMETHOD(device_detach, ti_gpio_detach), 1291 1292 /* GPIO protocol */ 1293 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus), 1294 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 1295 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 1296 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 1297 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 1298 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 1299 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 1300 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 1301 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 1302 1303 #ifdef INTRNG 1304 /* Interrupt controller interface */ 1305 DEVMETHOD(pic_disable_intr, ti_gpio_pic_disable_intr), 1306 DEVMETHOD(pic_enable_intr, ti_gpio_pic_enable_intr), 1307 DEVMETHOD(pic_map_intr, ti_gpio_pic_map_intr), 1308 DEVMETHOD(pic_setup_intr, ti_gpio_pic_setup_intr), 1309 DEVMETHOD(pic_teardown_intr, ti_gpio_pic_teardown_intr), 1310 DEVMETHOD(pic_post_filter, ti_gpio_pic_post_filter), 1311 DEVMETHOD(pic_post_ithread, ti_gpio_pic_post_ithread), 1312 DEVMETHOD(pic_pre_ithread, ti_gpio_pic_pre_ithread), 1313 #else 1314 /* Bus interface */ 1315 DEVMETHOD(bus_activate_resource, ti_gpio_activate_resource), 1316 DEVMETHOD(bus_deactivate_resource, ti_gpio_deactivate_resource), 1317 DEVMETHOD(bus_config_intr, ti_gpio_config_intr), 1318 DEVMETHOD(bus_setup_intr, ti_gpio_setup_intr), 1319 DEVMETHOD(bus_teardown_intr, ti_gpio_teardown_intr), 1320 #endif 1321 1322 /* ofw_bus interface */ 1323 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 1324 1325 {0, 0}, 1326 }; 1327 1328 driver_t ti_gpio_driver = { 1329 "gpio", 1330 ti_gpio_methods, 1331 sizeof(struct ti_gpio_softc), 1332 }; 1333