1 /*- 2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /** 29 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code 30 * here uses 0-5. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/rman.h> 43 #include <sys/lock.h> 44 #include <sys/mutex.h> 45 #include <sys/gpio.h> 46 #include <sys/interrupt.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 51 #include <arm/ti/ti_cpuid.h> 52 #include <arm/ti/ti_gpio.h> 53 #include <arm/ti/ti_scm.h> 54 #include <arm/ti/ti_prcm.h> 55 56 #include <dev/fdt/fdt_common.h> 57 #include <dev/ofw/openfirm.h> 58 #include <dev/ofw/ofw_bus.h> 59 #include <dev/ofw/ofw_bus_subr.h> 60 61 #include "gpio_if.h" 62 #include "ti_gpio_if.h" 63 64 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X) 65 #error "Unknown SoC" 66 #endif 67 68 /* Register definitions */ 69 #define TI_GPIO_REVISION 0x0000 70 #define TI_GPIO_SYSCONFIG 0x0010 71 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024 72 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028 73 #define TI_GPIO_IRQSTATUS_0 0x002C 74 #define TI_GPIO_IRQSTATUS_1 0x0030 75 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 76 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 77 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C 78 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 79 #define TI_GPIO_IRQWAKEN_0 0x0044 80 #define TI_GPIO_IRQWAKEN_1 0x0048 81 #define TI_GPIO_SYSSTATUS 0x0114 82 #define TI_GPIO_IRQSTATUS1 0x0118 83 #define TI_GPIO_IRQENABLE1 0x011C 84 #define TI_GPIO_WAKEUPENABLE 0x0120 85 #define TI_GPIO_IRQSTATUS2 0x0128 86 #define TI_GPIO_IRQENABLE2 0x012C 87 #define TI_GPIO_CTRL 0x0130 88 #define TI_GPIO_OE 0x0134 89 #define TI_GPIO_DATAIN 0x0138 90 #define TI_GPIO_DATAOUT 0x013C 91 #define TI_GPIO_LEVELDETECT0 0x0140 92 #define TI_GPIO_LEVELDETECT1 0x0144 93 #define TI_GPIO_RISINGDETECT 0x0148 94 #define TI_GPIO_FALLINGDETECT 0x014C 95 #define TI_GPIO_DEBOUNCENABLE 0x0150 96 #define TI_GPIO_DEBOUNCINGTIME 0x0154 97 #define TI_GPIO_CLEARWKUPENA 0x0180 98 #define TI_GPIO_SETWKUENA 0x0184 99 #define TI_GPIO_CLEARDATAOUT 0x0190 100 #define TI_GPIO_SETDATAOUT 0x0194 101 102 /* Other SoC Specific definitions */ 103 #define OMAP4_MAX_GPIO_BANKS 6 104 #define OMAP4_FIRST_GPIO_BANK 1 105 #define OMAP4_INTR_PER_BANK 1 106 #define OMAP4_GPIO_REV 0x50600801 107 #define AM335X_MAX_GPIO_BANKS 4 108 #define AM335X_FIRST_GPIO_BANK 0 109 #define AM335X_INTR_PER_BANK 2 110 #define AM335X_GPIO_REV 0x50600801 111 #define PINS_PER_BANK 32 112 #define TI_GPIO_BANK(p) ((p) / PINS_PER_BANK) 113 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK)) 114 115 static struct ti_gpio_softc *ti_gpio_sc = NULL; 116 117 static u_int 118 ti_max_gpio_banks(void) 119 { 120 switch(ti_chip()) { 121 #ifdef SOC_OMAP4 122 case CHIP_OMAP_4: 123 return (OMAP4_MAX_GPIO_BANKS); 124 #endif 125 #ifdef SOC_TI_AM335X 126 case CHIP_AM335X: 127 return (AM335X_MAX_GPIO_BANKS); 128 #endif 129 } 130 return (0); 131 } 132 133 static u_int 134 ti_max_gpio_intrs(void) 135 { 136 switch(ti_chip()) { 137 #ifdef SOC_OMAP4 138 case CHIP_OMAP_4: 139 return (OMAP4_MAX_GPIO_BANKS * OMAP4_INTR_PER_BANK); 140 #endif 141 #ifdef SOC_TI_AM335X 142 case CHIP_AM335X: 143 return (AM335X_MAX_GPIO_BANKS * AM335X_INTR_PER_BANK); 144 #endif 145 } 146 return (0); 147 } 148 149 static u_int 150 ti_first_gpio_bank(void) 151 { 152 switch(ti_chip()) { 153 #ifdef SOC_OMAP4 154 case CHIP_OMAP_4: 155 return (OMAP4_FIRST_GPIO_BANK); 156 #endif 157 #ifdef SOC_TI_AM335X 158 case CHIP_AM335X: 159 return (AM335X_FIRST_GPIO_BANK); 160 #endif 161 } 162 return (0); 163 } 164 165 static uint32_t 166 ti_gpio_rev(void) 167 { 168 switch(ti_chip()) { 169 #ifdef SOC_OMAP4 170 case CHIP_OMAP_4: 171 return (OMAP4_GPIO_REV); 172 #endif 173 #ifdef SOC_TI_AM335X 174 case CHIP_AM335X: 175 return (AM335X_GPIO_REV); 176 #endif 177 } 178 return (0); 179 } 180 181 /** 182 * ti_gpio_mem_spec - Resource specification used when allocating resources 183 * ti_gpio_irq_spec - Resource specification used when allocating resources 184 * 185 * This driver module can have up to six independent memory regions, each 186 * region typically controls 32 GPIO pins. 187 * 188 * On OMAP3 and OMAP4 there is only one physical interrupt line per bank, 189 * but there are two set of registers which control the interrupt delivery 190 * to internal subsystems. The first set of registers control the 191 * interrupts delivery to the MPU and the second set control the 192 * interrupts delivery to the DSP. 193 * 194 * On AM335x there are two physical interrupt lines for each GPIO module. 195 * Each interrupt line is controlled by a set of registers. 196 */ 197 static struct resource_spec ti_gpio_mem_spec[] = { 198 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 199 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL }, 200 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL }, 201 { SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL }, 202 #if !defined(SOC_TI_AM335X) 203 { SYS_RES_MEMORY, 4, RF_ACTIVE | RF_OPTIONAL }, 204 { SYS_RES_MEMORY, 5, RF_ACTIVE | RF_OPTIONAL }, 205 #endif 206 { -1, 0, 0 } 207 }; 208 static struct resource_spec ti_gpio_irq_spec[] = { 209 { SYS_RES_IRQ, 0, RF_ACTIVE }, 210 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, 211 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, 212 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, 213 { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL }, 214 { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL }, 215 #if defined(SOC_TI_AM335X) 216 { SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL }, 217 { SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL }, 218 #endif 219 { -1, 0, 0 } 220 }; 221 222 /** 223 * Macros for driver mutex locking 224 */ 225 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 226 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 227 #define TI_GPIO_LOCK_INIT(_sc) \ 228 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 229 "ti_gpio", MTX_SPIN) 230 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 231 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 232 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 233 234 /** 235 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers 236 * @sc: GPIO device context 237 * @bank: The bank to read from 238 * @off: The offset of a register from the GPIO register address range 239 * 240 * 241 * RETURNS: 242 * 32-bit value read from the register. 243 */ 244 static inline uint32_t 245 ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off) 246 { 247 return (bus_read_4(sc->sc_mem_res[bank], off)); 248 } 249 250 /** 251 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers 252 * @sc: GPIO device context 253 * @bank: The bank to write to 254 * @off: The offset of a register from the GPIO register address range 255 * @val: The value to write into the register 256 * 257 * RETURNS: 258 * nothing 259 */ 260 static inline void 261 ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off, 262 uint32_t val) 263 { 264 bus_write_4(sc->sc_mem_res[bank], off, val); 265 } 266 267 static inline void 268 ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask) 269 { 270 271 /* We clear both set of registers. */ 272 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask); 273 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask); 274 } 275 276 static inline void 277 ti_gpio_intr_set(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask) 278 { 279 280 /* 281 * On OMAP4 we unmask only the MPU interrupt and on AM335x we 282 * also activate only the first interrupt. 283 */ 284 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_SET_0, mask); 285 } 286 287 static inline void 288 ti_gpio_intr_ack(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask) 289 { 290 291 /* 292 * Acknowledge the interrupt on both registers even if we use only 293 * the first one. 294 */ 295 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_0, mask); 296 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_1, mask); 297 } 298 299 static inline uint32_t 300 ti_gpio_intr_status(struct ti_gpio_softc *sc, unsigned int bank) 301 { 302 uint32_t reg; 303 304 /* Get the status from both registers. */ 305 reg = ti_gpio_read_4(sc, bank, TI_GPIO_IRQSTATUS_0); 306 reg |= ti_gpio_read_4(sc, bank, TI_GPIO_IRQSTATUS_1); 307 308 return (reg); 309 } 310 311 /** 312 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 313 * @dev: gpio device handle 314 * @maxpin: pointer to a value that upon return will contain the maximum number 315 * of pins in the device. 316 * 317 * 318 * LOCKING: 319 * No locking required, returns static data. 320 * 321 * RETURNS: 322 * Returns 0 on success otherwise an error code 323 */ 324 static int 325 ti_gpio_pin_max(device_t dev, int *maxpin) 326 { 327 328 *maxpin = ti_max_gpio_banks() * PINS_PER_BANK - 1; 329 330 return (0); 331 } 332 333 static int 334 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin) 335 { 336 337 if (pin >= sc->sc_maxpin || 338 TI_GPIO_BANK(pin) >= ti_max_gpio_banks() || 339 sc->sc_mem_res[TI_GPIO_BANK(pin)] == NULL) { 340 return (EINVAL); 341 } 342 343 return (0); 344 } 345 346 /** 347 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin 348 * @dev: gpio device handle 349 * @pin: the number of the pin 350 * @caps: pointer to a value that upon return will contain the capabilities 351 * 352 * Currently all pins have the same capability, notably: 353 * - GPIO_PIN_INPUT 354 * - GPIO_PIN_OUTPUT 355 * - GPIO_PIN_PULLUP 356 * - GPIO_PIN_PULLDOWN 357 * 358 * LOCKING: 359 * No locking required, returns static data. 360 * 361 * RETURNS: 362 * Returns 0 on success otherwise an error code 363 */ 364 static int 365 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 366 { 367 struct ti_gpio_softc *sc; 368 369 sc = device_get_softc(dev); 370 if (ti_gpio_valid_pin(sc, pin) != 0) 371 return (EINVAL); 372 373 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP | 374 GPIO_PIN_PULLDOWN); 375 376 return (0); 377 } 378 379 /** 380 * ti_gpio_pin_getflags - Gets the current flags of a given pin 381 * @dev: gpio device handle 382 * @pin: the number of the pin 383 * @flags: upon return will contain the current flags of the pin 384 * 385 * Reads the current flags of a given pin, here we actually read the H/W 386 * registers to determine the flags, rather than storing the value in the 387 * setflags call. 388 * 389 * LOCKING: 390 * Internally locks the context 391 * 392 * RETURNS: 393 * Returns 0 on success otherwise an error code 394 */ 395 static int 396 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 397 { 398 struct ti_gpio_softc *sc; 399 400 sc = device_get_softc(dev); 401 if (ti_gpio_valid_pin(sc, pin) != 0) 402 return (EINVAL); 403 404 /* Get the current pin state */ 405 TI_GPIO_LOCK(sc); 406 TI_GPIO_GET_FLAGS(dev, pin, flags); 407 TI_GPIO_UNLOCK(sc); 408 409 return (0); 410 } 411 412 /** 413 * ti_gpio_pin_getname - Gets the name of a given pin 414 * @dev: gpio device handle 415 * @pin: the number of the pin 416 * @name: buffer to put the name in 417 * 418 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 419 * of the pin. 420 * 421 * LOCKING: 422 * No locking required, returns static data. 423 * 424 * RETURNS: 425 * Returns 0 on success otherwise an error code 426 */ 427 static int 428 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 429 { 430 struct ti_gpio_softc *sc; 431 432 sc = device_get_softc(dev); 433 if (ti_gpio_valid_pin(sc, pin) != 0) 434 return (EINVAL); 435 436 /* Set a very simple name */ 437 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 438 name[GPIOMAXNAME - 1] = '\0'; 439 440 return (0); 441 } 442 443 /** 444 * ti_gpio_pin_setflags - Sets the flags for a given pin 445 * @dev: gpio device handle 446 * @pin: the number of the pin 447 * @flags: the flags to set 448 * 449 * The flags of the pin correspond to things like input/output mode, pull-ups, 450 * pull-downs, etc. This driver doesn't support all flags, only the following: 451 * - GPIO_PIN_INPUT 452 * - GPIO_PIN_OUTPUT 453 * - GPIO_PIN_PULLUP 454 * - GPIO_PIN_PULLDOWN 455 * 456 * LOCKING: 457 * Internally locks the context 458 * 459 * RETURNS: 460 * Returns 0 on success otherwise an error code 461 */ 462 static int 463 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 464 { 465 struct ti_gpio_softc *sc; 466 uint32_t oe; 467 468 sc = device_get_softc(dev); 469 if (ti_gpio_valid_pin(sc, pin) != 0) 470 return (EINVAL); 471 472 /* Set the GPIO mode and state */ 473 TI_GPIO_LOCK(sc); 474 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) { 475 TI_GPIO_UNLOCK(sc); 476 return (EINVAL); 477 } 478 479 /* If configuring as an output set the "output enable" bit */ 480 oe = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), TI_GPIO_OE); 481 if (flags & GPIO_PIN_INPUT) 482 oe |= TI_GPIO_MASK(pin); 483 else 484 oe &= ~TI_GPIO_MASK(pin); 485 ti_gpio_write_4(sc, TI_GPIO_BANK(pin), TI_GPIO_OE, oe); 486 TI_GPIO_UNLOCK(sc); 487 488 return (0); 489 } 490 491 /** 492 * ti_gpio_pin_set - Sets the current level on a GPIO pin 493 * @dev: gpio device handle 494 * @pin: the number of the pin 495 * @value: non-zero value will drive the pin high, otherwise the pin is 496 * driven low. 497 * 498 * 499 * LOCKING: 500 * Internally locks the context 501 * 502 * RETURNS: 503 * Returns 0 on success otherwise a error code 504 */ 505 static int 506 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 507 { 508 struct ti_gpio_softc *sc; 509 uint32_t reg; 510 511 sc = device_get_softc(dev); 512 if (ti_gpio_valid_pin(sc, pin) != 0) 513 return (EINVAL); 514 515 TI_GPIO_LOCK(sc); 516 if (value == GPIO_PIN_LOW) 517 reg = TI_GPIO_CLEARDATAOUT; 518 else 519 reg = TI_GPIO_SETDATAOUT; 520 ti_gpio_write_4(sc, TI_GPIO_BANK(pin), reg, TI_GPIO_MASK(pin)); 521 TI_GPIO_UNLOCK(sc); 522 523 return (0); 524 } 525 526 /** 527 * ti_gpio_pin_get - Gets the current level on a GPIO pin 528 * @dev: gpio device handle 529 * @pin: the number of the pin 530 * @value: pointer to a value that upond return will contain the pin value 531 * 532 * The pin must be configured as an input pin beforehand, otherwise this 533 * function will fail. 534 * 535 * LOCKING: 536 * Internally locks the context 537 * 538 * RETURNS: 539 * Returns 0 on success otherwise a error code 540 */ 541 static int 542 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 543 { 544 struct ti_gpio_softc *sc; 545 uint32_t oe, reg, val; 546 547 sc = device_get_softc(dev); 548 if (ti_gpio_valid_pin(sc, pin) != 0) 549 return (EINVAL); 550 551 /* 552 * Return data from output latch when set as output and from the 553 * input register otherwise. 554 */ 555 TI_GPIO_LOCK(sc); 556 oe = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), TI_GPIO_OE); 557 if (oe & TI_GPIO_MASK(pin)) 558 reg = TI_GPIO_DATAIN; 559 else 560 reg = TI_GPIO_DATAOUT; 561 val = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), reg); 562 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0; 563 TI_GPIO_UNLOCK(sc); 564 565 return (0); 566 } 567 568 /** 569 * ti_gpio_pin_toggle - Toggles a given GPIO pin 570 * @dev: gpio device handle 571 * @pin: the number of the pin 572 * 573 * 574 * LOCKING: 575 * Internally locks the context 576 * 577 * RETURNS: 578 * Returns 0 on success otherwise a error code 579 */ 580 static int 581 ti_gpio_pin_toggle(device_t dev, uint32_t pin) 582 { 583 struct ti_gpio_softc *sc; 584 uint32_t reg, val; 585 586 sc = device_get_softc(dev); 587 if (ti_gpio_valid_pin(sc, pin) != 0) 588 return (EINVAL); 589 590 /* Toggle the pin */ 591 TI_GPIO_LOCK(sc); 592 val = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), TI_GPIO_DATAOUT); 593 if (val & TI_GPIO_MASK(pin)) 594 reg = TI_GPIO_CLEARDATAOUT; 595 else 596 reg = TI_GPIO_SETDATAOUT; 597 ti_gpio_write_4(sc, TI_GPIO_BANK(pin), reg, TI_GPIO_MASK(pin)); 598 TI_GPIO_UNLOCK(sc); 599 600 return (0); 601 } 602 603 /** 604 * ti_gpio_intr - ISR for all GPIO modules 605 * @arg: the soft context pointer 606 * 607 * LOCKING: 608 * Internally locks the context 609 * 610 */ 611 static int 612 ti_gpio_intr(void *arg) 613 { 614 int bank_last, irq; 615 struct intr_event *event; 616 struct ti_gpio_softc *sc; 617 uint32_t reg; 618 619 sc = (struct ti_gpio_softc *)arg; 620 bank_last = -1; 621 reg = 0; /* squelch bogus gcc warning */ 622 for (irq = 0; irq < sc->sc_maxpin; irq++) { 623 624 /* Read interrupt status only once for each bank. */ 625 if (TI_GPIO_BANK(irq) != bank_last) { 626 reg = ti_gpio_intr_status(sc, TI_GPIO_BANK(irq)); 627 bank_last = TI_GPIO_BANK(irq); 628 } 629 if ((reg & TI_GPIO_MASK(irq)) == 0) 630 continue; 631 event = sc->sc_events[irq]; 632 if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers)) 633 intr_event_handle(event, NULL); 634 else 635 device_printf(sc->sc_dev, "Stray IRQ %d\n", irq); 636 /* Ack the IRQ Status bit. */ 637 ti_gpio_intr_ack(sc, TI_GPIO_BANK(irq), TI_GPIO_MASK(irq)); 638 } 639 640 return (FILTER_HANDLED); 641 } 642 643 static int 644 ti_gpio_attach_intr(device_t dev) 645 { 646 int i; 647 struct ti_gpio_softc *sc; 648 649 sc = device_get_softc(dev); 650 for (i = 0; i < ti_max_gpio_intrs(); i++) { 651 if (sc->sc_irq_res[i] == NULL) 652 break; 653 654 /* 655 * Register our interrupt filter for each of the IRQ resources. 656 */ 657 if (bus_setup_intr(dev, sc->sc_irq_res[i], 658 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc, 659 &sc->sc_irq_hdl[i]) != 0) { 660 device_printf(dev, 661 "WARNING: unable to register interrupt filter\n"); 662 return (-1); 663 } 664 } 665 666 return (0); 667 } 668 669 static int 670 ti_gpio_detach_intr(device_t dev) 671 { 672 int i; 673 struct ti_gpio_softc *sc; 674 675 /* Teardown our interrupt filters. */ 676 sc = device_get_softc(dev); 677 for (i = 0; i < ti_max_gpio_intrs(); i++) { 678 if (sc->sc_irq_res[i] == NULL) 679 break; 680 681 if (sc->sc_irq_hdl[i]) { 682 bus_teardown_intr(dev, sc->sc_irq_res[i], 683 sc->sc_irq_hdl[i]); 684 } 685 } 686 687 return (0); 688 } 689 690 static int 691 ti_gpio_bank_init(device_t dev, int bank) 692 { 693 int pin; 694 struct ti_gpio_softc *sc; 695 uint32_t flags, reg_oe, rev; 696 697 sc = device_get_softc(dev); 698 699 /* Enable the interface and functional clocks for the module. */ 700 ti_prcm_clk_enable(GPIO0_CLK + ti_first_gpio_bank() + bank); 701 702 /* 703 * Read the revision number of the module. TI don't publish the 704 * actual revision numbers, so instead the values have been 705 * determined by experimentation. 706 */ 707 rev = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION); 708 709 /* Check the revision. */ 710 if (rev != ti_gpio_rev()) { 711 device_printf(dev, "Warning: could not determine the revision " 712 "of GPIO module %d (revision:0x%08x)\n", bank, rev); 713 return (EINVAL); 714 } 715 716 /* Disable interrupts for all pins. */ 717 ti_gpio_intr_clr(sc, bank, 0xffffffff); 718 719 /* Init OE register based on pads configuration. */ 720 reg_oe = 0xffffffff; 721 for (pin = 0; pin < PINS_PER_BANK; pin++) { 722 TI_GPIO_GET_FLAGS(dev, PINS_PER_BANK * bank + pin, &flags); 723 if (flags & GPIO_PIN_OUTPUT) 724 reg_oe &= ~(1UL << pin); 725 } 726 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe); 727 728 return (0); 729 } 730 731 /** 732 * ti_gpio_attach - attach function for the driver 733 * @dev: gpio device handle 734 * 735 * Allocates and sets up the driver context for all GPIO banks. This function 736 * expects the memory ranges and IRQs to already be allocated to the driver. 737 * 738 * LOCKING: 739 * None 740 * 741 * RETURNS: 742 * Always returns 0 743 */ 744 static int 745 ti_gpio_attach(device_t dev) 746 { 747 struct ti_gpio_softc *sc; 748 unsigned int i; 749 int err; 750 751 if (ti_gpio_sc != NULL) 752 return (ENXIO); 753 754 ti_gpio_sc = sc = device_get_softc(dev); 755 sc->sc_dev = dev; 756 TI_GPIO_LOCK_INIT(sc); 757 ti_gpio_pin_max(dev, &sc->sc_maxpin); 758 sc->sc_maxpin++; 759 760 /* There are up to 6 different GPIO register sets located in different 761 * memory areas on the chip. The memory range should have been set for 762 * the driver when it was added as a child. 763 */ 764 if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) { 765 device_printf(dev, "Error: could not allocate mem resources\n"); 766 return (ENXIO); 767 } 768 769 /* Request the IRQ resources */ 770 if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) { 771 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); 772 device_printf(dev, "Error: could not allocate irq resources\n"); 773 return (ENXIO); 774 } 775 776 /* Setup the IRQ resources */ 777 if (ti_gpio_attach_intr(dev) != 0) { 778 ti_gpio_detach_intr(dev); 779 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res); 780 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); 781 return (ENXIO); 782 } 783 784 /* 785 * Initialize the interrupt settings. The default is active-low 786 * interrupts. 787 */ 788 sc->sc_irq_trigger = malloc( 789 sizeof(*sc->sc_irq_trigger) * sc->sc_maxpin, 790 M_DEVBUF, M_WAITOK | M_ZERO); 791 sc->sc_irq_polarity = malloc( 792 sizeof(*sc->sc_irq_polarity) * sc->sc_maxpin, 793 M_DEVBUF, M_WAITOK | M_ZERO); 794 for (i = 0; i < sc->sc_maxpin; i++) { 795 sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL; 796 sc->sc_irq_polarity[i] = INTR_POLARITY_LOW; 797 } 798 799 sc->sc_events = malloc(sizeof(struct intr_event *) * sc->sc_maxpin, 800 M_DEVBUF, M_WAITOK | M_ZERO); 801 802 /* We need to go through each block and ensure the clocks are running and 803 * the module is enabled. It might be better to do this only when the 804 * pins are configured which would result in less power used if the GPIO 805 * pins weren't used ... 806 */ 807 for (i = 0; i < ti_max_gpio_banks(); i++) { 808 if (sc->sc_mem_res[i] != NULL) { 809 /* Initialize the GPIO module. */ 810 err = ti_gpio_bank_init(dev, i); 811 if (err != 0) { 812 ti_gpio_detach_intr(dev); 813 bus_release_resources(dev, ti_gpio_irq_spec, 814 sc->sc_irq_res); 815 bus_release_resources(dev, ti_gpio_mem_spec, 816 sc->sc_mem_res); 817 return (err); 818 } 819 } 820 } 821 822 /* Finish of the probe call */ 823 device_add_child(dev, "gpioc", -1); 824 device_add_child(dev, "gpiobus", -1); 825 826 return (bus_generic_attach(dev)); 827 } 828 829 /** 830 * ti_gpio_detach - detach function for the driver 831 * @dev: scm device handle 832 * 833 * Allocates and sets up the driver context, this simply entails creating a 834 * bus mappings for the SCM register set. 835 * 836 * LOCKING: 837 * None 838 * 839 * RETURNS: 840 * Always returns 0 841 */ 842 static int 843 ti_gpio_detach(device_t dev) 844 { 845 struct ti_gpio_softc *sc = device_get_softc(dev); 846 unsigned int i; 847 848 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 849 850 /* Disable all interrupts */ 851 for (i = 0; i < ti_max_gpio_banks(); i++) { 852 if (sc->sc_mem_res[i] != NULL) 853 ti_gpio_intr_clr(sc, i, 0xffffffff); 854 } 855 856 bus_generic_detach(dev); 857 858 free(sc->sc_events, M_DEVBUF); 859 free(sc->sc_irq_polarity, M_DEVBUF); 860 free(sc->sc_irq_trigger, M_DEVBUF); 861 862 /* Release the memory and IRQ resources. */ 863 ti_gpio_detach_intr(dev); 864 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res); 865 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); 866 867 TI_GPIO_LOCK_DESTROY(sc); 868 869 return (0); 870 } 871 872 static uint32_t 873 ti_gpio_intr_reg(struct ti_gpio_softc *sc, int irq) 874 { 875 876 if (ti_gpio_valid_pin(sc, irq) != 0) 877 return (0); 878 879 if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) { 880 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 881 return (TI_GPIO_LEVELDETECT0); 882 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 883 return (TI_GPIO_LEVELDETECT1); 884 } else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) { 885 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 886 return (TI_GPIO_FALLINGDETECT); 887 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 888 return (TI_GPIO_RISINGDETECT); 889 } 890 891 return (0); 892 } 893 894 static void 895 ti_gpio_mask_irq(void *source) 896 { 897 int irq; 898 uint32_t reg, val; 899 900 irq = (int)source; 901 if (ti_gpio_valid_pin(ti_gpio_sc, irq) != 0) 902 return; 903 904 TI_GPIO_LOCK(ti_gpio_sc); 905 ti_gpio_intr_clr(ti_gpio_sc, TI_GPIO_BANK(irq), TI_GPIO_MASK(irq)); 906 reg = ti_gpio_intr_reg(ti_gpio_sc, irq); 907 if (reg != 0) { 908 val = ti_gpio_read_4(ti_gpio_sc, TI_GPIO_BANK(irq), reg); 909 val &= ~TI_GPIO_MASK(irq); 910 ti_gpio_write_4(ti_gpio_sc, TI_GPIO_BANK(irq), reg, val); 911 } 912 TI_GPIO_UNLOCK(ti_gpio_sc); 913 } 914 915 static void 916 ti_gpio_unmask_irq(void *source) 917 { 918 int irq; 919 uint32_t reg, val; 920 921 irq = (int)source; 922 if (ti_gpio_valid_pin(ti_gpio_sc, irq) != 0) 923 return; 924 925 TI_GPIO_LOCK(ti_gpio_sc); 926 reg = ti_gpio_intr_reg(ti_gpio_sc, irq); 927 if (reg != 0) { 928 val = ti_gpio_read_4(ti_gpio_sc, TI_GPIO_BANK(irq), reg); 929 val |= TI_GPIO_MASK(irq); 930 ti_gpio_write_4(ti_gpio_sc, TI_GPIO_BANK(irq), reg, val); 931 ti_gpio_intr_set(ti_gpio_sc, TI_GPIO_BANK(irq), 932 TI_GPIO_MASK(irq)); 933 } 934 TI_GPIO_UNLOCK(ti_gpio_sc); 935 } 936 937 static int 938 ti_gpio_activate_resource(device_t dev, device_t child, int type, int rid, 939 struct resource *res) 940 { 941 int pin; 942 943 if (type != SYS_RES_IRQ) 944 return (ENXIO); 945 946 /* Unmask the interrupt. */ 947 pin = rman_get_start(res); 948 ti_gpio_unmask_irq((void *)(uintptr_t)pin); 949 950 return (0); 951 } 952 953 static int 954 ti_gpio_deactivate_resource(device_t dev, device_t child, int type, int rid, 955 struct resource *res) 956 { 957 int pin; 958 959 if (type != SYS_RES_IRQ) 960 return (ENXIO); 961 962 /* Mask the interrupt. */ 963 pin = rman_get_start(res); 964 ti_gpio_mask_irq((void *)(uintptr_t)pin); 965 966 return (0); 967 } 968 969 static int 970 ti_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig, 971 enum intr_polarity pol) 972 { 973 struct ti_gpio_softc *sc; 974 uint32_t oldreg, reg, val; 975 976 sc = device_get_softc(dev); 977 if (ti_gpio_valid_pin(sc, irq) != 0) 978 return (EINVAL); 979 980 /* There is no standard trigger or polarity. */ 981 if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM) 982 return (EINVAL); 983 984 TI_GPIO_LOCK(sc); 985 /* 986 * TRM recommends add the new event before remove the old one to 987 * avoid losing interrupts. 988 */ 989 oldreg = ti_gpio_intr_reg(sc, irq); 990 sc->sc_irq_trigger[irq] = trig; 991 sc->sc_irq_polarity[irq] = pol; 992 reg = ti_gpio_intr_reg(sc, irq); 993 if (reg != 0) { 994 /* Apply the new settings. */ 995 val = ti_gpio_read_4(sc, TI_GPIO_BANK(irq), reg); 996 val |= TI_GPIO_MASK(irq); 997 ti_gpio_write_4(sc, TI_GPIO_BANK(irq), reg, val); 998 } 999 if (oldreg != 0) { 1000 /* Remove the old settings. */ 1001 val = ti_gpio_read_4(sc, TI_GPIO_BANK(irq), oldreg); 1002 val &= ~TI_GPIO_MASK(irq); 1003 ti_gpio_write_4(sc, TI_GPIO_BANK(irq), oldreg, val); 1004 } 1005 TI_GPIO_UNLOCK(sc); 1006 1007 return (0); 1008 } 1009 1010 static int 1011 ti_gpio_setup_intr(device_t dev, device_t child, struct resource *ires, 1012 int flags, driver_filter_t *filt, driver_intr_t *handler, 1013 void *arg, void **cookiep) 1014 { 1015 struct ti_gpio_softc *sc; 1016 struct intr_event *event; 1017 int pin, error; 1018 1019 sc = device_get_softc(dev); 1020 pin = rman_get_start(ires); 1021 if (ti_gpio_valid_pin(sc, pin) != 0) 1022 panic("%s: bad pin %d", __func__, pin); 1023 1024 event = sc->sc_events[pin]; 1025 if (event == NULL) { 1026 error = intr_event_create(&event, (void *)(uintptr_t)pin, 0, 1027 pin, ti_gpio_mask_irq, ti_gpio_unmask_irq, NULL, NULL, 1028 "gpio%d pin%d:", device_get_unit(dev), pin); 1029 if (error != 0) 1030 return (error); 1031 sc->sc_events[pin] = event; 1032 } 1033 intr_event_add_handler(event, device_get_nameunit(child), filt, 1034 handler, arg, intr_priority(flags), flags, cookiep); 1035 1036 return (0); 1037 } 1038 1039 static int 1040 ti_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires, 1041 void *cookie) 1042 { 1043 struct ti_gpio_softc *sc; 1044 int pin, err; 1045 1046 sc = device_get_softc(dev); 1047 pin = rman_get_start(ires); 1048 if (ti_gpio_valid_pin(sc, pin) != 0) 1049 panic("%s: bad pin %d", __func__, pin); 1050 if (sc->sc_events[pin] == NULL) 1051 panic("Trying to teardown unoccupied IRQ"); 1052 err = intr_event_remove_handler(cookie); 1053 if (!err) 1054 sc->sc_events[pin] = NULL; 1055 1056 return (err); 1057 } 1058 1059 static phandle_t 1060 ti_gpio_get_node(device_t bus, device_t dev) 1061 { 1062 1063 /* We only have one child, the GPIO bus, which needs our own node. */ 1064 return (ofw_bus_get_node(bus)); 1065 } 1066 1067 static device_method_t ti_gpio_methods[] = { 1068 DEVMETHOD(device_attach, ti_gpio_attach), 1069 DEVMETHOD(device_detach, ti_gpio_detach), 1070 1071 /* GPIO protocol */ 1072 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 1073 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 1074 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 1075 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 1076 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 1077 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 1078 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 1079 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 1080 1081 /* Bus interface */ 1082 DEVMETHOD(bus_activate_resource, ti_gpio_activate_resource), 1083 DEVMETHOD(bus_deactivate_resource, ti_gpio_deactivate_resource), 1084 DEVMETHOD(bus_config_intr, ti_gpio_config_intr), 1085 DEVMETHOD(bus_setup_intr, ti_gpio_setup_intr), 1086 DEVMETHOD(bus_teardown_intr, ti_gpio_teardown_intr), 1087 1088 /* ofw_bus interface */ 1089 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 1090 1091 {0, 0}, 1092 }; 1093 1094 driver_t ti_gpio_driver = { 1095 "gpio", 1096 ti_gpio_methods, 1097 sizeof(struct ti_gpio_softc), 1098 }; 1099