1 /*- 2 * Copyright (c) 2011 3 * Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /** 29 * Very simple GPIO (general purpose IO) driver module for TI OMAP SoC's. 30 * 31 * Currently this driver only does the basics, get a value on a pin & set a 32 * value on a pin. Hopefully over time I'll expand this to be a bit more generic 33 * and support interrupts and other various bits on the SoC can do ... in the 34 * meantime this is all you get. 35 * 36 * Beware the OMA datasheet(s) lists GPIO banks 1-6, whereas I've used 0-5 here 37 * in the code. 38 * 39 * 40 */ 41 42 #include <sys/cdefs.h> 43 __FBSDID("$FreeBSD$"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/bus.h> 48 49 #include <sys/kernel.h> 50 #include <sys/module.h> 51 #include <sys/rman.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/gpio.h> 55 56 #include <machine/bus.h> 57 #include <machine/resource.h> 58 59 #include <arm/ti/ti_cpuid.h> 60 #include <arm/ti/ti_scm.h> 61 #include <arm/ti/ti_prcm.h> 62 63 #include <dev/fdt/fdt_common.h> 64 #include <dev/ofw/openfirm.h> 65 #include <dev/ofw/ofw_bus.h> 66 #include <dev/ofw/ofw_bus_subr.h> 67 68 #include "gpio_if.h" 69 70 /* Register definitions */ 71 #define TI_GPIO_REVISION 0x0000 72 #define TI_GPIO_SYSCONFIG 0x0010 73 #if defined(SOC_OMAP3) 74 #define TI_GPIO_SYSSTATUS 0x0014 75 #define TI_GPIO_IRQSTATUS1 0x0018 76 #define TI_GPIO_IRQENABLE1 0x001C 77 #define TI_GPIO_WAKEUPENABLE 0x0020 78 #define TI_GPIO_IRQSTATUS2 0x0028 79 #define TI_GPIO_IRQENABLE2 0x002C 80 #define TI_GPIO_CTRL 0x0030 81 #define TI_GPIO_OE 0x0034 82 #define TI_GPIO_DATAIN 0x0038 83 #define TI_GPIO_DATAOUT 0x003C 84 #define TI_GPIO_LEVELDETECT0 0x0040 85 #define TI_GPIO_LEVELDETECT1 0x0044 86 #define TI_GPIO_RISINGDETECT 0x0048 87 #define TI_GPIO_FALLINGDETECT 0x004C 88 #define TI_GPIO_DEBOUNCENABLE 0x0050 89 #define TI_GPIO_DEBOUNCINGTIME 0x0054 90 #define TI_GPIO_CLEARIRQENABLE1 0x0060 91 #define TI_GPIO_SETIRQENABLE1 0x0064 92 #define TI_GPIO_CLEARIRQENABLE2 0x0070 93 #define TI_GPIO_SETIRQENABLE2 0x0074 94 #define TI_GPIO_CLEARWKUENA 0x0080 95 #define TI_GPIO_SETWKUENA 0x0084 96 #define TI_GPIO_CLEARDATAOUT 0x0090 97 #define TI_GPIO_SETDATAOUT 0x0094 98 #elif defined(SOC_OMAP4) || defined(SOC_TI_AM335X) 99 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024 100 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028 101 #define TI_GPIO_IRQSTATUS_0 0x002C 102 #define TI_GPIO_IRQSTATUS_1 0x0030 103 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 104 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 105 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C 106 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 107 #define TI_GPIO_IRQWAKEN_0 0x0044 108 #define TI_GPIO_IRQWAKEN_1 0x0048 109 #define TI_GPIO_SYSSTATUS 0x0114 110 #define TI_GPIO_IRQSTATUS1 0x0118 111 #define TI_GPIO_IRQENABLE1 0x011C 112 #define TI_GPIO_WAKEUPENABLE 0x0120 113 #define TI_GPIO_IRQSTATUS2 0x0128 114 #define TI_GPIO_IRQENABLE2 0x012C 115 #define TI_GPIO_CTRL 0x0130 116 #define TI_GPIO_OE 0x0134 117 #define TI_GPIO_DATAIN 0x0138 118 #define TI_GPIO_DATAOUT 0x013C 119 #define TI_GPIO_LEVELDETECT0 0x0140 120 #define TI_GPIO_LEVELDETECT1 0x0144 121 #define TI_GPIO_RISINGDETECT 0x0148 122 #define TI_GPIO_FALLINGDETECT 0x014C 123 #define TI_GPIO_DEBOUNCENABLE 0x0150 124 #define TI_GPIO_DEBOUNCINGTIME 0x0154 125 #define TI_GPIO_CLEARWKUPENA 0x0180 126 #define TI_GPIO_SETWKUENA 0x0184 127 #define TI_GPIO_CLEARDATAOUT 0x0190 128 #define TI_GPIO_SETDATAOUT 0x0194 129 #else 130 #error "Unknown SoC" 131 #endif 132 133 /* Other SoC Specific definitions */ 134 #define OMAP3_MAX_GPIO_BANKS 6 135 #define OMAP3_FIRST_GPIO_BANK 1 136 #define OMAP3_INTR_PER_BANK 1 137 #define OMAP3_GPIO_REV 0x00000025 138 #define OMAP4_MAX_GPIO_BANKS 6 139 #define OMAP4_FIRST_GPIO_BANK 1 140 #define OMAP4_INTR_PER_BANK 1 141 #define OMAP4_GPIO_REV 0x50600801 142 #define AM335X_MAX_GPIO_BANKS 4 143 #define AM335X_FIRST_GPIO_BANK 0 144 #define AM335X_INTR_PER_BANK 2 145 #define AM335X_GPIO_REV 0x50600801 146 #define PINS_PER_BANK 32 147 #define MAX_GPIO_BANKS 6 148 /* Maximum GPIOS possible, max of *_MAX_GPIO_BANKS * *_INTR_PER_BANK */ 149 #define MAX_GPIO_INTRS 8 150 151 static u_int 152 ti_max_gpio_banks(void) 153 { 154 switch(ti_chip()) { 155 #ifdef SOC_OMAP3 156 case CHIP_OMAP_3: 157 return (OMAP3_MAX_GPIO_BANKS); 158 #endif 159 #ifdef SOC_OMAP4 160 case CHIP_OMAP_4: 161 return (OMAP4_MAX_GPIO_BANKS); 162 #endif 163 #ifdef SOC_TI_AM335X 164 case CHIP_AM335X: 165 return (AM335X_MAX_GPIO_BANKS); 166 #endif 167 } 168 return (0); 169 } 170 171 static u_int 172 ti_max_gpio_intrs(void) 173 { 174 switch(ti_chip()) { 175 #ifdef SOC_OMAP3 176 case CHIP_OMAP_3: 177 return (OMAP3_MAX_GPIO_BANKS * OMAP3_INTR_PER_BANK); 178 #endif 179 #ifdef SOC_OMAP4 180 case CHIP_OMAP_4: 181 return (OMAP4_MAX_GPIO_BANKS * OMAP4_INTR_PER_BANK); 182 #endif 183 #ifdef SOC_TI_AM335X 184 case CHIP_AM335X: 185 return (AM335X_MAX_GPIO_BANKS * AM335X_INTR_PER_BANK); 186 #endif 187 } 188 return (0); 189 } 190 191 static u_int 192 ti_first_gpio_bank(void) 193 { 194 switch(ti_chip()) { 195 #ifdef SOC_OMAP3 196 case CHIP_OMAP_3: 197 return (OMAP3_FIRST_GPIO_BANK); 198 #endif 199 #ifdef SOC_OMAP4 200 case CHIP_OMAP_4: 201 return (OMAP4_FIRST_GPIO_BANK); 202 #endif 203 #ifdef SOC_TI_AM335X 204 case CHIP_AM335X: 205 return (AM335X_FIRST_GPIO_BANK); 206 #endif 207 } 208 return (0); 209 } 210 211 static uint32_t 212 ti_gpio_rev(void) 213 { 214 switch(ti_chip()) { 215 #ifdef SOC_OMAP3 216 case CHIP_OMAP_3: 217 return (OMAP3_GPIO_REV); 218 #endif 219 #ifdef SOC_OMAP4 220 case CHIP_OMAP_4: 221 return (OMAP4_GPIO_REV); 222 #endif 223 #ifdef SOC_TI_AM335X 224 case CHIP_AM335X: 225 return (AM335X_GPIO_REV); 226 #endif 227 } 228 return (0); 229 } 230 231 /** 232 * ti_gpio_mem_spec - Resource specification used when allocating resources 233 * ti_gpio_irq_spec - Resource specification used when allocating resources 234 * 235 * This driver module can have up to six independent memory regions, each 236 * region typically controls 32 GPIO pins. 237 * 238 * On OMAP3 and OMAP4 there is only one physical interrupt line per bank, 239 * but there are two set of registers which control the interrupt delivery 240 * to internal subsystems. The first set of registers control the 241 * interrupts delivery to the MPU and the second set control the 242 * interrupts delivery to the DSP. 243 * 244 * On AM335x there are two physical interrupt lines for each GPIO module. 245 * Each interrupt line is controlled by a set of registers. 246 */ 247 static struct resource_spec ti_gpio_mem_spec[] = { 248 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 249 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL }, 250 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL }, 251 { SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL }, 252 #if !defined(SOC_TI_AM335X) 253 { SYS_RES_MEMORY, 4, RF_ACTIVE | RF_OPTIONAL }, 254 { SYS_RES_MEMORY, 5, RF_ACTIVE | RF_OPTIONAL }, 255 #endif 256 { -1, 0, 0 } 257 }; 258 static struct resource_spec ti_gpio_irq_spec[] = { 259 { SYS_RES_IRQ, 0, RF_ACTIVE }, 260 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, 261 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, 262 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, 263 { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL }, 264 { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL }, 265 #if defined(SOC_TI_AM335X) 266 { SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL }, 267 { SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL }, 268 #endif 269 { -1, 0, 0 } 270 }; 271 272 /** 273 * Structure that stores the driver context. 274 * 275 * This structure is allocated during driver attach. 276 */ 277 struct ti_gpio_softc { 278 device_t sc_dev; 279 280 /* 281 * The memory resource(s) for the PRCM register set, when the device is 282 * created the caller can assign up to 6 memory regions depending on 283 * the SoC type. 284 */ 285 struct resource *sc_mem_res[MAX_GPIO_BANKS]; 286 struct resource *sc_irq_res[MAX_GPIO_INTRS]; 287 288 /* The handle for the register IRQ handlers. */ 289 void *sc_irq_hdl[MAX_GPIO_INTRS]; 290 291 /* 292 * The following describes the H/W revision of each of the GPIO banks. 293 */ 294 uint32_t sc_revision[MAX_GPIO_BANKS]; 295 296 struct mtx sc_mtx; 297 }; 298 299 /** 300 * Macros for driver mutex locking 301 */ 302 #define TI_GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 303 #define TI_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 304 #define TI_GPIO_LOCK_INIT(_sc) \ 305 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 306 "ti_gpio", MTX_DEF) 307 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx) 308 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) 309 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED) 310 311 /** 312 * ti_gpio_read_4 - reads a 16-bit value from one of the PADCONFS registers 313 * @sc: GPIO device context 314 * @bank: The bank to read from 315 * @off: The offset of a register from the GPIO register address range 316 * 317 * 318 * RETURNS: 319 * 32-bit value read from the register. 320 */ 321 static inline uint32_t 322 ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off) 323 { 324 return (bus_read_4(sc->sc_mem_res[bank], off)); 325 } 326 327 /** 328 * ti_gpio_write_4 - writes a 32-bit value to one of the PADCONFS registers 329 * @sc: GPIO device context 330 * @bank: The bank to write to 331 * @off: The offset of a register from the GPIO register address range 332 * @val: The value to write into the register 333 * 334 * RETURNS: 335 * nothing 336 */ 337 static inline void 338 ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off, 339 uint32_t val) 340 { 341 bus_write_4(sc->sc_mem_res[bank], off, val); 342 } 343 344 static inline void 345 ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask) 346 { 347 348 /* We clear both set of registers. */ 349 #if defined(SOC_OMAP4) || defined(SOC_TI_AM335X) 350 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask); 351 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask); 352 #else 353 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE1, mask); 354 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE2, mask); 355 #endif 356 } 357 358 /** 359 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 360 * @dev: gpio device handle 361 * @maxpin: pointer to a value that upon return will contain the maximum number 362 * of pins in the device. 363 * 364 * 365 * LOCKING: 366 * Internally locks the context 367 * 368 * RETURNS: 369 * Returns 0 on success otherwise an error code 370 */ 371 static int 372 ti_gpio_pin_max(device_t dev, int *maxpin) 373 { 374 struct ti_gpio_softc *sc = device_get_softc(dev); 375 unsigned int i; 376 unsigned int banks = 0; 377 378 TI_GPIO_LOCK(sc); 379 380 /* Calculate how many valid banks we have and then multiply that by 32 to 381 * give use the total number of pins. 382 */ 383 for (i = 0; i < ti_max_gpio_banks(); i++) { 384 if (sc->sc_mem_res[i] != NULL) 385 banks++; 386 } 387 388 *maxpin = (banks * PINS_PER_BANK) - 1; 389 390 TI_GPIO_UNLOCK(sc); 391 392 return (0); 393 } 394 395 /** 396 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin 397 * @dev: gpio device handle 398 * @pin: the number of the pin 399 * @caps: pointer to a value that upon return will contain the capabilities 400 * 401 * Currently all pins have the same capability, notably: 402 * - GPIO_PIN_INPUT 403 * - GPIO_PIN_OUTPUT 404 * - GPIO_PIN_PULLUP 405 * - GPIO_PIN_PULLDOWN 406 * 407 * LOCKING: 408 * Internally locks the context 409 * 410 * RETURNS: 411 * Returns 0 on success otherwise an error code 412 */ 413 static int 414 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 415 { 416 struct ti_gpio_softc *sc = device_get_softc(dev); 417 uint32_t bank = (pin / PINS_PER_BANK); 418 419 TI_GPIO_LOCK(sc); 420 421 /* Sanity check the pin number is valid */ 422 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 423 TI_GPIO_UNLOCK(sc); 424 return (EINVAL); 425 } 426 427 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |GPIO_PIN_PULLUP | 428 GPIO_PIN_PULLDOWN); 429 430 TI_GPIO_UNLOCK(sc); 431 432 return (0); 433 } 434 435 /** 436 * ti_gpio_pin_getflags - Gets the current flags of a given pin 437 * @dev: gpio device handle 438 * @pin: the number of the pin 439 * @flags: upon return will contain the current flags of the pin 440 * 441 * Reads the current flags of a given pin, here we actually read the H/W 442 * registers to determine the flags, rather than storing the value in the 443 * setflags call. 444 * 445 * LOCKING: 446 * Internally locks the context 447 * 448 * RETURNS: 449 * Returns 0 on success otherwise an error code 450 */ 451 static int 452 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 453 { 454 struct ti_gpio_softc *sc = device_get_softc(dev); 455 uint32_t bank = (pin / PINS_PER_BANK); 456 457 TI_GPIO_LOCK(sc); 458 459 /* Sanity check the pin number is valid */ 460 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 461 TI_GPIO_UNLOCK(sc); 462 return (EINVAL); 463 } 464 465 /* Get the current pin state */ 466 ti_scm_padconf_get_gpioflags(pin, flags); 467 468 TI_GPIO_UNLOCK(sc); 469 470 return (0); 471 } 472 473 /** 474 * ti_gpio_pin_getname - Gets the name of a given pin 475 * @dev: gpio device handle 476 * @pin: the number of the pin 477 * @name: buffer to put the name in 478 * 479 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 480 * of the pin. 481 * 482 * LOCKING: 483 * Internally locks the context 484 * 485 * RETURNS: 486 * Returns 0 on success otherwise an error code 487 */ 488 static int 489 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 490 { 491 struct ti_gpio_softc *sc = device_get_softc(dev); 492 uint32_t bank = (pin / PINS_PER_BANK); 493 494 TI_GPIO_LOCK(sc); 495 496 /* Sanity check the pin number is valid */ 497 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 498 TI_GPIO_UNLOCK(sc); 499 return (EINVAL); 500 } 501 502 /* Set a very simple name */ 503 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 504 name[GPIOMAXNAME - 1] = '\0'; 505 506 TI_GPIO_UNLOCK(sc); 507 508 return (0); 509 } 510 511 /** 512 * ti_gpio_pin_setflags - Sets the flags for a given pin 513 * @dev: gpio device handle 514 * @pin: the number of the pin 515 * @flags: the flags to set 516 * 517 * The flags of the pin correspond to things like input/output mode, pull-ups, 518 * pull-downs, etc. This driver doesn't support all flags, only the following: 519 * - GPIO_PIN_INPUT 520 * - GPIO_PIN_OUTPUT 521 * - GPIO_PIN_PULLUP 522 * - GPIO_PIN_PULLDOWN 523 * 524 * LOCKING: 525 * Internally locks the context 526 * 527 * RETURNS: 528 * Returns 0 on success otherwise an error code 529 */ 530 static int 531 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 532 { 533 struct ti_gpio_softc *sc = device_get_softc(dev); 534 uint32_t bank = (pin / PINS_PER_BANK); 535 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 536 uint32_t reg_val; 537 538 /* Sanity check the flags supplied are valid, i.e. not input and output */ 539 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0x0000) 540 return (EINVAL); 541 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 542 (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) 543 return (EINVAL); 544 if ((flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) == 545 (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) 546 return (EINVAL); 547 548 TI_GPIO_LOCK(sc); 549 550 /* Sanity check the pin number is valid */ 551 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 552 TI_GPIO_UNLOCK(sc); 553 return (EINVAL); 554 } 555 556 /* Set the GPIO mode and state */ 557 if (ti_scm_padconf_set_gpioflags(pin, flags) != 0) { 558 TI_GPIO_UNLOCK(sc); 559 return (EINVAL); 560 } 561 562 /* If configuring as an output set the "output enable" bit */ 563 reg_val = ti_gpio_read_4(sc, bank, TI_GPIO_OE); 564 if (flags & GPIO_PIN_INPUT) 565 reg_val |= mask; 566 else 567 reg_val &= ~mask; 568 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_val); 569 570 TI_GPIO_UNLOCK(sc); 571 572 return (0); 573 } 574 575 /** 576 * ti_gpio_pin_set - Sets the current level on a GPIO pin 577 * @dev: gpio device handle 578 * @pin: the number of the pin 579 * @value: non-zero value will drive the pin high, otherwise the pin is 580 * driven low. 581 * 582 * 583 * LOCKING: 584 * Internally locks the context 585 * 586 * RETURNS: 587 * Returns 0 on success otherwise a error code 588 */ 589 static int 590 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 591 { 592 struct ti_gpio_softc *sc = device_get_softc(dev); 593 uint32_t bank = (pin / PINS_PER_BANK); 594 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 595 596 TI_GPIO_LOCK(sc); 597 598 /* Sanity check the pin number is valid */ 599 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 600 TI_GPIO_UNLOCK(sc); 601 return (EINVAL); 602 } 603 604 ti_gpio_write_4(sc, bank, (value == GPIO_PIN_LOW) ? TI_GPIO_CLEARDATAOUT 605 : TI_GPIO_SETDATAOUT, mask); 606 607 TI_GPIO_UNLOCK(sc); 608 609 return (0); 610 } 611 612 /** 613 * ti_gpio_pin_get - Gets the current level on a GPIO pin 614 * @dev: gpio device handle 615 * @pin: the number of the pin 616 * @value: pointer to a value that upond return will contain the pin value 617 * 618 * The pin must be configured as an input pin beforehand, otherwise this 619 * function will fail. 620 * 621 * LOCKING: 622 * Internally locks the context 623 * 624 * RETURNS: 625 * Returns 0 on success otherwise a error code 626 */ 627 static int 628 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 629 { 630 struct ti_gpio_softc *sc = device_get_softc(dev); 631 uint32_t bank = (pin / PINS_PER_BANK); 632 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 633 uint32_t val = 0; 634 635 TI_GPIO_LOCK(sc); 636 637 /* Sanity check the pin number is valid */ 638 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 639 TI_GPIO_UNLOCK(sc); 640 return (EINVAL); 641 } 642 643 /* Sanity check the pin is not configured as an output */ 644 val = ti_gpio_read_4(sc, bank, TI_GPIO_OE); 645 646 /* Read the value on the pin */ 647 if (val & mask) 648 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAIN) & mask) ? 1 : 0; 649 else 650 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT) & mask) ? 1 : 0; 651 652 TI_GPIO_UNLOCK(sc); 653 654 return (0); 655 } 656 657 /** 658 * ti_gpio_pin_toggle - Toggles a given GPIO pin 659 * @dev: gpio device handle 660 * @pin: the number of the pin 661 * 662 * 663 * LOCKING: 664 * Internally locks the context 665 * 666 * RETURNS: 667 * Returns 0 on success otherwise a error code 668 */ 669 static int 670 ti_gpio_pin_toggle(device_t dev, uint32_t pin) 671 { 672 struct ti_gpio_softc *sc = device_get_softc(dev); 673 uint32_t bank = (pin / PINS_PER_BANK); 674 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 675 uint32_t val; 676 677 TI_GPIO_LOCK(sc); 678 679 /* Sanity check the pin number is valid */ 680 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 681 TI_GPIO_UNLOCK(sc); 682 return (EINVAL); 683 } 684 685 /* Toggle the pin */ 686 val = ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT); 687 if (val & mask) 688 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARDATAOUT, mask); 689 else 690 ti_gpio_write_4(sc, bank, TI_GPIO_SETDATAOUT, mask); 691 692 TI_GPIO_UNLOCK(sc); 693 694 return (0); 695 } 696 697 /** 698 * ti_gpio_intr - ISR for all GPIO modules 699 * @arg: the soft context pointer 700 * 701 * Unsused 702 * 703 * LOCKING: 704 * Internally locks the context 705 * 706 */ 707 static void 708 ti_gpio_intr(void *arg) 709 { 710 struct ti_gpio_softc *sc = arg; 711 712 TI_GPIO_LOCK(sc); 713 /* TODO: something useful */ 714 TI_GPIO_UNLOCK(sc); 715 } 716 717 /** 718 * ti_gpio_probe - probe function for the driver 719 * @dev: gpio device handle 720 * 721 * Simply sets the name of the driver 722 * 723 * LOCKING: 724 * None 725 * 726 * RETURNS: 727 * Always returns 0 728 */ 729 static int 730 ti_gpio_probe(device_t dev) 731 { 732 733 if (!ofw_bus_status_okay(dev)) 734 return (ENXIO); 735 736 if (!ofw_bus_is_compatible(dev, "ti,gpio")) 737 return (ENXIO); 738 739 device_set_desc(dev, "TI General Purpose I/O (GPIO)"); 740 741 return (0); 742 } 743 744 static int 745 ti_gpio_attach_intr(device_t dev) 746 { 747 int i; 748 struct ti_gpio_softc *sc; 749 750 sc = device_get_softc(dev); 751 for (i = 0; i < ti_max_gpio_intrs(); i++) { 752 if (sc->sc_irq_res[i] == NULL) 753 break; 754 755 /* 756 * Register our interrupt handler for each of the IRQ resources. 757 */ 758 if (bus_setup_intr(dev, sc->sc_irq_res[i], 759 INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_gpio_intr, sc, 760 &sc->sc_irq_hdl[i]) != 0) { 761 device_printf(dev, 762 "WARNING: unable to register interrupt handler\n"); 763 return (-1); 764 } 765 } 766 767 return (0); 768 } 769 770 static int 771 ti_gpio_detach_intr(device_t dev) 772 { 773 int i; 774 struct ti_gpio_softc *sc; 775 776 /* Teardown our interrupt handlers. */ 777 sc = device_get_softc(dev); 778 for (i = 0; i < ti_max_gpio_intrs(); i++) { 779 if (sc->sc_irq_res[i] == NULL) 780 break; 781 782 if (sc->sc_irq_hdl[i]) { 783 bus_teardown_intr(dev, sc->sc_irq_res[i], 784 sc->sc_irq_hdl[i]); 785 } 786 } 787 788 return (0); 789 } 790 791 static int 792 ti_gpio_bank_init(device_t dev, int bank) 793 { 794 int pin; 795 struct ti_gpio_softc *sc; 796 uint32_t flags, reg_oe; 797 798 sc = device_get_softc(dev); 799 800 /* Enable the interface and functional clocks for the module. */ 801 ti_prcm_clk_enable(GPIO0_CLK + ti_first_gpio_bank() + bank); 802 803 /* 804 * Read the revision number of the module. TI don't publish the 805 * actual revision numbers, so instead the values have been 806 * determined by experimentation. 807 */ 808 sc->sc_revision[bank] = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION); 809 810 /* Check the revision. */ 811 if (sc->sc_revision[bank] != ti_gpio_rev()) { 812 device_printf(dev, "Warning: could not determine the revision " 813 "of %u GPIO module (revision:0x%08x)\n", 814 bank, sc->sc_revision[bank]); 815 return (EINVAL); 816 } 817 818 /* Disable interrupts for all pins. */ 819 ti_gpio_intr_clr(sc, bank, 0xffffffff); 820 821 /* Init OE register based on pads configuration. */ 822 reg_oe = 0xffffffff; 823 for (pin = 0; pin < PINS_PER_BANK; pin++) { 824 ti_scm_padconf_get_gpioflags(PINS_PER_BANK * bank + pin, 825 &flags); 826 if (flags & GPIO_PIN_OUTPUT) 827 reg_oe &= ~(1UL << pin); 828 } 829 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe); 830 831 return (0); 832 } 833 834 /** 835 * ti_gpio_attach - attach function for the driver 836 * @dev: gpio device handle 837 * 838 * Allocates and sets up the driver context for all GPIO banks. This function 839 * expects the memory ranges and IRQs to already be allocated to the driver. 840 * 841 * LOCKING: 842 * None 843 * 844 * RETURNS: 845 * Always returns 0 846 */ 847 static int 848 ti_gpio_attach(device_t dev) 849 { 850 struct ti_gpio_softc *sc; 851 unsigned int i; 852 int err; 853 854 sc = device_get_softc(dev); 855 sc->sc_dev = dev; 856 857 TI_GPIO_LOCK_INIT(sc); 858 859 /* There are up to 6 different GPIO register sets located in different 860 * memory areas on the chip. The memory range should have been set for 861 * the driver when it was added as a child. 862 */ 863 if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) { 864 device_printf(dev, "Error: could not allocate mem resources\n"); 865 return (ENXIO); 866 } 867 868 /* Request the IRQ resources */ 869 if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) { 870 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); 871 device_printf(dev, "Error: could not allocate irq resources\n"); 872 return (ENXIO); 873 } 874 875 /* Setup the IRQ resources */ 876 if (ti_gpio_attach_intr(dev) != 0) { 877 ti_gpio_detach_intr(dev); 878 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res); 879 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); 880 return (ENXIO); 881 } 882 883 /* We need to go through each block and ensure the clocks are running and 884 * the module is enabled. It might be better to do this only when the 885 * pins are configured which would result in less power used if the GPIO 886 * pins weren't used ... 887 */ 888 for (i = 0; i < ti_max_gpio_banks(); i++) { 889 if (sc->sc_mem_res[i] != NULL) { 890 /* Initialize the GPIO module. */ 891 err = ti_gpio_bank_init(dev, i); 892 if (err != 0) { 893 ti_gpio_detach_intr(dev); 894 bus_release_resources(dev, ti_gpio_irq_spec, 895 sc->sc_irq_res); 896 bus_release_resources(dev, ti_gpio_mem_spec, 897 sc->sc_mem_res); 898 return (err); 899 } 900 } 901 } 902 903 /* Finish of the probe call */ 904 device_add_child(dev, "gpioc", device_get_unit(dev)); 905 device_add_child(dev, "gpiobus", device_get_unit(dev)); 906 907 return (bus_generic_attach(dev)); 908 } 909 910 /** 911 * ti_gpio_detach - detach function for the driver 912 * @dev: scm device handle 913 * 914 * Allocates and sets up the driver context, this simply entails creating a 915 * bus mappings for the SCM register set. 916 * 917 * LOCKING: 918 * None 919 * 920 * RETURNS: 921 * Always returns 0 922 */ 923 static int 924 ti_gpio_detach(device_t dev) 925 { 926 struct ti_gpio_softc *sc = device_get_softc(dev); 927 unsigned int i; 928 929 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 930 931 /* Disable all interrupts */ 932 for (i = 0; i < ti_max_gpio_banks(); i++) { 933 if (sc->sc_mem_res[i] != NULL) 934 ti_gpio_intr_clr(sc, i, 0xffffffff); 935 } 936 937 bus_generic_detach(dev); 938 939 /* Release the memory and IRQ resources. */ 940 ti_gpio_detach_intr(dev); 941 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res); 942 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); 943 944 TI_GPIO_LOCK_DESTROY(sc); 945 946 return (0); 947 } 948 949 static phandle_t 950 ti_gpio_get_node(device_t bus, device_t dev) 951 { 952 953 /* We only have one child, the GPIO bus, which needs our own node. */ 954 return (ofw_bus_get_node(bus)); 955 } 956 957 static device_method_t ti_gpio_methods[] = { 958 DEVMETHOD(device_probe, ti_gpio_probe), 959 DEVMETHOD(device_attach, ti_gpio_attach), 960 DEVMETHOD(device_detach, ti_gpio_detach), 961 962 /* GPIO protocol */ 963 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 964 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 965 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 966 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 967 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 968 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 969 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 970 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 971 972 /* ofw_bus interface */ 973 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 974 975 {0, 0}, 976 }; 977 978 static driver_t ti_gpio_driver = { 979 "gpio", 980 ti_gpio_methods, 981 sizeof(struct ti_gpio_softc), 982 }; 983 static devclass_t ti_gpio_devclass; 984 985 DRIVER_MODULE(ti_gpio, simplebus, ti_gpio_driver, ti_gpio_devclass, 0, 0); 986