1 /*- 2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /** 29 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code 30 * here uses 0-5. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/proc.h> 45 #include <sys/rman.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/gpio.h> 49 #include <sys/interrupt.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 #include <machine/resource.h> 54 55 #include <arm/ti/ti_cpuid.h> 56 #include <arm/ti/ti_gpio.h> 57 #include <arm/ti/ti_scm.h> 58 #include <arm/ti/ti_prcm.h> 59 #include <arm/ti/ti_hwmods.h> 60 61 #include <dev/fdt/fdt_common.h> 62 #include <dev/gpio/gpiobusvar.h> 63 #include <dev/ofw/openfirm.h> 64 #include <dev/ofw/ofw_bus.h> 65 #include <dev/ofw/ofw_bus_subr.h> 66 67 #include "gpio_if.h" 68 #include "ti_gpio_if.h" 69 #include "pic_if.h" 70 71 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X) 72 #error "Unknown SoC" 73 #endif 74 75 /* Register definitions */ 76 #define TI_GPIO_REVISION 0x0000 77 #define TI_GPIO_SYSCONFIG 0x0010 78 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024 79 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028 80 #define TI_GPIO_IRQSTATUS_0 0x002C /* writing a 0 has no effect */ 81 #define TI_GPIO_IRQSTATUS_1 0x0030 /* writing a 0 has no effect */ 82 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 /* writing a 0 has no effect */ 83 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 /* writing a 0 has no effect */ 84 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C /* writing a 0 has no effect */ 85 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 /* writing a 0 has no effect */ 86 #define TI_GPIO_IRQWAKEN_0 0x0044 87 #define TI_GPIO_IRQWAKEN_1 0x0048 88 #define TI_GPIO_SYSSTATUS 0x0114 89 #define TI_GPIO_IRQSTATUS1 0x0118 90 #define TI_GPIO_IRQENABLE1 0x011C 91 #define TI_GPIO_WAKEUPENABLE 0x0120 92 #define TI_GPIO_IRQSTATUS2 0x0128 93 #define TI_GPIO_IRQENABLE2 0x012C 94 #define TI_GPIO_CTRL 0x0130 95 #define TI_GPIO_OE 0x0134 96 #define TI_GPIO_DATAIN 0x0138 97 #define TI_GPIO_DATAOUT 0x013C 98 #define TI_GPIO_LEVELDETECT0 0x0140 /* RW register */ 99 #define TI_GPIO_LEVELDETECT1 0x0144 /* RW register */ 100 #define TI_GPIO_RISINGDETECT 0x0148 /* RW register */ 101 #define TI_GPIO_FALLINGDETECT 0x014C /* RW register */ 102 #define TI_GPIO_DEBOUNCENABLE 0x0150 103 #define TI_GPIO_DEBOUNCINGTIME 0x0154 104 #define TI_GPIO_CLEARWKUPENA 0x0180 105 #define TI_GPIO_SETWKUENA 0x0184 106 #define TI_GPIO_CLEARDATAOUT 0x0190 107 #define TI_GPIO_SETDATAOUT 0x0194 108 109 /* Other SoC Specific definitions */ 110 #define OMAP4_FIRST_GPIO_BANK 1 111 #define OMAP4_INTR_PER_BANK 1 112 #define OMAP4_GPIO_REV 0x50600801 113 #define AM335X_FIRST_GPIO_BANK 0 114 #define AM335X_INTR_PER_BANK 2 115 #define AM335X_GPIO_REV 0x50600801 116 #define PINS_PER_BANK 32 117 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK)) 118 119 static int ti_gpio_intr(void *arg); 120 static int ti_gpio_detach(device_t); 121 122 static int ti_gpio_pic_attach(struct ti_gpio_softc *sc); 123 static int ti_gpio_pic_detach(struct ti_gpio_softc *sc); 124 125 static u_int 126 ti_first_gpio_bank(void) 127 { 128 switch(ti_chip()) { 129 #ifdef SOC_OMAP4 130 case CHIP_OMAP_4: 131 return (OMAP4_FIRST_GPIO_BANK); 132 #endif 133 #ifdef SOC_TI_AM335X 134 case CHIP_AM335X: 135 return (AM335X_FIRST_GPIO_BANK); 136 #endif 137 } 138 return (0); 139 } 140 141 static uint32_t 142 ti_gpio_rev(void) 143 { 144 switch(ti_chip()) { 145 #ifdef SOC_OMAP4 146 case CHIP_OMAP_4: 147 return (OMAP4_GPIO_REV); 148 #endif 149 #ifdef SOC_TI_AM335X 150 case CHIP_AM335X: 151 return (AM335X_GPIO_REV); 152 #endif 153 } 154 return (0); 155 } 156 157 /** 158 * Macros for driver mutex locking 159 */ 160 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 161 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 162 #define TI_GPIO_LOCK_INIT(_sc) \ 163 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 164 "ti_gpio", MTX_SPIN) 165 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 166 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 167 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 168 169 /** 170 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers 171 * @sc: GPIO device context 172 * @bank: The bank to read from 173 * @off: The offset of a register from the GPIO register address range 174 * 175 * 176 * RETURNS: 177 * 32-bit value read from the register. 178 */ 179 static inline uint32_t 180 ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off) 181 { 182 return (bus_read_4(sc->sc_mem_res, off)); 183 } 184 185 /** 186 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers 187 * @sc: GPIO device context 188 * @bank: The bank to write to 189 * @off: The offset of a register from the GPIO register address range 190 * @val: The value to write into the register 191 * 192 * RETURNS: 193 * nothing 194 */ 195 static inline void 196 ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off, 197 uint32_t val) 198 { 199 bus_write_4(sc->sc_mem_res, off, val); 200 } 201 202 static inline void 203 ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask) 204 { 205 206 /* We clear both set of registers. */ 207 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask); 208 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask); 209 } 210 211 static inline void 212 ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask) 213 { 214 215 /* 216 * On OMAP4 we unmask only the MPU interrupt and on AM335x we 217 * also activate only the first interrupt. 218 */ 219 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask); 220 } 221 222 static inline void 223 ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask) 224 { 225 226 /* 227 * Acknowledge the interrupt on both registers even if we use only 228 * the first one. 229 */ 230 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask); 231 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask); 232 } 233 234 static inline uint32_t 235 ti_gpio_intr_status(struct ti_gpio_softc *sc) 236 { 237 uint32_t reg; 238 239 /* Get the status from both registers. */ 240 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0); 241 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1); 242 243 return (reg); 244 } 245 246 static device_t 247 ti_gpio_get_bus(device_t dev) 248 { 249 struct ti_gpio_softc *sc; 250 251 sc = device_get_softc(dev); 252 253 return (sc->sc_busdev); 254 } 255 256 /** 257 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 258 * @dev: gpio device handle 259 * @maxpin: pointer to a value that upon return will contain the maximum number 260 * of pins in the device. 261 * 262 * 263 * LOCKING: 264 * No locking required, returns static data. 265 * 266 * RETURNS: 267 * Returns 0 on success otherwise an error code 268 */ 269 static int 270 ti_gpio_pin_max(device_t dev, int *maxpin) 271 { 272 273 *maxpin = PINS_PER_BANK - 1; 274 275 return (0); 276 } 277 278 static int 279 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin) 280 { 281 282 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL) 283 return (EINVAL); 284 285 return (0); 286 } 287 288 /** 289 * ti_gpio_pin_getcaps - Gets the capabilities of a given pin 290 * @dev: gpio device handle 291 * @pin: the number of the pin 292 * @caps: pointer to a value that upon return will contain the capabilities 293 * 294 * Currently all pins have the same capability, notably: 295 * - GPIO_PIN_INPUT 296 * - GPIO_PIN_OUTPUT 297 * - GPIO_PIN_PULLUP 298 * - GPIO_PIN_PULLDOWN 299 * - GPIO_INTR_LEVEL_LOW 300 * - GPIO_INTR_LEVEL_HIGH 301 * - GPIO_INTR_EDGE_RISING 302 * - GPIO_INTR_EDGE_FALLING 303 * - GPIO_INTR_EDGE_BOTH 304 * 305 * LOCKING: 306 * No locking required, returns static data. 307 * 308 * RETURNS: 309 * Returns 0 on success otherwise an error code 310 */ 311 static int 312 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 313 { 314 struct ti_gpio_softc *sc; 315 316 sc = device_get_softc(dev); 317 if (ti_gpio_valid_pin(sc, pin) != 0) 318 return (EINVAL); 319 320 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP | 321 GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | 322 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | 323 GPIO_INTR_EDGE_BOTH); 324 325 return (0); 326 } 327 328 /** 329 * ti_gpio_pin_getflags - Gets the current flags of a given pin 330 * @dev: gpio device handle 331 * @pin: the number of the pin 332 * @flags: upon return will contain the current flags of the pin 333 * 334 * Reads the current flags of a given pin, here we actually read the H/W 335 * registers to determine the flags, rather than storing the value in the 336 * setflags call. 337 * 338 * LOCKING: 339 * Internally locks the context 340 * 341 * RETURNS: 342 * Returns 0 on success otherwise an error code 343 */ 344 static int 345 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 346 { 347 struct ti_gpio_softc *sc; 348 349 sc = device_get_softc(dev); 350 if (ti_gpio_valid_pin(sc, pin) != 0) 351 return (EINVAL); 352 353 /* Get the current pin state */ 354 TI_GPIO_LOCK(sc); 355 TI_GPIO_GET_FLAGS(dev, pin, flags); 356 TI_GPIO_UNLOCK(sc); 357 358 return (0); 359 } 360 361 /** 362 * ti_gpio_pin_getname - Gets the name of a given pin 363 * @dev: gpio device handle 364 * @pin: the number of the pin 365 * @name: buffer to put the name in 366 * 367 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 368 * of the pin. 369 * 370 * LOCKING: 371 * No locking required, returns static data. 372 * 373 * RETURNS: 374 * Returns 0 on success otherwise an error code 375 */ 376 static int 377 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 378 { 379 struct ti_gpio_softc *sc; 380 381 sc = device_get_softc(dev); 382 if (ti_gpio_valid_pin(sc, pin) != 0) 383 return (EINVAL); 384 385 /* Set a very simple name */ 386 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 387 name[GPIOMAXNAME - 1] = '\0'; 388 389 return (0); 390 } 391 392 /** 393 * ti_gpio_pin_setflags - Sets the flags for a given pin 394 * @dev: gpio device handle 395 * @pin: the number of the pin 396 * @flags: the flags to set 397 * 398 * The flags of the pin correspond to things like input/output mode, pull-ups, 399 * pull-downs, etc. This driver doesn't support all flags, only the following: 400 * - GPIO_PIN_INPUT 401 * - GPIO_PIN_OUTPUT 402 * - GPIO_PIN_PULLUP 403 * - GPIO_PIN_PULLDOWN 404 * 405 * LOCKING: 406 * Internally locks the context 407 * 408 * RETURNS: 409 * Returns 0 on success otherwise an error code 410 */ 411 static int 412 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 413 { 414 struct ti_gpio_softc *sc; 415 uint32_t oe; 416 417 sc = device_get_softc(dev); 418 if (ti_gpio_valid_pin(sc, pin) != 0) 419 return (EINVAL); 420 421 /* Set the GPIO mode and state */ 422 TI_GPIO_LOCK(sc); 423 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) { 424 TI_GPIO_UNLOCK(sc); 425 return (EINVAL); 426 } 427 428 /* If configuring as an output set the "output enable" bit */ 429 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 430 if (flags & GPIO_PIN_INPUT) 431 oe |= TI_GPIO_MASK(pin); 432 else 433 oe &= ~TI_GPIO_MASK(pin); 434 ti_gpio_write_4(sc, TI_GPIO_OE, oe); 435 TI_GPIO_UNLOCK(sc); 436 437 return (0); 438 } 439 440 /** 441 * ti_gpio_pin_set - Sets the current level on a GPIO pin 442 * @dev: gpio device handle 443 * @pin: the number of the pin 444 * @value: non-zero value will drive the pin high, otherwise the pin is 445 * driven low. 446 * 447 * 448 * LOCKING: 449 * Internally locks the context 450 * 451 * RETURNS: 452 * Returns 0 on success otherwise a error code 453 */ 454 static int 455 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 456 { 457 struct ti_gpio_softc *sc; 458 uint32_t reg; 459 460 sc = device_get_softc(dev); 461 if (ti_gpio_valid_pin(sc, pin) != 0) 462 return (EINVAL); 463 464 TI_GPIO_LOCK(sc); 465 if (value == GPIO_PIN_LOW) 466 reg = TI_GPIO_CLEARDATAOUT; 467 else 468 reg = TI_GPIO_SETDATAOUT; 469 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 470 TI_GPIO_UNLOCK(sc); 471 472 return (0); 473 } 474 475 /** 476 * ti_gpio_pin_get - Gets the current level on a GPIO pin 477 * @dev: gpio device handle 478 * @pin: the number of the pin 479 * @value: pointer to a value that upond return will contain the pin value 480 * 481 * The pin must be configured as an input pin beforehand, otherwise this 482 * function will fail. 483 * 484 * LOCKING: 485 * Internally locks the context 486 * 487 * RETURNS: 488 * Returns 0 on success otherwise a error code 489 */ 490 static int 491 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 492 { 493 struct ti_gpio_softc *sc; 494 uint32_t oe, reg, val; 495 496 sc = device_get_softc(dev); 497 if (ti_gpio_valid_pin(sc, pin) != 0) 498 return (EINVAL); 499 500 /* 501 * Return data from output latch when set as output and from the 502 * input register otherwise. 503 */ 504 TI_GPIO_LOCK(sc); 505 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 506 if (oe & TI_GPIO_MASK(pin)) 507 reg = TI_GPIO_DATAIN; 508 else 509 reg = TI_GPIO_DATAOUT; 510 val = ti_gpio_read_4(sc, reg); 511 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0; 512 TI_GPIO_UNLOCK(sc); 513 514 return (0); 515 } 516 517 /** 518 * ti_gpio_pin_toggle - Toggles a given GPIO pin 519 * @dev: gpio device handle 520 * @pin: the number of the pin 521 * 522 * 523 * LOCKING: 524 * Internally locks the context 525 * 526 * RETURNS: 527 * Returns 0 on success otherwise a error code 528 */ 529 static int 530 ti_gpio_pin_toggle(device_t dev, uint32_t pin) 531 { 532 struct ti_gpio_softc *sc; 533 uint32_t reg, val; 534 535 sc = device_get_softc(dev); 536 if (ti_gpio_valid_pin(sc, pin) != 0) 537 return (EINVAL); 538 539 /* Toggle the pin */ 540 TI_GPIO_LOCK(sc); 541 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT); 542 if (val & TI_GPIO_MASK(pin)) 543 reg = TI_GPIO_CLEARDATAOUT; 544 else 545 reg = TI_GPIO_SETDATAOUT; 546 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 547 TI_GPIO_UNLOCK(sc); 548 549 return (0); 550 } 551 552 static int 553 ti_gpio_bank_init(device_t dev) 554 { 555 int pin; 556 struct ti_gpio_softc *sc; 557 uint32_t flags, reg_oe, reg_set, rev; 558 clk_ident_t clk; 559 560 sc = device_get_softc(dev); 561 562 /* Enable the interface and functional clocks for the module. */ 563 clk = ti_hwmods_get_clock(dev); 564 if (clk == INVALID_CLK_IDENT) { 565 device_printf(dev, "failed to get device id based on ti,hwmods\n"); 566 return (EINVAL); 567 } 568 569 sc->sc_bank = clk - GPIO1_CLK + ti_first_gpio_bank(); 570 ti_prcm_clk_enable(clk); 571 572 /* 573 * Read the revision number of the module. TI don't publish the 574 * actual revision numbers, so instead the values have been 575 * determined by experimentation. 576 */ 577 rev = ti_gpio_read_4(sc, TI_GPIO_REVISION); 578 579 /* Check the revision. */ 580 if (rev != ti_gpio_rev()) { 581 device_printf(dev, "Warning: could not determine the revision " 582 "of GPIO module (revision:0x%08x)\n", rev); 583 return (EINVAL); 584 } 585 586 /* Disable interrupts for all pins. */ 587 ti_gpio_intr_clr(sc, 0xffffffff); 588 589 /* Init OE register based on pads configuration. */ 590 reg_oe = 0xffffffff; 591 reg_set = 0; 592 for (pin = 0; pin < PINS_PER_BANK; pin++) { 593 TI_GPIO_GET_FLAGS(dev, pin, &flags); 594 if (flags & GPIO_PIN_OUTPUT) { 595 reg_oe &= ~(1UL << pin); 596 if (flags & GPIO_PIN_PULLUP) 597 reg_set |= (1UL << pin); 598 } 599 } 600 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe); 601 if (reg_set) 602 ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set); 603 604 return (0); 605 } 606 607 /** 608 * ti_gpio_attach - attach function for the driver 609 * @dev: gpio device handle 610 * 611 * Allocates and sets up the driver context for all GPIO banks. This function 612 * expects the memory ranges and IRQs to already be allocated to the driver. 613 * 614 * LOCKING: 615 * None 616 * 617 * RETURNS: 618 * Always returns 0 619 */ 620 static int 621 ti_gpio_attach(device_t dev) 622 { 623 struct ti_gpio_softc *sc; 624 int err; 625 626 sc = device_get_softc(dev); 627 sc->sc_dev = dev; 628 TI_GPIO_LOCK_INIT(sc); 629 ti_gpio_pin_max(dev, &sc->sc_maxpin); 630 sc->sc_maxpin++; 631 632 sc->sc_mem_rid = 0; 633 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 634 &sc->sc_mem_rid, RF_ACTIVE); 635 if (!sc->sc_mem_res) { 636 device_printf(dev, "Error: could not allocate mem resources\n"); 637 ti_gpio_detach(dev); 638 return (ENXIO); 639 } 640 641 sc->sc_irq_rid = 0; 642 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 643 &sc->sc_irq_rid, RF_ACTIVE); 644 if (!sc->sc_irq_res) { 645 device_printf(dev, "Error: could not allocate irq resources\n"); 646 ti_gpio_detach(dev); 647 return (ENXIO); 648 } 649 650 /* 651 * Register our interrupt filter for each of the IRQ resources. 652 */ 653 if (bus_setup_intr(dev, sc->sc_irq_res, 654 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc, 655 &sc->sc_irq_hdl) != 0) { 656 device_printf(dev, 657 "WARNING: unable to register interrupt filter\n"); 658 ti_gpio_detach(dev); 659 return (ENXIO); 660 } 661 662 if (ti_gpio_pic_attach(sc) != 0) { 663 device_printf(dev, "WARNING: unable to attach PIC\n"); 664 ti_gpio_detach(dev); 665 return (ENXIO); 666 } 667 668 /* We need to go through each block and ensure the clocks are running and 669 * the module is enabled. It might be better to do this only when the 670 * pins are configured which would result in less power used if the GPIO 671 * pins weren't used ... 672 */ 673 if (sc->sc_mem_res != NULL) { 674 /* Initialize the GPIO module. */ 675 err = ti_gpio_bank_init(dev); 676 if (err != 0) { 677 ti_gpio_detach(dev); 678 return (err); 679 } 680 } 681 682 sc->sc_busdev = gpiobus_attach_bus(dev); 683 if (sc->sc_busdev == NULL) { 684 ti_gpio_detach(dev); 685 return (ENXIO); 686 } 687 688 return (0); 689 } 690 691 /** 692 * ti_gpio_detach - detach function for the driver 693 * @dev: scm device handle 694 * 695 * Allocates and sets up the driver context, this simply entails creating a 696 * bus mappings for the SCM register set. 697 * 698 * LOCKING: 699 * None 700 * 701 * RETURNS: 702 * Always returns 0 703 */ 704 static int 705 ti_gpio_detach(device_t dev) 706 { 707 struct ti_gpio_softc *sc = device_get_softc(dev); 708 709 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 710 711 /* Disable all interrupts */ 712 if (sc->sc_mem_res != NULL) 713 ti_gpio_intr_clr(sc, 0xffffffff); 714 gpiobus_detach_bus(dev); 715 if (sc->sc_isrcs != NULL) 716 ti_gpio_pic_detach(sc); 717 /* Release the memory and IRQ resources. */ 718 if (sc->sc_irq_hdl) { 719 bus_teardown_intr(dev, sc->sc_irq_res, 720 sc->sc_irq_hdl); 721 } 722 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 723 sc->sc_irq_res); 724 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 725 sc->sc_mem_res); 726 TI_GPIO_LOCK_DESTROY(sc); 727 728 return (0); 729 } 730 731 static inline void 732 ti_gpio_rwreg_modify(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask, 733 bool set_bits) 734 { 735 uint32_t value; 736 737 value = ti_gpio_read_4(sc, reg); 738 ti_gpio_write_4(sc, reg, set_bits ? value | mask : value & ~mask); 739 } 740 741 static inline void 742 ti_gpio_isrc_mask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 743 { 744 745 /* Writing a 0 has no effect. */ 746 ti_gpio_intr_clr(sc, tgi->tgi_mask); 747 } 748 749 static inline void 750 ti_gpio_isrc_unmask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 751 { 752 753 /* Writing a 0 has no effect. */ 754 ti_gpio_intr_set(sc, tgi->tgi_mask); 755 } 756 757 static inline void 758 ti_gpio_isrc_eoi(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 759 { 760 761 /* Writing a 0 has no effect. */ 762 ti_gpio_intr_ack(sc, tgi->tgi_mask); 763 } 764 765 static inline bool 766 ti_gpio_isrc_is_level(struct ti_gpio_irqsrc *tgi) 767 { 768 769 return (tgi->tgi_mode == GPIO_INTR_LEVEL_LOW || 770 tgi->tgi_mode == GPIO_INTR_LEVEL_HIGH); 771 } 772 773 static int 774 ti_gpio_intr(void *arg) 775 { 776 u_int irq; 777 uint32_t reg; 778 struct ti_gpio_softc *sc; 779 struct trapframe *tf; 780 struct ti_gpio_irqsrc *tgi; 781 782 sc = (struct ti_gpio_softc *)arg; 783 tf = curthread->td_intr_frame; 784 785 reg = ti_gpio_intr_status(sc); 786 for (irq = 0; irq < sc->sc_maxpin; irq++) { 787 tgi = &sc->sc_isrcs[irq]; 788 if ((reg & tgi->tgi_mask) == 0) 789 continue; 790 if (!ti_gpio_isrc_is_level(tgi)) 791 ti_gpio_isrc_eoi(sc, tgi); 792 if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) { 793 ti_gpio_isrc_mask(sc, tgi); 794 if (ti_gpio_isrc_is_level(tgi)) 795 ti_gpio_isrc_eoi(sc, tgi); 796 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 797 irq); 798 } 799 } 800 return (FILTER_HANDLED); 801 } 802 803 static int 804 ti_gpio_pic_attach(struct ti_gpio_softc *sc) 805 { 806 int error; 807 uint32_t irq; 808 const char *name; 809 810 sc->sc_isrcs = malloc(sizeof(*sc->sc_isrcs) * sc->sc_maxpin, M_DEVBUF, 811 M_WAITOK | M_ZERO); 812 813 name = device_get_nameunit(sc->sc_dev); 814 for (irq = 0; irq < sc->sc_maxpin; irq++) { 815 sc->sc_isrcs[irq].tgi_irq = irq; 816 sc->sc_isrcs[irq].tgi_mask = TI_GPIO_MASK(irq); 817 sc->sc_isrcs[irq].tgi_mode = GPIO_INTR_CONFORM; 818 819 error = intr_isrc_register(&sc->sc_isrcs[irq].tgi_isrc, 820 sc->sc_dev, 0, "%s,%u", name, irq); 821 if (error != 0) 822 return (error); /* XXX deregister ISRCs */ 823 } 824 if (intr_pic_register(sc->sc_dev, 825 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL) 826 return (ENXIO); 827 828 return (0); 829 } 830 831 static int 832 ti_gpio_pic_detach(struct ti_gpio_softc *sc) 833 { 834 835 /* 836 * There has not been established any procedure yet 837 * how to detach PIC from living system correctly. 838 */ 839 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 840 return (EBUSY); 841 } 842 843 static void 844 ti_gpio_pic_config_intr(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi, 845 uint32_t mode) 846 { 847 848 TI_GPIO_LOCK(sc); 849 ti_gpio_rwreg_modify(sc, TI_GPIO_RISINGDETECT, tgi->tgi_mask, 850 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH); 851 ti_gpio_rwreg_modify(sc, TI_GPIO_FALLINGDETECT, tgi->tgi_mask, 852 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH); 853 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT1, tgi->tgi_mask, 854 mode == GPIO_INTR_LEVEL_HIGH); 855 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT0, tgi->tgi_mask, 856 mode == GPIO_INTR_LEVEL_LOW); 857 tgi->tgi_mode = mode; 858 TI_GPIO_UNLOCK(sc); 859 } 860 861 static void 862 ti_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 863 { 864 struct ti_gpio_softc *sc = device_get_softc(dev); 865 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 866 867 ti_gpio_isrc_mask(sc, tgi); 868 } 869 870 static void 871 ti_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 872 { 873 struct ti_gpio_softc *sc = device_get_softc(dev); 874 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 875 876 arm_irq_memory_barrier(tgi->tgi_irq); 877 ti_gpio_isrc_unmask(sc, tgi); 878 } 879 880 static int 881 ti_gpio_pic_map_fdt(struct ti_gpio_softc *sc, struct intr_map_data_fdt *daf, 882 u_int *irqp, uint32_t *modep) 883 { 884 uint32_t mode; 885 886 /* 887 * The first cell is the interrupt number. 888 * The second cell is used to specify flags: 889 * bits[3:0] trigger type and level flags: 890 * 1 = low-to-high edge triggered. 891 * 2 = high-to-low edge triggered. 892 * 4 = active high level-sensitive. 893 * 8 = active low level-sensitive. 894 */ 895 if (daf->ncells != 2 || daf->cells[0] >= sc->sc_maxpin) 896 return (EINVAL); 897 898 /* Only reasonable modes are supported. */ 899 if (daf->cells[1] == 1) 900 mode = GPIO_INTR_EDGE_RISING; 901 else if (daf->cells[1] == 2) 902 mode = GPIO_INTR_EDGE_FALLING; 903 else if (daf->cells[1] == 3) 904 mode = GPIO_INTR_EDGE_BOTH; 905 else if (daf->cells[1] == 4) 906 mode = GPIO_INTR_LEVEL_HIGH; 907 else if (daf->cells[1] == 8) 908 mode = GPIO_INTR_LEVEL_LOW; 909 else 910 return (EINVAL); 911 912 *irqp = daf->cells[0]; 913 if (modep != NULL) 914 *modep = mode; 915 return (0); 916 } 917 918 static int 919 ti_gpio_pic_map_gpio(struct ti_gpio_softc *sc, struct intr_map_data_gpio *dag, 920 u_int *irqp, uint32_t *modep) 921 { 922 uint32_t mode; 923 924 if (dag->gpio_pin_num >= sc->sc_maxpin) 925 return (EINVAL); 926 927 mode = dag->gpio_intr_mode; 928 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH && 929 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING && 930 mode != GPIO_INTR_EDGE_BOTH) 931 return (EINVAL); 932 933 *irqp = dag->gpio_pin_num; 934 if (modep != NULL) 935 *modep = mode; 936 return (0); 937 } 938 939 static int 940 ti_gpio_pic_map(struct ti_gpio_softc *sc, struct intr_map_data *data, 941 u_int *irqp, uint32_t *modep) 942 { 943 944 switch (data->type) { 945 case INTR_MAP_DATA_FDT: 946 return (ti_gpio_pic_map_fdt(sc, 947 (struct intr_map_data_fdt *)data, irqp, modep)); 948 case INTR_MAP_DATA_GPIO: 949 return (ti_gpio_pic_map_gpio(sc, 950 (struct intr_map_data_gpio *)data, irqp, modep)); 951 default: 952 return (ENOTSUP); 953 } 954 } 955 956 static int 957 ti_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 958 struct intr_irqsrc **isrcp) 959 { 960 int error; 961 u_int irq; 962 struct ti_gpio_softc *sc = device_get_softc(dev); 963 964 error = ti_gpio_pic_map(sc, data, &irq, NULL); 965 if (error == 0) 966 *isrcp = &sc->sc_isrcs[irq].tgi_isrc; 967 return (error); 968 } 969 970 static void 971 ti_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 972 { 973 struct ti_gpio_softc *sc = device_get_softc(dev); 974 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 975 976 if (ti_gpio_isrc_is_level(tgi)) 977 ti_gpio_isrc_eoi(sc, tgi); 978 } 979 980 static void 981 ti_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 982 { 983 984 ti_gpio_pic_enable_intr(dev, isrc); 985 } 986 987 static void 988 ti_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 989 { 990 struct ti_gpio_softc *sc = device_get_softc(dev); 991 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 992 993 ti_gpio_isrc_mask(sc, tgi); 994 if (ti_gpio_isrc_is_level(tgi)) 995 ti_gpio_isrc_eoi(sc, tgi); 996 } 997 998 static int 999 ti_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1000 struct resource *res, struct intr_map_data *data) 1001 { 1002 u_int irq; 1003 uint32_t mode; 1004 struct ti_gpio_softc *sc; 1005 struct ti_gpio_irqsrc *tgi; 1006 1007 if (data == NULL) 1008 return (ENOTSUP); 1009 1010 sc = device_get_softc(dev); 1011 tgi = (struct ti_gpio_irqsrc *)isrc; 1012 1013 /* Get and check config for an interrupt. */ 1014 if (ti_gpio_pic_map(sc, data, &irq, &mode) != 0 || tgi->tgi_irq != irq) 1015 return (EINVAL); 1016 1017 /* 1018 * If this is a setup for another handler, 1019 * only check that its configuration match. 1020 */ 1021 if (isrc->isrc_handlers != 0) 1022 return (tgi->tgi_mode == mode ? 0 : EINVAL); 1023 1024 ti_gpio_pic_config_intr(sc, tgi, mode); 1025 return (0); 1026 } 1027 1028 static int 1029 ti_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1030 struct resource *res, struct intr_map_data *data) 1031 { 1032 struct ti_gpio_softc *sc = device_get_softc(dev); 1033 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1034 1035 if (isrc->isrc_handlers == 0) 1036 ti_gpio_pic_config_intr(sc, tgi, GPIO_INTR_CONFORM); 1037 return (0); 1038 } 1039 1040 static phandle_t 1041 ti_gpio_get_node(device_t bus, device_t dev) 1042 { 1043 1044 /* We only have one child, the GPIO bus, which needs our own node. */ 1045 return (ofw_bus_get_node(bus)); 1046 } 1047 1048 static device_method_t ti_gpio_methods[] = { 1049 DEVMETHOD(device_attach, ti_gpio_attach), 1050 DEVMETHOD(device_detach, ti_gpio_detach), 1051 1052 /* GPIO protocol */ 1053 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus), 1054 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 1055 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 1056 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 1057 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 1058 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 1059 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 1060 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 1061 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 1062 1063 /* Interrupt controller interface */ 1064 DEVMETHOD(pic_disable_intr, ti_gpio_pic_disable_intr), 1065 DEVMETHOD(pic_enable_intr, ti_gpio_pic_enable_intr), 1066 DEVMETHOD(pic_map_intr, ti_gpio_pic_map_intr), 1067 DEVMETHOD(pic_setup_intr, ti_gpio_pic_setup_intr), 1068 DEVMETHOD(pic_teardown_intr, ti_gpio_pic_teardown_intr), 1069 DEVMETHOD(pic_post_filter, ti_gpio_pic_post_filter), 1070 DEVMETHOD(pic_post_ithread, ti_gpio_pic_post_ithread), 1071 DEVMETHOD(pic_pre_ithread, ti_gpio_pic_pre_ithread), 1072 1073 /* ofw_bus interface */ 1074 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 1075 1076 {0, 0}, 1077 }; 1078 1079 driver_t ti_gpio_driver = { 1080 "gpio", 1081 ti_gpio_methods, 1082 sizeof(struct ti_gpio_softc), 1083 }; 1084