1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 5 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /** 31 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code 32 * here uses 0-5. 33 */ 34 35 #include <sys/cdefs.h> 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/proc.h> 45 #include <sys/rman.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/gpio.h> 49 #include <sys/interrupt.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 #include <machine/resource.h> 54 55 #include <arm/ti/ti_cpuid.h> 56 #include <arm/ti/ti_gpio.h> 57 #include <arm/ti/ti_scm.h> 58 #include <arm/ti/ti_sysc.h> 59 60 #include <dev/gpio/gpiobusvar.h> 61 #include <dev/ofw/openfirm.h> 62 #include <dev/ofw/ofw_bus.h> 63 #include <dev/ofw/ofw_bus_subr.h> 64 65 #include "gpio_if.h" 66 #include "ti_gpio_if.h" 67 #include "pic_if.h" 68 69 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X) 70 #error "Unknown SoC" 71 #endif 72 73 /* Register definitions */ 74 #define TI_GPIO_REVISION 0x0000 75 #define TI_GPIO_SYSCONFIG 0x0010 76 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024 77 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028 78 #define TI_GPIO_IRQSTATUS_0 0x002C /* writing a 0 has no effect */ 79 #define TI_GPIO_IRQSTATUS_1 0x0030 /* writing a 0 has no effect */ 80 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 /* writing a 0 has no effect */ 81 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 /* writing a 0 has no effect */ 82 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C /* writing a 0 has no effect */ 83 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 /* writing a 0 has no effect */ 84 #define TI_GPIO_IRQWAKEN_0 0x0044 85 #define TI_GPIO_IRQWAKEN_1 0x0048 86 #define TI_GPIO_SYSSTATUS 0x0114 87 #define TI_GPIO_IRQSTATUS1 0x0118 88 #define TI_GPIO_IRQENABLE1 0x011C 89 #define TI_GPIO_WAKEUPENABLE 0x0120 90 #define TI_GPIO_IRQSTATUS2 0x0128 91 #define TI_GPIO_IRQENABLE2 0x012C 92 #define TI_GPIO_CTRL 0x0130 93 #define TI_GPIO_OE 0x0134 94 #define TI_GPIO_DATAIN 0x0138 95 #define TI_GPIO_DATAOUT 0x013C 96 #define TI_GPIO_LEVELDETECT0 0x0140 /* RW register */ 97 #define TI_GPIO_LEVELDETECT1 0x0144 /* RW register */ 98 #define TI_GPIO_RISINGDETECT 0x0148 /* RW register */ 99 #define TI_GPIO_FALLINGDETECT 0x014C /* RW register */ 100 #define TI_GPIO_DEBOUNCENABLE 0x0150 101 #define TI_GPIO_DEBOUNCINGTIME 0x0154 102 #define TI_GPIO_CLEARWKUPENA 0x0180 103 #define TI_GPIO_SETWKUENA 0x0184 104 #define TI_GPIO_CLEARDATAOUT 0x0190 105 #define TI_GPIO_SETDATAOUT 0x0194 106 107 /* Other SoC Specific definitions */ 108 #define OMAP4_FIRST_GPIO_BANK 1 109 #define OMAP4_INTR_PER_BANK 1 110 #define OMAP4_GPIO_REV 0x50600801 111 #define AM335X_FIRST_GPIO_BANK 0 112 #define AM335X_INTR_PER_BANK 2 113 #define AM335X_GPIO_REV 0x50600801 114 #define PINS_PER_BANK 32 115 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK)) 116 117 #define OMAP4_GPIO1_REV 0x00000 118 #define OMAP4_GPIO2_REV 0x55000 119 #define OMAP4_GPIO3_REV 0x57000 120 #define OMAP4_GPIO4_REV 0x59000 121 #define OMAP4_GPIO5_REV 0x5b000 122 #define OMAP4_GPIO6_REV 0x5d000 123 124 #define AM335X_GPIO0_REV 0x07000 125 #define AM335X_GPIO1_REV 0x4C000 126 #define AM335X_GPIO2_REV 0xAC000 127 #define AM335X_GPIO3_REV 0xAE000 128 129 static int ti_gpio_intr(void *arg); 130 static int ti_gpio_detach(device_t); 131 132 static int ti_gpio_pic_attach(struct ti_gpio_softc *sc); 133 static int ti_gpio_pic_detach(struct ti_gpio_softc *sc); 134 135 static uint32_t 136 ti_gpio_rev(void) 137 { 138 switch(ti_chip()) { 139 #ifdef SOC_OMAP4 140 case CHIP_OMAP_4: 141 return (OMAP4_GPIO_REV); 142 #endif 143 #ifdef SOC_TI_AM335X 144 case CHIP_AM335X: 145 return (AM335X_GPIO_REV); 146 #endif 147 } 148 return (0); 149 } 150 151 /** 152 * Macros for driver mutex locking 153 */ 154 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 155 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 156 #define TI_GPIO_LOCK_INIT(_sc) \ 157 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 158 "ti_gpio", MTX_SPIN) 159 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 160 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 161 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 162 163 /** 164 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers 165 * @sc: GPIO device context 166 * @bank: The bank to read from 167 * @off: The offset of a register from the GPIO register address range 168 * 169 * 170 * RETURNS: 171 * 32-bit value read from the register. 172 */ 173 static inline uint32_t 174 ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off) 175 { 176 return (bus_read_4(sc->sc_mem_res, off)); 177 } 178 179 /** 180 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers 181 * @sc: GPIO device context 182 * @bank: The bank to write to 183 * @off: The offset of a register from the GPIO register address range 184 * @val: The value to write into the register 185 * 186 * RETURNS: 187 * nothing 188 */ 189 static inline void 190 ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off, 191 uint32_t val) 192 { 193 bus_write_4(sc->sc_mem_res, off, val); 194 } 195 196 static inline void 197 ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask) 198 { 199 200 /* We clear both set of registers. */ 201 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask); 202 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask); 203 } 204 205 static inline void 206 ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask) 207 { 208 209 /* 210 * On OMAP4 we unmask only the MPU interrupt and on AM335x we 211 * also activate only the first interrupt. 212 */ 213 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask); 214 } 215 216 static inline void 217 ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask) 218 { 219 220 /* 221 * Acknowledge the interrupt on both registers even if we use only 222 * the first one. 223 */ 224 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask); 225 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask); 226 } 227 228 static inline uint32_t 229 ti_gpio_intr_status(struct ti_gpio_softc *sc) 230 { 231 uint32_t reg; 232 233 /* Get the status from both registers. */ 234 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0); 235 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1); 236 237 return (reg); 238 } 239 240 static device_t 241 ti_gpio_get_bus(device_t dev) 242 { 243 struct ti_gpio_softc *sc; 244 245 sc = device_get_softc(dev); 246 247 return (sc->sc_busdev); 248 } 249 250 /** 251 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 252 * @dev: gpio device handle 253 * @maxpin: pointer to a value that upon return will contain the maximum number 254 * of pins in the device. 255 * 256 * 257 * LOCKING: 258 * No locking required, returns static data. 259 * 260 * RETURNS: 261 * Returns 0 on success otherwise an error code 262 */ 263 static int 264 ti_gpio_pin_max(device_t dev, int *maxpin) 265 { 266 267 *maxpin = PINS_PER_BANK - 1; 268 269 return (0); 270 } 271 272 static int 273 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin) 274 { 275 276 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL) 277 return (EINVAL); 278 279 return (0); 280 } 281 282 /** 283 * ti_gpio_pin_getcaps - Gets the capabilities of a given pin 284 * @dev: gpio device handle 285 * @pin: the number of the pin 286 * @caps: pointer to a value that upon return will contain the capabilities 287 * 288 * Currently all pins have the same capability, notably: 289 * - GPIO_PIN_INPUT 290 * - GPIO_PIN_OUTPUT 291 * - GPIO_PIN_PULLUP 292 * - GPIO_PIN_PULLDOWN 293 * - GPIO_INTR_LEVEL_LOW 294 * - GPIO_INTR_LEVEL_HIGH 295 * - GPIO_INTR_EDGE_RISING 296 * - GPIO_INTR_EDGE_FALLING 297 * - GPIO_INTR_EDGE_BOTH 298 * 299 * LOCKING: 300 * No locking required, returns static data. 301 * 302 * RETURNS: 303 * Returns 0 on success otherwise an error code 304 */ 305 static int 306 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 307 { 308 struct ti_gpio_softc *sc; 309 310 sc = device_get_softc(dev); 311 if (ti_gpio_valid_pin(sc, pin) != 0) 312 return (EINVAL); 313 314 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP | 315 GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | 316 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | 317 GPIO_INTR_EDGE_BOTH); 318 319 return (0); 320 } 321 322 /** 323 * ti_gpio_pin_getflags - Gets the current flags of a given pin 324 * @dev: gpio device handle 325 * @pin: the number of the pin 326 * @flags: upon return will contain the current flags of the pin 327 * 328 * Reads the current flags of a given pin, here we actually read the H/W 329 * registers to determine the flags, rather than storing the value in the 330 * setflags call. 331 * 332 * LOCKING: 333 * Internally locks the context 334 * 335 * RETURNS: 336 * Returns 0 on success otherwise an error code 337 */ 338 static int 339 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 340 { 341 struct ti_gpio_softc *sc; 342 343 sc = device_get_softc(dev); 344 if (ti_gpio_valid_pin(sc, pin) != 0) 345 return (EINVAL); 346 347 /* Get the current pin state */ 348 TI_GPIO_LOCK(sc); 349 TI_GPIO_GET_FLAGS(dev, pin, flags); 350 TI_GPIO_UNLOCK(sc); 351 352 return (0); 353 } 354 355 /** 356 * ti_gpio_pin_getname - Gets the name of a given pin 357 * @dev: gpio device handle 358 * @pin: the number of the pin 359 * @name: buffer to put the name in 360 * 361 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 362 * of the pin. 363 * 364 * LOCKING: 365 * No locking required, returns static data. 366 * 367 * RETURNS: 368 * Returns 0 on success otherwise an error code 369 */ 370 static int 371 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 372 { 373 struct ti_gpio_softc *sc; 374 375 sc = device_get_softc(dev); 376 if (ti_gpio_valid_pin(sc, pin) != 0) 377 return (EINVAL); 378 379 /* Set a very simple name */ 380 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 381 name[GPIOMAXNAME - 1] = '\0'; 382 383 return (0); 384 } 385 386 /** 387 * ti_gpio_pin_setflags - Sets the flags for a given pin 388 * @dev: gpio device handle 389 * @pin: the number of the pin 390 * @flags: the flags to set 391 * 392 * The flags of the pin correspond to things like input/output mode, pull-ups, 393 * pull-downs, etc. This driver doesn't support all flags, only the following: 394 * - GPIO_PIN_INPUT 395 * - GPIO_PIN_OUTPUT 396 * - GPIO_PIN_PULLUP 397 * - GPIO_PIN_PULLDOWN 398 * 399 * LOCKING: 400 * Internally locks the context 401 * 402 * RETURNS: 403 * Returns 0 on success otherwise an error code 404 */ 405 static int 406 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 407 { 408 struct ti_gpio_softc *sc; 409 uint32_t oe; 410 411 sc = device_get_softc(dev); 412 if (ti_gpio_valid_pin(sc, pin) != 0) 413 return (EINVAL); 414 415 /* Set the GPIO mode and state */ 416 TI_GPIO_LOCK(sc); 417 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) { 418 TI_GPIO_UNLOCK(sc); 419 return (EINVAL); 420 } 421 422 /* If configuring as an output set the "output enable" bit */ 423 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 424 if (flags & GPIO_PIN_INPUT) 425 oe |= TI_GPIO_MASK(pin); 426 else 427 oe &= ~TI_GPIO_MASK(pin); 428 ti_gpio_write_4(sc, TI_GPIO_OE, oe); 429 TI_GPIO_UNLOCK(sc); 430 431 return (0); 432 } 433 434 /** 435 * ti_gpio_pin_set - Sets the current level on a GPIO pin 436 * @dev: gpio device handle 437 * @pin: the number of the pin 438 * @value: non-zero value will drive the pin high, otherwise the pin is 439 * driven low. 440 * 441 * 442 * LOCKING: 443 * Internally locks the context 444 * 445 * RETURNS: 446 * Returns 0 on success otherwise a error code 447 */ 448 static int 449 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 450 { 451 struct ti_gpio_softc *sc; 452 uint32_t reg; 453 454 sc = device_get_softc(dev); 455 if (ti_gpio_valid_pin(sc, pin) != 0) 456 return (EINVAL); 457 458 TI_GPIO_LOCK(sc); 459 if (value == GPIO_PIN_LOW) 460 reg = TI_GPIO_CLEARDATAOUT; 461 else 462 reg = TI_GPIO_SETDATAOUT; 463 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 464 TI_GPIO_UNLOCK(sc); 465 466 return (0); 467 } 468 469 /** 470 * ti_gpio_pin_get - Gets the current level on a GPIO pin 471 * @dev: gpio device handle 472 * @pin: the number of the pin 473 * @value: pointer to a value that upond return will contain the pin value 474 * 475 * The pin must be configured as an input pin beforehand, otherwise this 476 * function will fail. 477 * 478 * LOCKING: 479 * Internally locks the context 480 * 481 * RETURNS: 482 * Returns 0 on success otherwise a error code 483 */ 484 static int 485 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 486 { 487 struct ti_gpio_softc *sc; 488 uint32_t oe, reg, val; 489 490 sc = device_get_softc(dev); 491 if (ti_gpio_valid_pin(sc, pin) != 0) 492 return (EINVAL); 493 494 /* 495 * Return data from output latch when set as output and from the 496 * input register otherwise. 497 */ 498 TI_GPIO_LOCK(sc); 499 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 500 if (oe & TI_GPIO_MASK(pin)) 501 reg = TI_GPIO_DATAIN; 502 else 503 reg = TI_GPIO_DATAOUT; 504 val = ti_gpio_read_4(sc, reg); 505 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0; 506 TI_GPIO_UNLOCK(sc); 507 508 return (0); 509 } 510 511 /** 512 * ti_gpio_pin_toggle - Toggles a given GPIO pin 513 * @dev: gpio device handle 514 * @pin: the number of the pin 515 * 516 * 517 * LOCKING: 518 * Internally locks the context 519 * 520 * RETURNS: 521 * Returns 0 on success otherwise a error code 522 */ 523 static int 524 ti_gpio_pin_toggle(device_t dev, uint32_t pin) 525 { 526 struct ti_gpio_softc *sc; 527 uint32_t reg, val; 528 529 sc = device_get_softc(dev); 530 if (ti_gpio_valid_pin(sc, pin) != 0) 531 return (EINVAL); 532 533 /* Toggle the pin */ 534 TI_GPIO_LOCK(sc); 535 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT); 536 if (val & TI_GPIO_MASK(pin)) 537 reg = TI_GPIO_CLEARDATAOUT; 538 else 539 reg = TI_GPIO_SETDATAOUT; 540 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 541 TI_GPIO_UNLOCK(sc); 542 543 return (0); 544 } 545 546 static int 547 ti_gpio_bank_init(device_t dev) 548 { 549 int pin, err; 550 struct ti_gpio_softc *sc; 551 uint32_t flags, reg_oe, reg_set, rev; 552 uint64_t rev_address; 553 554 sc = device_get_softc(dev); 555 556 /* Enable the interface and functional clocks for the module. */ 557 rev_address = ti_sysc_get_rev_address(device_get_parent(dev)); 558 /* AM335x 559 * sc->sc_bank used in am335x/am335x_gpio.c and omap4/omap4_gpio.c */ 560 switch(ti_chip()) { 561 #ifdef SOC_OMAP4 562 case CHIP_OMAP_4: 563 switch (rev_address) { 564 case OMAP4_GPIO1_REV: 565 sc->sc_bank = 0; 566 break; 567 case OMAP4_GPIO2_REV: 568 sc->sc_bank = 1; 569 break; 570 case OMAP4_GPIO3_REV: 571 sc->sc_bank = 2; 572 break; 573 case OMAP4_GPIO4_REV: 574 sc->sc_bank = 3; 575 break; 576 case OMAP4_GPIO5_REV: 577 sc->sc_bank = 4; 578 break; 579 case OMAP4_GPIO6_REV: 580 sc->sc_bank = 5; 581 break; 582 } 583 #endif 584 #ifdef SOC_TI_AM335X 585 case CHIP_AM335X: 586 switch (rev_address) { 587 case AM335X_GPIO0_REV: 588 sc->sc_bank = 0; 589 break; 590 case AM335X_GPIO1_REV: 591 sc->sc_bank = 1; 592 break; 593 case AM335X_GPIO2_REV: 594 sc->sc_bank = 2; 595 break; 596 case AM335X_GPIO3_REV: 597 sc->sc_bank = 3; 598 break; 599 } 600 #endif 601 } 602 err = ti_sysc_clock_enable(device_get_parent(dev)); 603 if (err) { 604 device_printf(dev, "Failed to enable clock\n"); 605 return (EINVAL); 606 } 607 608 /* 609 * Read the revision number of the module. TI don't publish the 610 * actual revision numbers, so instead the values have been 611 * determined by experimentation. 612 */ 613 rev = ti_gpio_read_4(sc, 614 ti_sysc_get_rev_address_offset_host(device_get_parent(dev))); 615 616 /* Check the revision. */ 617 if (rev != ti_gpio_rev()) { 618 device_printf(dev, "Warning: could not determine the revision " 619 "of GPIO module (revision:0x%08x)\n", rev); 620 return (EINVAL); 621 } 622 623 /* Disable interrupts for all pins. */ 624 ti_gpio_intr_clr(sc, 0xffffffff); 625 626 /* Init OE register based on pads configuration. */ 627 reg_oe = 0xffffffff; 628 reg_set = 0; 629 for (pin = 0; pin < PINS_PER_BANK; pin++) { 630 TI_GPIO_GET_FLAGS(dev, pin, &flags); 631 if (flags & GPIO_PIN_OUTPUT) { 632 reg_oe &= ~(1UL << pin); 633 if (flags & GPIO_PIN_PULLUP) 634 reg_set |= (1UL << pin); 635 } 636 } 637 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe); 638 if (reg_set) 639 ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set); 640 641 return (0); 642 } 643 644 /** 645 * ti_gpio_attach - attach function for the driver 646 * @dev: gpio device handle 647 * 648 * Allocates and sets up the driver context for all GPIO banks. This function 649 * expects the memory ranges and IRQs to already be allocated to the driver. 650 * 651 * LOCKING: 652 * None 653 * 654 * RETURNS: 655 * Always returns 0 656 */ 657 static int 658 ti_gpio_attach(device_t dev) 659 { 660 struct ti_gpio_softc *sc; 661 int err; 662 663 sc = device_get_softc(dev); 664 sc->sc_dev = dev; 665 TI_GPIO_LOCK_INIT(sc); 666 ti_gpio_pin_max(dev, &sc->sc_maxpin); 667 sc->sc_maxpin++; 668 669 sc->sc_mem_rid = 0; 670 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 671 &sc->sc_mem_rid, RF_ACTIVE); 672 if (!sc->sc_mem_res) { 673 device_printf(dev, "Error: could not allocate mem resources\n"); 674 ti_gpio_detach(dev); 675 return (ENXIO); 676 } 677 678 sc->sc_irq_rid = 0; 679 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 680 &sc->sc_irq_rid, RF_ACTIVE); 681 if (!sc->sc_irq_res) { 682 device_printf(dev, "Error: could not allocate irq resources\n"); 683 ti_gpio_detach(dev); 684 return (ENXIO); 685 } 686 687 /* 688 * Register our interrupt filter for each of the IRQ resources. 689 */ 690 if (bus_setup_intr(dev, sc->sc_irq_res, 691 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc, 692 &sc->sc_irq_hdl) != 0) { 693 device_printf(dev, 694 "WARNING: unable to register interrupt filter\n"); 695 ti_gpio_detach(dev); 696 return (ENXIO); 697 } 698 699 if (ti_gpio_pic_attach(sc) != 0) { 700 device_printf(dev, "WARNING: unable to attach PIC\n"); 701 ti_gpio_detach(dev); 702 return (ENXIO); 703 } 704 705 /* We need to go through each block and ensure the clocks are running and 706 * the module is enabled. It might be better to do this only when the 707 * pins are configured which would result in less power used if the GPIO 708 * pins weren't used ... 709 */ 710 if (sc->sc_mem_res != NULL) { 711 /* Initialize the GPIO module. */ 712 err = ti_gpio_bank_init(dev); 713 if (err != 0) { 714 ti_gpio_detach(dev); 715 return (err); 716 } 717 } 718 719 sc->sc_busdev = gpiobus_attach_bus(dev); 720 if (sc->sc_busdev == NULL) { 721 ti_gpio_detach(dev); 722 return (ENXIO); 723 } 724 725 return (0); 726 } 727 728 /** 729 * ti_gpio_detach - detach function for the driver 730 * @dev: scm device handle 731 * 732 * Allocates and sets up the driver context, this simply entails creating a 733 * bus mappings for the SCM register set. 734 * 735 * LOCKING: 736 * None 737 * 738 * RETURNS: 739 * Always returns 0 740 */ 741 static int 742 ti_gpio_detach(device_t dev) 743 { 744 struct ti_gpio_softc *sc = device_get_softc(dev); 745 746 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 747 748 /* Disable all interrupts */ 749 if (sc->sc_mem_res != NULL) 750 ti_gpio_intr_clr(sc, 0xffffffff); 751 if (sc->sc_busdev != NULL) 752 gpiobus_detach_bus(dev); 753 if (sc->sc_isrcs != NULL) 754 ti_gpio_pic_detach(sc); 755 /* Release the memory and IRQ resources. */ 756 if (sc->sc_irq_hdl) { 757 bus_teardown_intr(dev, sc->sc_irq_res, 758 sc->sc_irq_hdl); 759 } 760 if (sc->sc_irq_res) 761 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 762 sc->sc_irq_res); 763 if (sc->sc_mem_res) 764 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 765 sc->sc_mem_res); 766 TI_GPIO_LOCK_DESTROY(sc); 767 768 return (0); 769 } 770 771 static inline void 772 ti_gpio_rwreg_modify(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask, 773 bool set_bits) 774 { 775 uint32_t value; 776 777 value = ti_gpio_read_4(sc, reg); 778 ti_gpio_write_4(sc, reg, set_bits ? value | mask : value & ~mask); 779 } 780 781 static inline void 782 ti_gpio_isrc_mask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 783 { 784 785 /* Writing a 0 has no effect. */ 786 ti_gpio_intr_clr(sc, tgi->tgi_mask); 787 } 788 789 static inline void 790 ti_gpio_isrc_unmask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 791 { 792 793 /* Writing a 0 has no effect. */ 794 ti_gpio_intr_set(sc, tgi->tgi_mask); 795 } 796 797 static inline void 798 ti_gpio_isrc_eoi(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 799 { 800 801 /* Writing a 0 has no effect. */ 802 ti_gpio_intr_ack(sc, tgi->tgi_mask); 803 } 804 805 static inline bool 806 ti_gpio_isrc_is_level(struct ti_gpio_irqsrc *tgi) 807 { 808 809 return (tgi->tgi_mode == GPIO_INTR_LEVEL_LOW || 810 tgi->tgi_mode == GPIO_INTR_LEVEL_HIGH); 811 } 812 813 static int 814 ti_gpio_intr(void *arg) 815 { 816 u_int irq; 817 uint32_t reg; 818 struct ti_gpio_softc *sc; 819 struct trapframe *tf; 820 struct ti_gpio_irqsrc *tgi; 821 822 sc = (struct ti_gpio_softc *)arg; 823 tf = curthread->td_intr_frame; 824 825 reg = ti_gpio_intr_status(sc); 826 for (irq = 0; irq < sc->sc_maxpin; irq++) { 827 tgi = &sc->sc_isrcs[irq]; 828 if ((reg & tgi->tgi_mask) == 0) 829 continue; 830 if (!ti_gpio_isrc_is_level(tgi)) 831 ti_gpio_isrc_eoi(sc, tgi); 832 if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) { 833 ti_gpio_isrc_mask(sc, tgi); 834 if (ti_gpio_isrc_is_level(tgi)) 835 ti_gpio_isrc_eoi(sc, tgi); 836 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 837 irq); 838 } 839 } 840 return (FILTER_HANDLED); 841 } 842 843 static int 844 ti_gpio_pic_attach(struct ti_gpio_softc *sc) 845 { 846 int error; 847 uint32_t irq; 848 const char *name; 849 850 sc->sc_isrcs = malloc(sizeof(*sc->sc_isrcs) * sc->sc_maxpin, M_DEVBUF, 851 M_WAITOK | M_ZERO); 852 853 name = device_get_nameunit(sc->sc_dev); 854 for (irq = 0; irq < sc->sc_maxpin; irq++) { 855 sc->sc_isrcs[irq].tgi_irq = irq; 856 sc->sc_isrcs[irq].tgi_mask = TI_GPIO_MASK(irq); 857 sc->sc_isrcs[irq].tgi_mode = GPIO_INTR_CONFORM; 858 859 error = intr_isrc_register(&sc->sc_isrcs[irq].tgi_isrc, 860 sc->sc_dev, 0, "%s,%u", name, irq); 861 if (error != 0) 862 return (error); /* XXX deregister ISRCs */ 863 } 864 if (intr_pic_register(sc->sc_dev, 865 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL) 866 return (ENXIO); 867 868 return (0); 869 } 870 871 static int 872 ti_gpio_pic_detach(struct ti_gpio_softc *sc) 873 { 874 875 /* 876 * There has not been established any procedure yet 877 * how to detach PIC from living system correctly. 878 */ 879 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 880 return (EBUSY); 881 } 882 883 static void 884 ti_gpio_pic_config_intr(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi, 885 uint32_t mode) 886 { 887 888 TI_GPIO_LOCK(sc); 889 ti_gpio_rwreg_modify(sc, TI_GPIO_RISINGDETECT, tgi->tgi_mask, 890 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH); 891 ti_gpio_rwreg_modify(sc, TI_GPIO_FALLINGDETECT, tgi->tgi_mask, 892 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH); 893 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT1, tgi->tgi_mask, 894 mode == GPIO_INTR_LEVEL_HIGH); 895 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT0, tgi->tgi_mask, 896 mode == GPIO_INTR_LEVEL_LOW); 897 tgi->tgi_mode = mode; 898 TI_GPIO_UNLOCK(sc); 899 } 900 901 static void 902 ti_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 903 { 904 struct ti_gpio_softc *sc = device_get_softc(dev); 905 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 906 907 ti_gpio_isrc_mask(sc, tgi); 908 } 909 910 static void 911 ti_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 912 { 913 struct ti_gpio_softc *sc = device_get_softc(dev); 914 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 915 916 arm_irq_memory_barrier(tgi->tgi_irq); 917 ti_gpio_isrc_unmask(sc, tgi); 918 } 919 920 static int 921 ti_gpio_pic_map_fdt(struct ti_gpio_softc *sc, struct intr_map_data_fdt *daf, 922 u_int *irqp, uint32_t *modep) 923 { 924 uint32_t mode; 925 926 /* 927 * The first cell is the interrupt number. 928 * The second cell is used to specify flags: 929 * bits[3:0] trigger type and level flags: 930 * 1 = low-to-high edge triggered. 931 * 2 = high-to-low edge triggered. 932 * 4 = active high level-sensitive. 933 * 8 = active low level-sensitive. 934 */ 935 if (daf->ncells != 2 || daf->cells[0] >= sc->sc_maxpin) 936 return (EINVAL); 937 938 /* Only reasonable modes are supported. */ 939 if (daf->cells[1] == 1) 940 mode = GPIO_INTR_EDGE_RISING; 941 else if (daf->cells[1] == 2) 942 mode = GPIO_INTR_EDGE_FALLING; 943 else if (daf->cells[1] == 3) 944 mode = GPIO_INTR_EDGE_BOTH; 945 else if (daf->cells[1] == 4) 946 mode = GPIO_INTR_LEVEL_HIGH; 947 else if (daf->cells[1] == 8) 948 mode = GPIO_INTR_LEVEL_LOW; 949 else 950 return (EINVAL); 951 952 *irqp = daf->cells[0]; 953 if (modep != NULL) 954 *modep = mode; 955 return (0); 956 } 957 958 static int 959 ti_gpio_pic_map_gpio(struct ti_gpio_softc *sc, struct intr_map_data_gpio *dag, 960 u_int *irqp, uint32_t *modep) 961 { 962 uint32_t mode; 963 964 if (dag->gpio_pin_num >= sc->sc_maxpin) 965 return (EINVAL); 966 967 mode = dag->gpio_intr_mode; 968 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH && 969 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING && 970 mode != GPIO_INTR_EDGE_BOTH) 971 return (EINVAL); 972 973 *irqp = dag->gpio_pin_num; 974 if (modep != NULL) 975 *modep = mode; 976 return (0); 977 } 978 979 static int 980 ti_gpio_pic_map(struct ti_gpio_softc *sc, struct intr_map_data *data, 981 u_int *irqp, uint32_t *modep) 982 { 983 984 switch (data->type) { 985 case INTR_MAP_DATA_FDT: 986 return (ti_gpio_pic_map_fdt(sc, 987 (struct intr_map_data_fdt *)data, irqp, modep)); 988 case INTR_MAP_DATA_GPIO: 989 return (ti_gpio_pic_map_gpio(sc, 990 (struct intr_map_data_gpio *)data, irqp, modep)); 991 default: 992 return (ENOTSUP); 993 } 994 } 995 996 static int 997 ti_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 998 struct intr_irqsrc **isrcp) 999 { 1000 int error; 1001 u_int irq; 1002 struct ti_gpio_softc *sc = device_get_softc(dev); 1003 1004 error = ti_gpio_pic_map(sc, data, &irq, NULL); 1005 if (error == 0) 1006 *isrcp = &sc->sc_isrcs[irq].tgi_isrc; 1007 return (error); 1008 } 1009 1010 static void 1011 ti_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 1012 { 1013 struct ti_gpio_softc *sc = device_get_softc(dev); 1014 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1015 1016 if (ti_gpio_isrc_is_level(tgi)) 1017 ti_gpio_isrc_eoi(sc, tgi); 1018 } 1019 1020 static void 1021 ti_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 1022 { 1023 1024 ti_gpio_pic_enable_intr(dev, isrc); 1025 } 1026 1027 static void 1028 ti_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 1029 { 1030 struct ti_gpio_softc *sc = device_get_softc(dev); 1031 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1032 1033 ti_gpio_isrc_mask(sc, tgi); 1034 if (ti_gpio_isrc_is_level(tgi)) 1035 ti_gpio_isrc_eoi(sc, tgi); 1036 } 1037 1038 static int 1039 ti_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1040 struct resource *res, struct intr_map_data *data) 1041 { 1042 u_int irq; 1043 uint32_t mode; 1044 struct ti_gpio_softc *sc; 1045 struct ti_gpio_irqsrc *tgi; 1046 1047 if (data == NULL) 1048 return (ENOTSUP); 1049 1050 sc = device_get_softc(dev); 1051 tgi = (struct ti_gpio_irqsrc *)isrc; 1052 1053 /* Get and check config for an interrupt. */ 1054 if (ti_gpio_pic_map(sc, data, &irq, &mode) != 0 || tgi->tgi_irq != irq) 1055 return (EINVAL); 1056 1057 /* 1058 * If this is a setup for another handler, 1059 * only check that its configuration match. 1060 */ 1061 if (isrc->isrc_handlers != 0) 1062 return (tgi->tgi_mode == mode ? 0 : EINVAL); 1063 1064 ti_gpio_pic_config_intr(sc, tgi, mode); 1065 return (0); 1066 } 1067 1068 static int 1069 ti_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1070 struct resource *res, struct intr_map_data *data) 1071 { 1072 struct ti_gpio_softc *sc = device_get_softc(dev); 1073 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1074 1075 if (isrc->isrc_handlers == 0) 1076 ti_gpio_pic_config_intr(sc, tgi, GPIO_INTR_CONFORM); 1077 return (0); 1078 } 1079 1080 static phandle_t 1081 ti_gpio_get_node(device_t bus, device_t dev) 1082 { 1083 1084 /* We only have one child, the GPIO bus, which needs our own node. */ 1085 return (ofw_bus_get_node(bus)); 1086 } 1087 1088 static device_method_t ti_gpio_methods[] = { 1089 DEVMETHOD(device_attach, ti_gpio_attach), 1090 DEVMETHOD(device_detach, ti_gpio_detach), 1091 1092 /* GPIO protocol */ 1093 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus), 1094 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 1095 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 1096 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 1097 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 1098 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 1099 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 1100 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 1101 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 1102 1103 /* Interrupt controller interface */ 1104 DEVMETHOD(pic_disable_intr, ti_gpio_pic_disable_intr), 1105 DEVMETHOD(pic_enable_intr, ti_gpio_pic_enable_intr), 1106 DEVMETHOD(pic_map_intr, ti_gpio_pic_map_intr), 1107 DEVMETHOD(pic_setup_intr, ti_gpio_pic_setup_intr), 1108 DEVMETHOD(pic_teardown_intr, ti_gpio_pic_teardown_intr), 1109 DEVMETHOD(pic_post_filter, ti_gpio_pic_post_filter), 1110 DEVMETHOD(pic_post_ithread, ti_gpio_pic_post_ithread), 1111 DEVMETHOD(pic_pre_ithread, ti_gpio_pic_pre_ithread), 1112 1113 /* ofw_bus interface */ 1114 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 1115 1116 {0, 0}, 1117 }; 1118 1119 driver_t ti_gpio_driver = { 1120 "gpio", 1121 ti_gpio_methods, 1122 sizeof(struct ti_gpio_softc), 1123 }; 1124