1 /*- 2 * Copyright (c) 2011 3 * Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /** 29 * Very simple GPIO (general purpose IO) driver module for TI OMAP SoC's. 30 * 31 * Currently this driver only does the basics, get a value on a pin & set a 32 * value on a pin. Hopefully over time I'll expand this to be a bit more generic 33 * and support interrupts and other various bits on the SoC can do ... in the 34 * meantime this is all you get. 35 * 36 * Beware the OMA datasheet(s) lists GPIO banks 1-6, whereas I've used 0-5 here 37 * in the code. 38 * 39 * 40 */ 41 42 #include <sys/cdefs.h> 43 __FBSDID("$FreeBSD$"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/bus.h> 48 49 #include <sys/kernel.h> 50 #include <sys/module.h> 51 #include <sys/rman.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/gpio.h> 55 56 #include <machine/bus.h> 57 #include <machine/resource.h> 58 59 #include <arm/ti/ti_cpuid.h> 60 #include <arm/ti/ti_scm.h> 61 #include <arm/ti/ti_prcm.h> 62 63 #include <dev/fdt/fdt_common.h> 64 #include <dev/ofw/openfirm.h> 65 #include <dev/ofw/ofw_bus.h> 66 #include <dev/ofw/ofw_bus_subr.h> 67 68 #include "gpio_if.h" 69 70 /* Register definitions */ 71 #define TI_GPIO_REVISION 0x0000 72 #define TI_GPIO_SYSCONFIG 0x0010 73 #if defined(SOC_OMAP4) || defined(SOC_TI_AM335X) 74 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024 75 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028 76 #define TI_GPIO_IRQSTATUS_0 0x002C 77 #define TI_GPIO_IRQSTATUS_1 0x0030 78 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 79 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 80 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C 81 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 82 #define TI_GPIO_IRQWAKEN_0 0x0044 83 #define TI_GPIO_IRQWAKEN_1 0x0048 84 #define TI_GPIO_SYSSTATUS 0x0114 85 #define TI_GPIO_IRQSTATUS1 0x0118 86 #define TI_GPIO_IRQENABLE1 0x011C 87 #define TI_GPIO_WAKEUPENABLE 0x0120 88 #define TI_GPIO_IRQSTATUS2 0x0128 89 #define TI_GPIO_IRQENABLE2 0x012C 90 #define TI_GPIO_CTRL 0x0130 91 #define TI_GPIO_OE 0x0134 92 #define TI_GPIO_DATAIN 0x0138 93 #define TI_GPIO_DATAOUT 0x013C 94 #define TI_GPIO_LEVELDETECT0 0x0140 95 #define TI_GPIO_LEVELDETECT1 0x0144 96 #define TI_GPIO_RISINGDETECT 0x0148 97 #define TI_GPIO_FALLINGDETECT 0x014C 98 #define TI_GPIO_DEBOUNCENABLE 0x0150 99 #define TI_GPIO_DEBOUNCINGTIME 0x0154 100 #define TI_GPIO_CLEARWKUPENA 0x0180 101 #define TI_GPIO_SETWKUENA 0x0184 102 #define TI_GPIO_CLEARDATAOUT 0x0190 103 #define TI_GPIO_SETDATAOUT 0x0194 104 #else 105 #error "Unknown SoC" 106 #endif 107 108 /* Other SoC Specific definitions */ 109 #define OMAP4_MAX_GPIO_BANKS 6 110 #define OMAP4_FIRST_GPIO_BANK 1 111 #define OMAP4_INTR_PER_BANK 1 112 #define OMAP4_GPIO_REV 0x50600801 113 #define AM335X_MAX_GPIO_BANKS 4 114 #define AM335X_FIRST_GPIO_BANK 0 115 #define AM335X_INTR_PER_BANK 2 116 #define AM335X_GPIO_REV 0x50600801 117 #define PINS_PER_BANK 32 118 #define MAX_GPIO_BANKS 6 119 /* Maximum GPIOS possible, max of *_MAX_GPIO_BANKS * *_INTR_PER_BANK */ 120 #define MAX_GPIO_INTRS 8 121 122 static u_int 123 ti_max_gpio_banks(void) 124 { 125 switch(ti_chip()) { 126 #ifdef SOC_OMAP4 127 case CHIP_OMAP_4: 128 return (OMAP4_MAX_GPIO_BANKS); 129 #endif 130 #ifdef SOC_TI_AM335X 131 case CHIP_AM335X: 132 return (AM335X_MAX_GPIO_BANKS); 133 #endif 134 } 135 return (0); 136 } 137 138 static u_int 139 ti_max_gpio_intrs(void) 140 { 141 switch(ti_chip()) { 142 #ifdef SOC_OMAP4 143 case CHIP_OMAP_4: 144 return (OMAP4_MAX_GPIO_BANKS * OMAP4_INTR_PER_BANK); 145 #endif 146 #ifdef SOC_TI_AM335X 147 case CHIP_AM335X: 148 return (AM335X_MAX_GPIO_BANKS * AM335X_INTR_PER_BANK); 149 #endif 150 } 151 return (0); 152 } 153 154 static u_int 155 ti_first_gpio_bank(void) 156 { 157 switch(ti_chip()) { 158 #ifdef SOC_OMAP4 159 case CHIP_OMAP_4: 160 return (OMAP4_FIRST_GPIO_BANK); 161 #endif 162 #ifdef SOC_TI_AM335X 163 case CHIP_AM335X: 164 return (AM335X_FIRST_GPIO_BANK); 165 #endif 166 } 167 return (0); 168 } 169 170 static uint32_t 171 ti_gpio_rev(void) 172 { 173 switch(ti_chip()) { 174 #ifdef SOC_OMAP4 175 case CHIP_OMAP_4: 176 return (OMAP4_GPIO_REV); 177 #endif 178 #ifdef SOC_TI_AM335X 179 case CHIP_AM335X: 180 return (AM335X_GPIO_REV); 181 #endif 182 } 183 return (0); 184 } 185 186 /** 187 * ti_gpio_mem_spec - Resource specification used when allocating resources 188 * ti_gpio_irq_spec - Resource specification used when allocating resources 189 * 190 * This driver module can have up to six independent memory regions, each 191 * region typically controls 32 GPIO pins. 192 * 193 * On OMAP3 and OMAP4 there is only one physical interrupt line per bank, 194 * but there are two set of registers which control the interrupt delivery 195 * to internal subsystems. The first set of registers control the 196 * interrupts delivery to the MPU and the second set control the 197 * interrupts delivery to the DSP. 198 * 199 * On AM335x there are two physical interrupt lines for each GPIO module. 200 * Each interrupt line is controlled by a set of registers. 201 */ 202 static struct resource_spec ti_gpio_mem_spec[] = { 203 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 204 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL }, 205 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL }, 206 { SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL }, 207 #if !defined(SOC_TI_AM335X) 208 { SYS_RES_MEMORY, 4, RF_ACTIVE | RF_OPTIONAL }, 209 { SYS_RES_MEMORY, 5, RF_ACTIVE | RF_OPTIONAL }, 210 #endif 211 { -1, 0, 0 } 212 }; 213 static struct resource_spec ti_gpio_irq_spec[] = { 214 { SYS_RES_IRQ, 0, RF_ACTIVE }, 215 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, 216 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, 217 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, 218 { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL }, 219 { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL }, 220 #if defined(SOC_TI_AM335X) 221 { SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL }, 222 { SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL }, 223 #endif 224 { -1, 0, 0 } 225 }; 226 227 /** 228 * Structure that stores the driver context. 229 * 230 * This structure is allocated during driver attach. 231 */ 232 struct ti_gpio_softc { 233 device_t sc_dev; 234 235 /* 236 * The memory resource(s) for the PRCM register set, when the device is 237 * created the caller can assign up to 6 memory regions depending on 238 * the SoC type. 239 */ 240 struct resource *sc_mem_res[MAX_GPIO_BANKS]; 241 struct resource *sc_irq_res[MAX_GPIO_INTRS]; 242 243 /* The handle for the register IRQ handlers. */ 244 void *sc_irq_hdl[MAX_GPIO_INTRS]; 245 246 /* 247 * The following describes the H/W revision of each of the GPIO banks. 248 */ 249 uint32_t sc_revision[MAX_GPIO_BANKS]; 250 251 struct mtx sc_mtx; 252 }; 253 254 /** 255 * Macros for driver mutex locking 256 */ 257 #define TI_GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 258 #define TI_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 259 #define TI_GPIO_LOCK_INIT(_sc) \ 260 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 261 "ti_gpio", MTX_DEF) 262 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx) 263 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) 264 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED) 265 266 /** 267 * ti_gpio_read_4 - reads a 16-bit value from one of the PADCONFS registers 268 * @sc: GPIO device context 269 * @bank: The bank to read from 270 * @off: The offset of a register from the GPIO register address range 271 * 272 * 273 * RETURNS: 274 * 32-bit value read from the register. 275 */ 276 static inline uint32_t 277 ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off) 278 { 279 return (bus_read_4(sc->sc_mem_res[bank], off)); 280 } 281 282 /** 283 * ti_gpio_write_4 - writes a 32-bit value to one of the PADCONFS registers 284 * @sc: GPIO device context 285 * @bank: The bank to write to 286 * @off: The offset of a register from the GPIO register address range 287 * @val: The value to write into the register 288 * 289 * RETURNS: 290 * nothing 291 */ 292 static inline void 293 ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off, 294 uint32_t val) 295 { 296 bus_write_4(sc->sc_mem_res[bank], off, val); 297 } 298 299 static inline void 300 ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask) 301 { 302 303 /* We clear both set of registers. */ 304 #if defined(SOC_OMAP4) || defined(SOC_TI_AM335X) 305 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask); 306 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask); 307 #else 308 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE1, mask); 309 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE2, mask); 310 #endif 311 } 312 313 /** 314 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 315 * @dev: gpio device handle 316 * @maxpin: pointer to a value that upon return will contain the maximum number 317 * of pins in the device. 318 * 319 * 320 * LOCKING: 321 * Internally locks the context 322 * 323 * RETURNS: 324 * Returns 0 on success otherwise an error code 325 */ 326 static int 327 ti_gpio_pin_max(device_t dev, int *maxpin) 328 { 329 struct ti_gpio_softc *sc = device_get_softc(dev); 330 unsigned int i; 331 unsigned int banks = 0; 332 333 TI_GPIO_LOCK(sc); 334 335 /* Calculate how many valid banks we have and then multiply that by 32 to 336 * give use the total number of pins. 337 */ 338 for (i = 0; i < ti_max_gpio_banks(); i++) { 339 if (sc->sc_mem_res[i] != NULL) 340 banks++; 341 } 342 343 *maxpin = (banks * PINS_PER_BANK) - 1; 344 345 TI_GPIO_UNLOCK(sc); 346 347 return (0); 348 } 349 350 /** 351 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin 352 * @dev: gpio device handle 353 * @pin: the number of the pin 354 * @caps: pointer to a value that upon return will contain the capabilities 355 * 356 * Currently all pins have the same capability, notably: 357 * - GPIO_PIN_INPUT 358 * - GPIO_PIN_OUTPUT 359 * - GPIO_PIN_PULLUP 360 * - GPIO_PIN_PULLDOWN 361 * 362 * LOCKING: 363 * Internally locks the context 364 * 365 * RETURNS: 366 * Returns 0 on success otherwise an error code 367 */ 368 static int 369 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 370 { 371 struct ti_gpio_softc *sc = device_get_softc(dev); 372 uint32_t bank = (pin / PINS_PER_BANK); 373 374 TI_GPIO_LOCK(sc); 375 376 /* Sanity check the pin number is valid */ 377 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 378 TI_GPIO_UNLOCK(sc); 379 return (EINVAL); 380 } 381 382 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |GPIO_PIN_PULLUP | 383 GPIO_PIN_PULLDOWN); 384 385 TI_GPIO_UNLOCK(sc); 386 387 return (0); 388 } 389 390 /** 391 * ti_gpio_pin_getflags - Gets the current flags of a given pin 392 * @dev: gpio device handle 393 * @pin: the number of the pin 394 * @flags: upon return will contain the current flags of the pin 395 * 396 * Reads the current flags of a given pin, here we actually read the H/W 397 * registers to determine the flags, rather than storing the value in the 398 * setflags call. 399 * 400 * LOCKING: 401 * Internally locks the context 402 * 403 * RETURNS: 404 * Returns 0 on success otherwise an error code 405 */ 406 static int 407 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 408 { 409 struct ti_gpio_softc *sc = device_get_softc(dev); 410 uint32_t bank = (pin / PINS_PER_BANK); 411 412 TI_GPIO_LOCK(sc); 413 414 /* Sanity check the pin number is valid */ 415 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 416 TI_GPIO_UNLOCK(sc); 417 return (EINVAL); 418 } 419 420 /* Get the current pin state */ 421 ti_scm_padconf_get_gpioflags(pin, flags); 422 423 TI_GPIO_UNLOCK(sc); 424 425 return (0); 426 } 427 428 /** 429 * ti_gpio_pin_getname - Gets the name of a given pin 430 * @dev: gpio device handle 431 * @pin: the number of the pin 432 * @name: buffer to put the name in 433 * 434 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 435 * of the pin. 436 * 437 * LOCKING: 438 * Internally locks the context 439 * 440 * RETURNS: 441 * Returns 0 on success otherwise an error code 442 */ 443 static int 444 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 445 { 446 struct ti_gpio_softc *sc = device_get_softc(dev); 447 uint32_t bank = (pin / PINS_PER_BANK); 448 449 TI_GPIO_LOCK(sc); 450 451 /* Sanity check the pin number is valid */ 452 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 453 TI_GPIO_UNLOCK(sc); 454 return (EINVAL); 455 } 456 457 /* Set a very simple name */ 458 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 459 name[GPIOMAXNAME - 1] = '\0'; 460 461 TI_GPIO_UNLOCK(sc); 462 463 return (0); 464 } 465 466 /** 467 * ti_gpio_pin_setflags - Sets the flags for a given pin 468 * @dev: gpio device handle 469 * @pin: the number of the pin 470 * @flags: the flags to set 471 * 472 * The flags of the pin correspond to things like input/output mode, pull-ups, 473 * pull-downs, etc. This driver doesn't support all flags, only the following: 474 * - GPIO_PIN_INPUT 475 * - GPIO_PIN_OUTPUT 476 * - GPIO_PIN_PULLUP 477 * - GPIO_PIN_PULLDOWN 478 * 479 * LOCKING: 480 * Internally locks the context 481 * 482 * RETURNS: 483 * Returns 0 on success otherwise an error code 484 */ 485 static int 486 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 487 { 488 struct ti_gpio_softc *sc = device_get_softc(dev); 489 uint32_t bank = (pin / PINS_PER_BANK); 490 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 491 uint32_t reg_val; 492 493 /* Sanity check the flags supplied are valid, i.e. not input and output */ 494 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0x0000) 495 return (EINVAL); 496 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 497 (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) 498 return (EINVAL); 499 if ((flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) == 500 (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) 501 return (EINVAL); 502 503 TI_GPIO_LOCK(sc); 504 505 /* Sanity check the pin number is valid */ 506 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 507 TI_GPIO_UNLOCK(sc); 508 return (EINVAL); 509 } 510 511 /* Set the GPIO mode and state */ 512 if (ti_scm_padconf_set_gpioflags(pin, flags) != 0) { 513 TI_GPIO_UNLOCK(sc); 514 return (EINVAL); 515 } 516 517 /* If configuring as an output set the "output enable" bit */ 518 reg_val = ti_gpio_read_4(sc, bank, TI_GPIO_OE); 519 if (flags & GPIO_PIN_INPUT) 520 reg_val |= mask; 521 else 522 reg_val &= ~mask; 523 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_val); 524 525 TI_GPIO_UNLOCK(sc); 526 527 return (0); 528 } 529 530 /** 531 * ti_gpio_pin_set - Sets the current level on a GPIO pin 532 * @dev: gpio device handle 533 * @pin: the number of the pin 534 * @value: non-zero value will drive the pin high, otherwise the pin is 535 * driven low. 536 * 537 * 538 * LOCKING: 539 * Internally locks the context 540 * 541 * RETURNS: 542 * Returns 0 on success otherwise a error code 543 */ 544 static int 545 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 546 { 547 struct ti_gpio_softc *sc = device_get_softc(dev); 548 uint32_t bank = (pin / PINS_PER_BANK); 549 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 550 551 TI_GPIO_LOCK(sc); 552 553 /* Sanity check the pin number is valid */ 554 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 555 TI_GPIO_UNLOCK(sc); 556 return (EINVAL); 557 } 558 559 ti_gpio_write_4(sc, bank, (value == GPIO_PIN_LOW) ? TI_GPIO_CLEARDATAOUT 560 : TI_GPIO_SETDATAOUT, mask); 561 562 TI_GPIO_UNLOCK(sc); 563 564 return (0); 565 } 566 567 /** 568 * ti_gpio_pin_get - Gets the current level on a GPIO pin 569 * @dev: gpio device handle 570 * @pin: the number of the pin 571 * @value: pointer to a value that upond return will contain the pin value 572 * 573 * The pin must be configured as an input pin beforehand, otherwise this 574 * function will fail. 575 * 576 * LOCKING: 577 * Internally locks the context 578 * 579 * RETURNS: 580 * Returns 0 on success otherwise a error code 581 */ 582 static int 583 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 584 { 585 struct ti_gpio_softc *sc = device_get_softc(dev); 586 uint32_t bank = (pin / PINS_PER_BANK); 587 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 588 uint32_t val = 0; 589 590 TI_GPIO_LOCK(sc); 591 592 /* Sanity check the pin number is valid */ 593 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 594 TI_GPIO_UNLOCK(sc); 595 return (EINVAL); 596 } 597 598 /* Sanity check the pin is not configured as an output */ 599 val = ti_gpio_read_4(sc, bank, TI_GPIO_OE); 600 601 /* Read the value on the pin */ 602 if (val & mask) 603 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAIN) & mask) ? 1 : 0; 604 else 605 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT) & mask) ? 1 : 0; 606 607 TI_GPIO_UNLOCK(sc); 608 609 return (0); 610 } 611 612 /** 613 * ti_gpio_pin_toggle - Toggles a given GPIO pin 614 * @dev: gpio device handle 615 * @pin: the number of the pin 616 * 617 * 618 * LOCKING: 619 * Internally locks the context 620 * 621 * RETURNS: 622 * Returns 0 on success otherwise a error code 623 */ 624 static int 625 ti_gpio_pin_toggle(device_t dev, uint32_t pin) 626 { 627 struct ti_gpio_softc *sc = device_get_softc(dev); 628 uint32_t bank = (pin / PINS_PER_BANK); 629 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 630 uint32_t val; 631 632 TI_GPIO_LOCK(sc); 633 634 /* Sanity check the pin number is valid */ 635 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 636 TI_GPIO_UNLOCK(sc); 637 return (EINVAL); 638 } 639 640 /* Toggle the pin */ 641 val = ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT); 642 if (val & mask) 643 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARDATAOUT, mask); 644 else 645 ti_gpio_write_4(sc, bank, TI_GPIO_SETDATAOUT, mask); 646 647 TI_GPIO_UNLOCK(sc); 648 649 return (0); 650 } 651 652 /** 653 * ti_gpio_intr - ISR for all GPIO modules 654 * @arg: the soft context pointer 655 * 656 * Unsused 657 * 658 * LOCKING: 659 * Internally locks the context 660 * 661 */ 662 static void 663 ti_gpio_intr(void *arg) 664 { 665 struct ti_gpio_softc *sc = arg; 666 667 TI_GPIO_LOCK(sc); 668 /* TODO: something useful */ 669 TI_GPIO_UNLOCK(sc); 670 } 671 672 /** 673 * ti_gpio_probe - probe function for the driver 674 * @dev: gpio device handle 675 * 676 * Simply sets the name of the driver 677 * 678 * LOCKING: 679 * None 680 * 681 * RETURNS: 682 * Always returns 0 683 */ 684 static int 685 ti_gpio_probe(device_t dev) 686 { 687 688 if (!ofw_bus_status_okay(dev)) 689 return (ENXIO); 690 691 if (!ofw_bus_is_compatible(dev, "ti,gpio")) 692 return (ENXIO); 693 694 device_set_desc(dev, "TI General Purpose I/O (GPIO)"); 695 696 return (0); 697 } 698 699 static int 700 ti_gpio_attach_intr(device_t dev) 701 { 702 int i; 703 struct ti_gpio_softc *sc; 704 705 sc = device_get_softc(dev); 706 for (i = 0; i < ti_max_gpio_intrs(); i++) { 707 if (sc->sc_irq_res[i] == NULL) 708 break; 709 710 /* 711 * Register our interrupt handler for each of the IRQ resources. 712 */ 713 if (bus_setup_intr(dev, sc->sc_irq_res[i], 714 INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_gpio_intr, sc, 715 &sc->sc_irq_hdl[i]) != 0) { 716 device_printf(dev, 717 "WARNING: unable to register interrupt handler\n"); 718 return (-1); 719 } 720 } 721 722 return (0); 723 } 724 725 static int 726 ti_gpio_detach_intr(device_t dev) 727 { 728 int i; 729 struct ti_gpio_softc *sc; 730 731 /* Teardown our interrupt handlers. */ 732 sc = device_get_softc(dev); 733 for (i = 0; i < ti_max_gpio_intrs(); i++) { 734 if (sc->sc_irq_res[i] == NULL) 735 break; 736 737 if (sc->sc_irq_hdl[i]) { 738 bus_teardown_intr(dev, sc->sc_irq_res[i], 739 sc->sc_irq_hdl[i]); 740 } 741 } 742 743 return (0); 744 } 745 746 static int 747 ti_gpio_bank_init(device_t dev, int bank) 748 { 749 int pin; 750 struct ti_gpio_softc *sc; 751 uint32_t flags, reg_oe; 752 753 sc = device_get_softc(dev); 754 755 /* Enable the interface and functional clocks for the module. */ 756 ti_prcm_clk_enable(GPIO0_CLK + ti_first_gpio_bank() + bank); 757 758 /* 759 * Read the revision number of the module. TI don't publish the 760 * actual revision numbers, so instead the values have been 761 * determined by experimentation. 762 */ 763 sc->sc_revision[bank] = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION); 764 765 /* Check the revision. */ 766 if (sc->sc_revision[bank] != ti_gpio_rev()) { 767 device_printf(dev, "Warning: could not determine the revision " 768 "of %u GPIO module (revision:0x%08x)\n", 769 bank, sc->sc_revision[bank]); 770 return (EINVAL); 771 } 772 773 /* Disable interrupts for all pins. */ 774 ti_gpio_intr_clr(sc, bank, 0xffffffff); 775 776 /* Init OE register based on pads configuration. */ 777 reg_oe = 0xffffffff; 778 for (pin = 0; pin < PINS_PER_BANK; pin++) { 779 ti_scm_padconf_get_gpioflags(PINS_PER_BANK * bank + pin, 780 &flags); 781 if (flags & GPIO_PIN_OUTPUT) 782 reg_oe &= ~(1UL << pin); 783 } 784 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe); 785 786 return (0); 787 } 788 789 /** 790 * ti_gpio_attach - attach function for the driver 791 * @dev: gpio device handle 792 * 793 * Allocates and sets up the driver context for all GPIO banks. This function 794 * expects the memory ranges and IRQs to already be allocated to the driver. 795 * 796 * LOCKING: 797 * None 798 * 799 * RETURNS: 800 * Always returns 0 801 */ 802 static int 803 ti_gpio_attach(device_t dev) 804 { 805 struct ti_gpio_softc *sc; 806 unsigned int i; 807 int err; 808 809 sc = device_get_softc(dev); 810 sc->sc_dev = dev; 811 812 TI_GPIO_LOCK_INIT(sc); 813 814 /* There are up to 6 different GPIO register sets located in different 815 * memory areas on the chip. The memory range should have been set for 816 * the driver when it was added as a child. 817 */ 818 if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) { 819 device_printf(dev, "Error: could not allocate mem resources\n"); 820 return (ENXIO); 821 } 822 823 /* Request the IRQ resources */ 824 if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) { 825 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); 826 device_printf(dev, "Error: could not allocate irq resources\n"); 827 return (ENXIO); 828 } 829 830 /* Setup the IRQ resources */ 831 if (ti_gpio_attach_intr(dev) != 0) { 832 ti_gpio_detach_intr(dev); 833 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res); 834 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); 835 return (ENXIO); 836 } 837 838 /* We need to go through each block and ensure the clocks are running and 839 * the module is enabled. It might be better to do this only when the 840 * pins are configured which would result in less power used if the GPIO 841 * pins weren't used ... 842 */ 843 for (i = 0; i < ti_max_gpio_banks(); i++) { 844 if (sc->sc_mem_res[i] != NULL) { 845 /* Initialize the GPIO module. */ 846 err = ti_gpio_bank_init(dev, i); 847 if (err != 0) { 848 ti_gpio_detach_intr(dev); 849 bus_release_resources(dev, ti_gpio_irq_spec, 850 sc->sc_irq_res); 851 bus_release_resources(dev, ti_gpio_mem_spec, 852 sc->sc_mem_res); 853 return (err); 854 } 855 } 856 } 857 858 /* Finish of the probe call */ 859 device_add_child(dev, "gpioc", device_get_unit(dev)); 860 device_add_child(dev, "gpiobus", device_get_unit(dev)); 861 862 return (bus_generic_attach(dev)); 863 } 864 865 /** 866 * ti_gpio_detach - detach function for the driver 867 * @dev: scm device handle 868 * 869 * Allocates and sets up the driver context, this simply entails creating a 870 * bus mappings for the SCM register set. 871 * 872 * LOCKING: 873 * None 874 * 875 * RETURNS: 876 * Always returns 0 877 */ 878 static int 879 ti_gpio_detach(device_t dev) 880 { 881 struct ti_gpio_softc *sc = device_get_softc(dev); 882 unsigned int i; 883 884 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 885 886 /* Disable all interrupts */ 887 for (i = 0; i < ti_max_gpio_banks(); i++) { 888 if (sc->sc_mem_res[i] != NULL) 889 ti_gpio_intr_clr(sc, i, 0xffffffff); 890 } 891 892 bus_generic_detach(dev); 893 894 /* Release the memory and IRQ resources. */ 895 ti_gpio_detach_intr(dev); 896 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res); 897 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); 898 899 TI_GPIO_LOCK_DESTROY(sc); 900 901 return (0); 902 } 903 904 static phandle_t 905 ti_gpio_get_node(device_t bus, device_t dev) 906 { 907 908 /* We only have one child, the GPIO bus, which needs our own node. */ 909 return (ofw_bus_get_node(bus)); 910 } 911 912 static device_method_t ti_gpio_methods[] = { 913 DEVMETHOD(device_probe, ti_gpio_probe), 914 DEVMETHOD(device_attach, ti_gpio_attach), 915 DEVMETHOD(device_detach, ti_gpio_detach), 916 917 /* GPIO protocol */ 918 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 919 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 920 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 921 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 922 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 923 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 924 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 925 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 926 927 /* ofw_bus interface */ 928 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 929 930 {0, 0}, 931 }; 932 933 static driver_t ti_gpio_driver = { 934 "gpio", 935 ti_gpio_methods, 936 sizeof(struct ti_gpio_softc), 937 }; 938 static devclass_t ti_gpio_devclass; 939 940 DRIVER_MODULE(ti_gpio, simplebus, ti_gpio_driver, ti_gpio_devclass, 0, 0); 941