1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 5 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /** 31 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code 32 * here uses 0-5. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include "opt_platform.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/proc.h> 47 #include <sys/rman.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <sys/gpio.h> 51 #include <sys/interrupt.h> 52 53 #include <machine/bus.h> 54 #include <machine/intr.h> 55 #include <machine/resource.h> 56 57 #include <arm/ti/ti_cpuid.h> 58 #include <arm/ti/ti_gpio.h> 59 #include <arm/ti/ti_scm.h> 60 #include <arm/ti/ti_sysc.h> 61 62 #include <dev/gpio/gpiobusvar.h> 63 #include <dev/ofw/openfirm.h> 64 #include <dev/ofw/ofw_bus.h> 65 #include <dev/ofw/ofw_bus_subr.h> 66 67 #include "gpio_if.h" 68 #include "ti_gpio_if.h" 69 #include "pic_if.h" 70 71 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X) 72 #error "Unknown SoC" 73 #endif 74 75 /* Register definitions */ 76 #define TI_GPIO_REVISION 0x0000 77 #define TI_GPIO_SYSCONFIG 0x0010 78 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024 79 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028 80 #define TI_GPIO_IRQSTATUS_0 0x002C /* writing a 0 has no effect */ 81 #define TI_GPIO_IRQSTATUS_1 0x0030 /* writing a 0 has no effect */ 82 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 /* writing a 0 has no effect */ 83 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 /* writing a 0 has no effect */ 84 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C /* writing a 0 has no effect */ 85 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 /* writing a 0 has no effect */ 86 #define TI_GPIO_IRQWAKEN_0 0x0044 87 #define TI_GPIO_IRQWAKEN_1 0x0048 88 #define TI_GPIO_SYSSTATUS 0x0114 89 #define TI_GPIO_IRQSTATUS1 0x0118 90 #define TI_GPIO_IRQENABLE1 0x011C 91 #define TI_GPIO_WAKEUPENABLE 0x0120 92 #define TI_GPIO_IRQSTATUS2 0x0128 93 #define TI_GPIO_IRQENABLE2 0x012C 94 #define TI_GPIO_CTRL 0x0130 95 #define TI_GPIO_OE 0x0134 96 #define TI_GPIO_DATAIN 0x0138 97 #define TI_GPIO_DATAOUT 0x013C 98 #define TI_GPIO_LEVELDETECT0 0x0140 /* RW register */ 99 #define TI_GPIO_LEVELDETECT1 0x0144 /* RW register */ 100 #define TI_GPIO_RISINGDETECT 0x0148 /* RW register */ 101 #define TI_GPIO_FALLINGDETECT 0x014C /* RW register */ 102 #define TI_GPIO_DEBOUNCENABLE 0x0150 103 #define TI_GPIO_DEBOUNCINGTIME 0x0154 104 #define TI_GPIO_CLEARWKUPENA 0x0180 105 #define TI_GPIO_SETWKUENA 0x0184 106 #define TI_GPIO_CLEARDATAOUT 0x0190 107 #define TI_GPIO_SETDATAOUT 0x0194 108 109 /* Other SoC Specific definitions */ 110 #define OMAP4_FIRST_GPIO_BANK 1 111 #define OMAP4_INTR_PER_BANK 1 112 #define OMAP4_GPIO_REV 0x50600801 113 #define AM335X_FIRST_GPIO_BANK 0 114 #define AM335X_INTR_PER_BANK 2 115 #define AM335X_GPIO_REV 0x50600801 116 #define PINS_PER_BANK 32 117 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK)) 118 119 #define OMAP4_GPIO1_REV 0x00000 120 #define OMAP4_GPIO2_REV 0x55000 121 #define OMAP4_GPIO3_REV 0x57000 122 #define OMAP4_GPIO4_REV 0x59000 123 #define OMAP4_GPIO5_REV 0x5b000 124 #define OMAP4_GPIO6_REV 0x5d000 125 126 #define AM335X_GPIO0_REV 0x07000 127 #define AM335X_GPIO1_REV 0x4C000 128 #define AM335X_GPIO2_REV 0xAC000 129 #define AM335X_GPIO3_REV 0xAE000 130 131 static int ti_gpio_intr(void *arg); 132 static int ti_gpio_detach(device_t); 133 134 static int ti_gpio_pic_attach(struct ti_gpio_softc *sc); 135 static int ti_gpio_pic_detach(struct ti_gpio_softc *sc); 136 137 static u_int 138 ti_first_gpio_bank(void) 139 { 140 switch(ti_chip()) { 141 #ifdef SOC_OMAP4 142 case CHIP_OMAP_4: 143 return (OMAP4_FIRST_GPIO_BANK); 144 #endif 145 #ifdef SOC_TI_AM335X 146 case CHIP_AM335X: 147 return (AM335X_FIRST_GPIO_BANK); 148 #endif 149 } 150 return (0); 151 } 152 153 static uint32_t 154 ti_gpio_rev(void) 155 { 156 switch(ti_chip()) { 157 #ifdef SOC_OMAP4 158 case CHIP_OMAP_4: 159 return (OMAP4_GPIO_REV); 160 #endif 161 #ifdef SOC_TI_AM335X 162 case CHIP_AM335X: 163 return (AM335X_GPIO_REV); 164 #endif 165 } 166 return (0); 167 } 168 169 /** 170 * Macros for driver mutex locking 171 */ 172 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 173 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 174 #define TI_GPIO_LOCK_INIT(_sc) \ 175 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 176 "ti_gpio", MTX_SPIN) 177 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 178 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 179 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 180 181 /** 182 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers 183 * @sc: GPIO device context 184 * @bank: The bank to read from 185 * @off: The offset of a register from the GPIO register address range 186 * 187 * 188 * RETURNS: 189 * 32-bit value read from the register. 190 */ 191 static inline uint32_t 192 ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off) 193 { 194 return (bus_read_4(sc->sc_mem_res, off)); 195 } 196 197 /** 198 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers 199 * @sc: GPIO device context 200 * @bank: The bank to write to 201 * @off: The offset of a register from the GPIO register address range 202 * @val: The value to write into the register 203 * 204 * RETURNS: 205 * nothing 206 */ 207 static inline void 208 ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off, 209 uint32_t val) 210 { 211 bus_write_4(sc->sc_mem_res, off, val); 212 } 213 214 static inline void 215 ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask) 216 { 217 218 /* We clear both set of registers. */ 219 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask); 220 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask); 221 } 222 223 static inline void 224 ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask) 225 { 226 227 /* 228 * On OMAP4 we unmask only the MPU interrupt and on AM335x we 229 * also activate only the first interrupt. 230 */ 231 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask); 232 } 233 234 static inline void 235 ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask) 236 { 237 238 /* 239 * Acknowledge the interrupt on both registers even if we use only 240 * the first one. 241 */ 242 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask); 243 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask); 244 } 245 246 static inline uint32_t 247 ti_gpio_intr_status(struct ti_gpio_softc *sc) 248 { 249 uint32_t reg; 250 251 /* Get the status from both registers. */ 252 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0); 253 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1); 254 255 return (reg); 256 } 257 258 static device_t 259 ti_gpio_get_bus(device_t dev) 260 { 261 struct ti_gpio_softc *sc; 262 263 sc = device_get_softc(dev); 264 265 return (sc->sc_busdev); 266 } 267 268 /** 269 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 270 * @dev: gpio device handle 271 * @maxpin: pointer to a value that upon return will contain the maximum number 272 * of pins in the device. 273 * 274 * 275 * LOCKING: 276 * No locking required, returns static data. 277 * 278 * RETURNS: 279 * Returns 0 on success otherwise an error code 280 */ 281 static int 282 ti_gpio_pin_max(device_t dev, int *maxpin) 283 { 284 285 *maxpin = PINS_PER_BANK - 1; 286 287 return (0); 288 } 289 290 static int 291 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin) 292 { 293 294 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL) 295 return (EINVAL); 296 297 return (0); 298 } 299 300 /** 301 * ti_gpio_pin_getcaps - Gets the capabilities of a given pin 302 * @dev: gpio device handle 303 * @pin: the number of the pin 304 * @caps: pointer to a value that upon return will contain the capabilities 305 * 306 * Currently all pins have the same capability, notably: 307 * - GPIO_PIN_INPUT 308 * - GPIO_PIN_OUTPUT 309 * - GPIO_PIN_PULLUP 310 * - GPIO_PIN_PULLDOWN 311 * - GPIO_INTR_LEVEL_LOW 312 * - GPIO_INTR_LEVEL_HIGH 313 * - GPIO_INTR_EDGE_RISING 314 * - GPIO_INTR_EDGE_FALLING 315 * - GPIO_INTR_EDGE_BOTH 316 * 317 * LOCKING: 318 * No locking required, returns static data. 319 * 320 * RETURNS: 321 * Returns 0 on success otherwise an error code 322 */ 323 static int 324 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 325 { 326 struct ti_gpio_softc *sc; 327 328 sc = device_get_softc(dev); 329 if (ti_gpio_valid_pin(sc, pin) != 0) 330 return (EINVAL); 331 332 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP | 333 GPIO_PIN_PULLDOWN | GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | 334 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | 335 GPIO_INTR_EDGE_BOTH); 336 337 return (0); 338 } 339 340 /** 341 * ti_gpio_pin_getflags - Gets the current flags of a given pin 342 * @dev: gpio device handle 343 * @pin: the number of the pin 344 * @flags: upon return will contain the current flags of the pin 345 * 346 * Reads the current flags of a given pin, here we actually read the H/W 347 * registers to determine the flags, rather than storing the value in the 348 * setflags call. 349 * 350 * LOCKING: 351 * Internally locks the context 352 * 353 * RETURNS: 354 * Returns 0 on success otherwise an error code 355 */ 356 static int 357 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 358 { 359 struct ti_gpio_softc *sc; 360 361 sc = device_get_softc(dev); 362 if (ti_gpio_valid_pin(sc, pin) != 0) 363 return (EINVAL); 364 365 /* Get the current pin state */ 366 TI_GPIO_LOCK(sc); 367 TI_GPIO_GET_FLAGS(dev, pin, flags); 368 TI_GPIO_UNLOCK(sc); 369 370 return (0); 371 } 372 373 /** 374 * ti_gpio_pin_getname - Gets the name of a given pin 375 * @dev: gpio device handle 376 * @pin: the number of the pin 377 * @name: buffer to put the name in 378 * 379 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 380 * of the pin. 381 * 382 * LOCKING: 383 * No locking required, returns static data. 384 * 385 * RETURNS: 386 * Returns 0 on success otherwise an error code 387 */ 388 static int 389 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 390 { 391 struct ti_gpio_softc *sc; 392 393 sc = device_get_softc(dev); 394 if (ti_gpio_valid_pin(sc, pin) != 0) 395 return (EINVAL); 396 397 /* Set a very simple name */ 398 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 399 name[GPIOMAXNAME - 1] = '\0'; 400 401 return (0); 402 } 403 404 /** 405 * ti_gpio_pin_setflags - Sets the flags for a given pin 406 * @dev: gpio device handle 407 * @pin: the number of the pin 408 * @flags: the flags to set 409 * 410 * The flags of the pin correspond to things like input/output mode, pull-ups, 411 * pull-downs, etc. This driver doesn't support all flags, only the following: 412 * - GPIO_PIN_INPUT 413 * - GPIO_PIN_OUTPUT 414 * - GPIO_PIN_PULLUP 415 * - GPIO_PIN_PULLDOWN 416 * 417 * LOCKING: 418 * Internally locks the context 419 * 420 * RETURNS: 421 * Returns 0 on success otherwise an error code 422 */ 423 static int 424 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 425 { 426 struct ti_gpio_softc *sc; 427 uint32_t oe; 428 429 sc = device_get_softc(dev); 430 if (ti_gpio_valid_pin(sc, pin) != 0) 431 return (EINVAL); 432 433 /* Set the GPIO mode and state */ 434 TI_GPIO_LOCK(sc); 435 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) { 436 TI_GPIO_UNLOCK(sc); 437 return (EINVAL); 438 } 439 440 /* If configuring as an output set the "output enable" bit */ 441 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 442 if (flags & GPIO_PIN_INPUT) 443 oe |= TI_GPIO_MASK(pin); 444 else 445 oe &= ~TI_GPIO_MASK(pin); 446 ti_gpio_write_4(sc, TI_GPIO_OE, oe); 447 TI_GPIO_UNLOCK(sc); 448 449 return (0); 450 } 451 452 /** 453 * ti_gpio_pin_set - Sets the current level on a GPIO pin 454 * @dev: gpio device handle 455 * @pin: the number of the pin 456 * @value: non-zero value will drive the pin high, otherwise the pin is 457 * driven low. 458 * 459 * 460 * LOCKING: 461 * Internally locks the context 462 * 463 * RETURNS: 464 * Returns 0 on success otherwise a error code 465 */ 466 static int 467 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 468 { 469 struct ti_gpio_softc *sc; 470 uint32_t reg; 471 472 sc = device_get_softc(dev); 473 if (ti_gpio_valid_pin(sc, pin) != 0) 474 return (EINVAL); 475 476 TI_GPIO_LOCK(sc); 477 if (value == GPIO_PIN_LOW) 478 reg = TI_GPIO_CLEARDATAOUT; 479 else 480 reg = TI_GPIO_SETDATAOUT; 481 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 482 TI_GPIO_UNLOCK(sc); 483 484 return (0); 485 } 486 487 /** 488 * ti_gpio_pin_get - Gets the current level on a GPIO pin 489 * @dev: gpio device handle 490 * @pin: the number of the pin 491 * @value: pointer to a value that upond return will contain the pin value 492 * 493 * The pin must be configured as an input pin beforehand, otherwise this 494 * function will fail. 495 * 496 * LOCKING: 497 * Internally locks the context 498 * 499 * RETURNS: 500 * Returns 0 on success otherwise a error code 501 */ 502 static int 503 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 504 { 505 struct ti_gpio_softc *sc; 506 uint32_t oe, reg, val; 507 508 sc = device_get_softc(dev); 509 if (ti_gpio_valid_pin(sc, pin) != 0) 510 return (EINVAL); 511 512 /* 513 * Return data from output latch when set as output and from the 514 * input register otherwise. 515 */ 516 TI_GPIO_LOCK(sc); 517 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 518 if (oe & TI_GPIO_MASK(pin)) 519 reg = TI_GPIO_DATAIN; 520 else 521 reg = TI_GPIO_DATAOUT; 522 val = ti_gpio_read_4(sc, reg); 523 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0; 524 TI_GPIO_UNLOCK(sc); 525 526 return (0); 527 } 528 529 /** 530 * ti_gpio_pin_toggle - Toggles a given GPIO pin 531 * @dev: gpio device handle 532 * @pin: the number of the pin 533 * 534 * 535 * LOCKING: 536 * Internally locks the context 537 * 538 * RETURNS: 539 * Returns 0 on success otherwise a error code 540 */ 541 static int 542 ti_gpio_pin_toggle(device_t dev, uint32_t pin) 543 { 544 struct ti_gpio_softc *sc; 545 uint32_t reg, val; 546 547 sc = device_get_softc(dev); 548 if (ti_gpio_valid_pin(sc, pin) != 0) 549 return (EINVAL); 550 551 /* Toggle the pin */ 552 TI_GPIO_LOCK(sc); 553 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT); 554 if (val & TI_GPIO_MASK(pin)) 555 reg = TI_GPIO_CLEARDATAOUT; 556 else 557 reg = TI_GPIO_SETDATAOUT; 558 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 559 TI_GPIO_UNLOCK(sc); 560 561 return (0); 562 } 563 564 static int 565 ti_gpio_bank_init(device_t dev) 566 { 567 int pin, err; 568 struct ti_gpio_softc *sc; 569 uint32_t flags, reg_oe, reg_set, rev; 570 uint64_t rev_address; 571 572 sc = device_get_softc(dev); 573 574 /* Enable the interface and functional clocks for the module. */ 575 rev_address = ti_sysc_get_rev_address(device_get_parent(dev)); 576 /* AM335x 577 * sc->sc_bank used in am335x/am335x_gpio.c and omap4/omap4_gpio.c */ 578 switch(ti_chip()) { 579 #ifdef SOC_OMAP4 580 case CHIP_OMAP_4: 581 switch (rev_address) { 582 case OMAP4_GPIO1_REV: 583 sc->sc_bank = 0; 584 break; 585 case OMAP4_GPIO2_REV: 586 sc->sc_bank = 1; 587 break; 588 case OMAP4_GPIO3_REV: 589 sc->sc_bank = 2; 590 break; 591 case OMAP4_GPIO4_REV: 592 sc->sc_bank = 3; 593 break; 594 case OMAP4_GPIO5_REV: 595 sc->sc_bank = 4; 596 break; 597 case OMAP4_GPIO6_REV: 598 sc->sc_bank = 5; 599 break; 600 } 601 #endif 602 #ifdef SOC_TI_AM335X 603 case CHIP_AM335X: 604 switch (rev_address) { 605 case AM335X_GPIO0_REV: 606 sc->sc_bank = 0; 607 break; 608 case AM335X_GPIO1_REV: 609 sc->sc_bank = 1; 610 break; 611 case AM335X_GPIO2_REV: 612 sc->sc_bank = 2; 613 break; 614 case AM335X_GPIO3_REV: 615 sc->sc_bank = 3; 616 break; 617 } 618 #endif 619 } 620 err = ti_sysc_clock_enable(device_get_parent(dev)); 621 if (err) { 622 device_printf(dev, "Failed to enable clock\n"); 623 return (EINVAL); 624 } 625 626 /* 627 * Read the revision number of the module. TI don't publish the 628 * actual revision numbers, so instead the values have been 629 * determined by experimentation. 630 */ 631 rev = ti_gpio_read_4(sc, 632 ti_sysc_get_rev_address_offset_host(device_get_parent(dev))); 633 634 /* Check the revision. */ 635 if (rev != ti_gpio_rev()) { 636 device_printf(dev, "Warning: could not determine the revision " 637 "of GPIO module (revision:0x%08x)\n", rev); 638 return (EINVAL); 639 } 640 641 /* Disable interrupts for all pins. */ 642 ti_gpio_intr_clr(sc, 0xffffffff); 643 644 /* Init OE register based on pads configuration. */ 645 reg_oe = 0xffffffff; 646 reg_set = 0; 647 for (pin = 0; pin < PINS_PER_BANK; pin++) { 648 TI_GPIO_GET_FLAGS(dev, pin, &flags); 649 if (flags & GPIO_PIN_OUTPUT) { 650 reg_oe &= ~(1UL << pin); 651 if (flags & GPIO_PIN_PULLUP) 652 reg_set |= (1UL << pin); 653 } 654 } 655 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe); 656 if (reg_set) 657 ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set); 658 659 return (0); 660 } 661 662 /** 663 * ti_gpio_attach - attach function for the driver 664 * @dev: gpio device handle 665 * 666 * Allocates and sets up the driver context for all GPIO banks. This function 667 * expects the memory ranges and IRQs to already be allocated to the driver. 668 * 669 * LOCKING: 670 * None 671 * 672 * RETURNS: 673 * Always returns 0 674 */ 675 static int 676 ti_gpio_attach(device_t dev) 677 { 678 struct ti_gpio_softc *sc; 679 int err; 680 681 sc = device_get_softc(dev); 682 sc->sc_dev = dev; 683 TI_GPIO_LOCK_INIT(sc); 684 ti_gpio_pin_max(dev, &sc->sc_maxpin); 685 sc->sc_maxpin++; 686 687 sc->sc_mem_rid = 0; 688 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 689 &sc->sc_mem_rid, RF_ACTIVE); 690 if (!sc->sc_mem_res) { 691 device_printf(dev, "Error: could not allocate mem resources\n"); 692 ti_gpio_detach(dev); 693 return (ENXIO); 694 } 695 696 sc->sc_irq_rid = 0; 697 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 698 &sc->sc_irq_rid, RF_ACTIVE); 699 if (!sc->sc_irq_res) { 700 device_printf(dev, "Error: could not allocate irq resources\n"); 701 ti_gpio_detach(dev); 702 return (ENXIO); 703 } 704 705 /* 706 * Register our interrupt filter for each of the IRQ resources. 707 */ 708 if (bus_setup_intr(dev, sc->sc_irq_res, 709 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc, 710 &sc->sc_irq_hdl) != 0) { 711 device_printf(dev, 712 "WARNING: unable to register interrupt filter\n"); 713 ti_gpio_detach(dev); 714 return (ENXIO); 715 } 716 717 if (ti_gpio_pic_attach(sc) != 0) { 718 device_printf(dev, "WARNING: unable to attach PIC\n"); 719 ti_gpio_detach(dev); 720 return (ENXIO); 721 } 722 723 /* We need to go through each block and ensure the clocks are running and 724 * the module is enabled. It might be better to do this only when the 725 * pins are configured which would result in less power used if the GPIO 726 * pins weren't used ... 727 */ 728 if (sc->sc_mem_res != NULL) { 729 /* Initialize the GPIO module. */ 730 err = ti_gpio_bank_init(dev); 731 if (err != 0) { 732 ti_gpio_detach(dev); 733 return (err); 734 } 735 } 736 737 sc->sc_busdev = gpiobus_attach_bus(dev); 738 if (sc->sc_busdev == NULL) { 739 ti_gpio_detach(dev); 740 return (ENXIO); 741 } 742 743 return (0); 744 } 745 746 /** 747 * ti_gpio_detach - detach function for the driver 748 * @dev: scm device handle 749 * 750 * Allocates and sets up the driver context, this simply entails creating a 751 * bus mappings for the SCM register set. 752 * 753 * LOCKING: 754 * None 755 * 756 * RETURNS: 757 * Always returns 0 758 */ 759 static int 760 ti_gpio_detach(device_t dev) 761 { 762 struct ti_gpio_softc *sc = device_get_softc(dev); 763 764 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 765 766 /* Disable all interrupts */ 767 if (sc->sc_mem_res != NULL) 768 ti_gpio_intr_clr(sc, 0xffffffff); 769 if (sc->sc_busdev != NULL) 770 gpiobus_detach_bus(dev); 771 if (sc->sc_isrcs != NULL) 772 ti_gpio_pic_detach(sc); 773 /* Release the memory and IRQ resources. */ 774 if (sc->sc_irq_hdl) { 775 bus_teardown_intr(dev, sc->sc_irq_res, 776 sc->sc_irq_hdl); 777 } 778 if (sc->sc_irq_res) 779 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 780 sc->sc_irq_res); 781 if (sc->sc_mem_res) 782 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 783 sc->sc_mem_res); 784 TI_GPIO_LOCK_DESTROY(sc); 785 786 return (0); 787 } 788 789 static inline void 790 ti_gpio_rwreg_modify(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask, 791 bool set_bits) 792 { 793 uint32_t value; 794 795 value = ti_gpio_read_4(sc, reg); 796 ti_gpio_write_4(sc, reg, set_bits ? value | mask : value & ~mask); 797 } 798 799 static inline void 800 ti_gpio_isrc_mask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 801 { 802 803 /* Writing a 0 has no effect. */ 804 ti_gpio_intr_clr(sc, tgi->tgi_mask); 805 } 806 807 static inline void 808 ti_gpio_isrc_unmask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 809 { 810 811 /* Writing a 0 has no effect. */ 812 ti_gpio_intr_set(sc, tgi->tgi_mask); 813 } 814 815 static inline void 816 ti_gpio_isrc_eoi(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi) 817 { 818 819 /* Writing a 0 has no effect. */ 820 ti_gpio_intr_ack(sc, tgi->tgi_mask); 821 } 822 823 static inline bool 824 ti_gpio_isrc_is_level(struct ti_gpio_irqsrc *tgi) 825 { 826 827 return (tgi->tgi_mode == GPIO_INTR_LEVEL_LOW || 828 tgi->tgi_mode == GPIO_INTR_LEVEL_HIGH); 829 } 830 831 static int 832 ti_gpio_intr(void *arg) 833 { 834 u_int irq; 835 uint32_t reg; 836 struct ti_gpio_softc *sc; 837 struct trapframe *tf; 838 struct ti_gpio_irqsrc *tgi; 839 840 sc = (struct ti_gpio_softc *)arg; 841 tf = curthread->td_intr_frame; 842 843 reg = ti_gpio_intr_status(sc); 844 for (irq = 0; irq < sc->sc_maxpin; irq++) { 845 tgi = &sc->sc_isrcs[irq]; 846 if ((reg & tgi->tgi_mask) == 0) 847 continue; 848 if (!ti_gpio_isrc_is_level(tgi)) 849 ti_gpio_isrc_eoi(sc, tgi); 850 if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) { 851 ti_gpio_isrc_mask(sc, tgi); 852 if (ti_gpio_isrc_is_level(tgi)) 853 ti_gpio_isrc_eoi(sc, tgi); 854 device_printf(sc->sc_dev, "Stray irq %u disabled\n", 855 irq); 856 } 857 } 858 return (FILTER_HANDLED); 859 } 860 861 static int 862 ti_gpio_pic_attach(struct ti_gpio_softc *sc) 863 { 864 int error; 865 uint32_t irq; 866 const char *name; 867 868 sc->sc_isrcs = malloc(sizeof(*sc->sc_isrcs) * sc->sc_maxpin, M_DEVBUF, 869 M_WAITOK | M_ZERO); 870 871 name = device_get_nameunit(sc->sc_dev); 872 for (irq = 0; irq < sc->sc_maxpin; irq++) { 873 sc->sc_isrcs[irq].tgi_irq = irq; 874 sc->sc_isrcs[irq].tgi_mask = TI_GPIO_MASK(irq); 875 sc->sc_isrcs[irq].tgi_mode = GPIO_INTR_CONFORM; 876 877 error = intr_isrc_register(&sc->sc_isrcs[irq].tgi_isrc, 878 sc->sc_dev, 0, "%s,%u", name, irq); 879 if (error != 0) 880 return (error); /* XXX deregister ISRCs */ 881 } 882 if (intr_pic_register(sc->sc_dev, 883 OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))) == NULL) 884 return (ENXIO); 885 886 return (0); 887 } 888 889 static int 890 ti_gpio_pic_detach(struct ti_gpio_softc *sc) 891 { 892 893 /* 894 * There has not been established any procedure yet 895 * how to detach PIC from living system correctly. 896 */ 897 device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__); 898 return (EBUSY); 899 } 900 901 static void 902 ti_gpio_pic_config_intr(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi, 903 uint32_t mode) 904 { 905 906 TI_GPIO_LOCK(sc); 907 ti_gpio_rwreg_modify(sc, TI_GPIO_RISINGDETECT, tgi->tgi_mask, 908 mode == GPIO_INTR_EDGE_RISING || mode == GPIO_INTR_EDGE_BOTH); 909 ti_gpio_rwreg_modify(sc, TI_GPIO_FALLINGDETECT, tgi->tgi_mask, 910 mode == GPIO_INTR_EDGE_FALLING || mode == GPIO_INTR_EDGE_BOTH); 911 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT1, tgi->tgi_mask, 912 mode == GPIO_INTR_LEVEL_HIGH); 913 ti_gpio_rwreg_modify(sc, TI_GPIO_LEVELDETECT0, tgi->tgi_mask, 914 mode == GPIO_INTR_LEVEL_LOW); 915 tgi->tgi_mode = mode; 916 TI_GPIO_UNLOCK(sc); 917 } 918 919 static void 920 ti_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 921 { 922 struct ti_gpio_softc *sc = device_get_softc(dev); 923 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 924 925 ti_gpio_isrc_mask(sc, tgi); 926 } 927 928 static void 929 ti_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 930 { 931 struct ti_gpio_softc *sc = device_get_softc(dev); 932 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 933 934 arm_irq_memory_barrier(tgi->tgi_irq); 935 ti_gpio_isrc_unmask(sc, tgi); 936 } 937 938 static int 939 ti_gpio_pic_map_fdt(struct ti_gpio_softc *sc, struct intr_map_data_fdt *daf, 940 u_int *irqp, uint32_t *modep) 941 { 942 uint32_t mode; 943 944 /* 945 * The first cell is the interrupt number. 946 * The second cell is used to specify flags: 947 * bits[3:0] trigger type and level flags: 948 * 1 = low-to-high edge triggered. 949 * 2 = high-to-low edge triggered. 950 * 4 = active high level-sensitive. 951 * 8 = active low level-sensitive. 952 */ 953 if (daf->ncells != 2 || daf->cells[0] >= sc->sc_maxpin) 954 return (EINVAL); 955 956 /* Only reasonable modes are supported. */ 957 if (daf->cells[1] == 1) 958 mode = GPIO_INTR_EDGE_RISING; 959 else if (daf->cells[1] == 2) 960 mode = GPIO_INTR_EDGE_FALLING; 961 else if (daf->cells[1] == 3) 962 mode = GPIO_INTR_EDGE_BOTH; 963 else if (daf->cells[1] == 4) 964 mode = GPIO_INTR_LEVEL_HIGH; 965 else if (daf->cells[1] == 8) 966 mode = GPIO_INTR_LEVEL_LOW; 967 else 968 return (EINVAL); 969 970 *irqp = daf->cells[0]; 971 if (modep != NULL) 972 *modep = mode; 973 return (0); 974 } 975 976 static int 977 ti_gpio_pic_map_gpio(struct ti_gpio_softc *sc, struct intr_map_data_gpio *dag, 978 u_int *irqp, uint32_t *modep) 979 { 980 uint32_t mode; 981 982 if (dag->gpio_pin_num >= sc->sc_maxpin) 983 return (EINVAL); 984 985 mode = dag->gpio_intr_mode; 986 if (mode != GPIO_INTR_LEVEL_LOW && mode != GPIO_INTR_LEVEL_HIGH && 987 mode != GPIO_INTR_EDGE_RISING && mode != GPIO_INTR_EDGE_FALLING && 988 mode != GPIO_INTR_EDGE_BOTH) 989 return (EINVAL); 990 991 *irqp = dag->gpio_pin_num; 992 if (modep != NULL) 993 *modep = mode; 994 return (0); 995 } 996 997 static int 998 ti_gpio_pic_map(struct ti_gpio_softc *sc, struct intr_map_data *data, 999 u_int *irqp, uint32_t *modep) 1000 { 1001 1002 switch (data->type) { 1003 case INTR_MAP_DATA_FDT: 1004 return (ti_gpio_pic_map_fdt(sc, 1005 (struct intr_map_data_fdt *)data, irqp, modep)); 1006 case INTR_MAP_DATA_GPIO: 1007 return (ti_gpio_pic_map_gpio(sc, 1008 (struct intr_map_data_gpio *)data, irqp, modep)); 1009 default: 1010 return (ENOTSUP); 1011 } 1012 } 1013 1014 static int 1015 ti_gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 1016 struct intr_irqsrc **isrcp) 1017 { 1018 int error; 1019 u_int irq; 1020 struct ti_gpio_softc *sc = device_get_softc(dev); 1021 1022 error = ti_gpio_pic_map(sc, data, &irq, NULL); 1023 if (error == 0) 1024 *isrcp = &sc->sc_isrcs[irq].tgi_isrc; 1025 return (error); 1026 } 1027 1028 static void 1029 ti_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 1030 { 1031 struct ti_gpio_softc *sc = device_get_softc(dev); 1032 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1033 1034 if (ti_gpio_isrc_is_level(tgi)) 1035 ti_gpio_isrc_eoi(sc, tgi); 1036 } 1037 1038 static void 1039 ti_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 1040 { 1041 1042 ti_gpio_pic_enable_intr(dev, isrc); 1043 } 1044 1045 static void 1046 ti_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 1047 { 1048 struct ti_gpio_softc *sc = device_get_softc(dev); 1049 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1050 1051 ti_gpio_isrc_mask(sc, tgi); 1052 if (ti_gpio_isrc_is_level(tgi)) 1053 ti_gpio_isrc_eoi(sc, tgi); 1054 } 1055 1056 static int 1057 ti_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 1058 struct resource *res, struct intr_map_data *data) 1059 { 1060 u_int irq; 1061 uint32_t mode; 1062 struct ti_gpio_softc *sc; 1063 struct ti_gpio_irqsrc *tgi; 1064 1065 if (data == NULL) 1066 return (ENOTSUP); 1067 1068 sc = device_get_softc(dev); 1069 tgi = (struct ti_gpio_irqsrc *)isrc; 1070 1071 /* Get and check config for an interrupt. */ 1072 if (ti_gpio_pic_map(sc, data, &irq, &mode) != 0 || tgi->tgi_irq != irq) 1073 return (EINVAL); 1074 1075 /* 1076 * If this is a setup for another handler, 1077 * only check that its configuration match. 1078 */ 1079 if (isrc->isrc_handlers != 0) 1080 return (tgi->tgi_mode == mode ? 0 : EINVAL); 1081 1082 ti_gpio_pic_config_intr(sc, tgi, mode); 1083 return (0); 1084 } 1085 1086 static int 1087 ti_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 1088 struct resource *res, struct intr_map_data *data) 1089 { 1090 struct ti_gpio_softc *sc = device_get_softc(dev); 1091 struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc; 1092 1093 if (isrc->isrc_handlers == 0) 1094 ti_gpio_pic_config_intr(sc, tgi, GPIO_INTR_CONFORM); 1095 return (0); 1096 } 1097 1098 static phandle_t 1099 ti_gpio_get_node(device_t bus, device_t dev) 1100 { 1101 1102 /* We only have one child, the GPIO bus, which needs our own node. */ 1103 return (ofw_bus_get_node(bus)); 1104 } 1105 1106 static device_method_t ti_gpio_methods[] = { 1107 DEVMETHOD(device_attach, ti_gpio_attach), 1108 DEVMETHOD(device_detach, ti_gpio_detach), 1109 1110 /* GPIO protocol */ 1111 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus), 1112 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 1113 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 1114 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 1115 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 1116 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 1117 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 1118 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 1119 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 1120 1121 /* Interrupt controller interface */ 1122 DEVMETHOD(pic_disable_intr, ti_gpio_pic_disable_intr), 1123 DEVMETHOD(pic_enable_intr, ti_gpio_pic_enable_intr), 1124 DEVMETHOD(pic_map_intr, ti_gpio_pic_map_intr), 1125 DEVMETHOD(pic_setup_intr, ti_gpio_pic_setup_intr), 1126 DEVMETHOD(pic_teardown_intr, ti_gpio_pic_teardown_intr), 1127 DEVMETHOD(pic_post_filter, ti_gpio_pic_post_filter), 1128 DEVMETHOD(pic_post_ithread, ti_gpio_pic_post_ithread), 1129 DEVMETHOD(pic_pre_ithread, ti_gpio_pic_pre_ithread), 1130 1131 /* ofw_bus interface */ 1132 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 1133 1134 {0, 0}, 1135 }; 1136 1137 driver_t ti_gpio_driver = { 1138 "gpio", 1139 ti_gpio_methods, 1140 sizeof(struct ti_gpio_softc), 1141 }; 1142