1 /*- 2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /** 29 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code 30 * here uses 0-5. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/rman.h> 43 #include <sys/lock.h> 44 #include <sys/mutex.h> 45 #include <sys/gpio.h> 46 #include <sys/interrupt.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 51 #include <arm/ti/ti_cpuid.h> 52 #include <arm/ti/ti_gpio.h> 53 #include <arm/ti/ti_scm.h> 54 #include <arm/ti/ti_prcm.h> 55 #include <arm/ti/ti_hwmods.h> 56 57 #include <dev/fdt/fdt_common.h> 58 #include <dev/gpio/gpiobusvar.h> 59 #include <dev/ofw/openfirm.h> 60 #include <dev/ofw/ofw_bus.h> 61 #include <dev/ofw/ofw_bus_subr.h> 62 63 #include "gpio_if.h" 64 #include "ti_gpio_if.h" 65 66 #if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X) 67 #error "Unknown SoC" 68 #endif 69 70 /* Register definitions */ 71 #define TI_GPIO_REVISION 0x0000 72 #define TI_GPIO_SYSCONFIG 0x0010 73 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024 74 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028 75 #define TI_GPIO_IRQSTATUS_0 0x002C 76 #define TI_GPIO_IRQSTATUS_1 0x0030 77 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 78 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 79 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C 80 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 81 #define TI_GPIO_IRQWAKEN_0 0x0044 82 #define TI_GPIO_IRQWAKEN_1 0x0048 83 #define TI_GPIO_SYSSTATUS 0x0114 84 #define TI_GPIO_IRQSTATUS1 0x0118 85 #define TI_GPIO_IRQENABLE1 0x011C 86 #define TI_GPIO_WAKEUPENABLE 0x0120 87 #define TI_GPIO_IRQSTATUS2 0x0128 88 #define TI_GPIO_IRQENABLE2 0x012C 89 #define TI_GPIO_CTRL 0x0130 90 #define TI_GPIO_OE 0x0134 91 #define TI_GPIO_DATAIN 0x0138 92 #define TI_GPIO_DATAOUT 0x013C 93 #define TI_GPIO_LEVELDETECT0 0x0140 94 #define TI_GPIO_LEVELDETECT1 0x0144 95 #define TI_GPIO_RISINGDETECT 0x0148 96 #define TI_GPIO_FALLINGDETECT 0x014C 97 #define TI_GPIO_DEBOUNCENABLE 0x0150 98 #define TI_GPIO_DEBOUNCINGTIME 0x0154 99 #define TI_GPIO_CLEARWKUPENA 0x0180 100 #define TI_GPIO_SETWKUENA 0x0184 101 #define TI_GPIO_CLEARDATAOUT 0x0190 102 #define TI_GPIO_SETDATAOUT 0x0194 103 104 /* Other SoC Specific definitions */ 105 #define OMAP4_FIRST_GPIO_BANK 1 106 #define OMAP4_INTR_PER_BANK 1 107 #define OMAP4_GPIO_REV 0x50600801 108 #define AM335X_FIRST_GPIO_BANK 0 109 #define AM335X_INTR_PER_BANK 2 110 #define AM335X_GPIO_REV 0x50600801 111 #define PINS_PER_BANK 32 112 #define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK)) 113 114 static int ti_gpio_detach(device_t); 115 116 static u_int 117 ti_first_gpio_bank(void) 118 { 119 switch(ti_chip()) { 120 #ifdef SOC_OMAP4 121 case CHIP_OMAP_4: 122 return (OMAP4_FIRST_GPIO_BANK); 123 #endif 124 #ifdef SOC_TI_AM335X 125 case CHIP_AM335X: 126 return (AM335X_FIRST_GPIO_BANK); 127 #endif 128 } 129 return (0); 130 } 131 132 static uint32_t 133 ti_gpio_rev(void) 134 { 135 switch(ti_chip()) { 136 #ifdef SOC_OMAP4 137 case CHIP_OMAP_4: 138 return (OMAP4_GPIO_REV); 139 #endif 140 #ifdef SOC_TI_AM335X 141 case CHIP_AM335X: 142 return (AM335X_GPIO_REV); 143 #endif 144 } 145 return (0); 146 } 147 148 /** 149 * Macros for driver mutex locking 150 */ 151 #define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 152 #define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 153 #define TI_GPIO_LOCK_INIT(_sc) \ 154 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 155 "ti_gpio", MTX_SPIN) 156 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 157 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 158 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) 159 160 /** 161 * ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers 162 * @sc: GPIO device context 163 * @bank: The bank to read from 164 * @off: The offset of a register from the GPIO register address range 165 * 166 * 167 * RETURNS: 168 * 32-bit value read from the register. 169 */ 170 static inline uint32_t 171 ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off) 172 { 173 return (bus_read_4(sc->sc_mem_res, off)); 174 } 175 176 /** 177 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers 178 * @sc: GPIO device context 179 * @bank: The bank to write to 180 * @off: The offset of a register from the GPIO register address range 181 * @val: The value to write into the register 182 * 183 * RETURNS: 184 * nothing 185 */ 186 static inline void 187 ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off, 188 uint32_t val) 189 { 190 bus_write_4(sc->sc_mem_res, off, val); 191 } 192 193 static inline void 194 ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask) 195 { 196 197 /* We clear both set of registers. */ 198 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask); 199 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask); 200 } 201 202 static inline void 203 ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask) 204 { 205 206 /* 207 * On OMAP4 we unmask only the MPU interrupt and on AM335x we 208 * also activate only the first interrupt. 209 */ 210 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask); 211 } 212 213 static inline void 214 ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask) 215 { 216 217 /* 218 * Acknowledge the interrupt on both registers even if we use only 219 * the first one. 220 */ 221 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask); 222 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask); 223 } 224 225 static inline uint32_t 226 ti_gpio_intr_status(struct ti_gpio_softc *sc) 227 { 228 uint32_t reg; 229 230 /* Get the status from both registers. */ 231 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0); 232 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1); 233 234 return (reg); 235 } 236 237 static device_t 238 ti_gpio_get_bus(device_t dev) 239 { 240 struct ti_gpio_softc *sc; 241 242 sc = device_get_softc(dev); 243 244 return (sc->sc_busdev); 245 } 246 247 /** 248 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 249 * @dev: gpio device handle 250 * @maxpin: pointer to a value that upon return will contain the maximum number 251 * of pins in the device. 252 * 253 * 254 * LOCKING: 255 * No locking required, returns static data. 256 * 257 * RETURNS: 258 * Returns 0 on success otherwise an error code 259 */ 260 static int 261 ti_gpio_pin_max(device_t dev, int *maxpin) 262 { 263 264 *maxpin = PINS_PER_BANK - 1; 265 266 return (0); 267 } 268 269 static int 270 ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin) 271 { 272 273 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL) 274 return (EINVAL); 275 276 return (0); 277 } 278 279 /** 280 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin 281 * @dev: gpio device handle 282 * @pin: the number of the pin 283 * @caps: pointer to a value that upon return will contain the capabilities 284 * 285 * Currently all pins have the same capability, notably: 286 * - GPIO_PIN_INPUT 287 * - GPIO_PIN_OUTPUT 288 * - GPIO_PIN_PULLUP 289 * - GPIO_PIN_PULLDOWN 290 * 291 * LOCKING: 292 * No locking required, returns static data. 293 * 294 * RETURNS: 295 * Returns 0 on success otherwise an error code 296 */ 297 static int 298 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 299 { 300 struct ti_gpio_softc *sc; 301 302 sc = device_get_softc(dev); 303 if (ti_gpio_valid_pin(sc, pin) != 0) 304 return (EINVAL); 305 306 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP | 307 GPIO_PIN_PULLDOWN); 308 309 return (0); 310 } 311 312 /** 313 * ti_gpio_pin_getflags - Gets the current flags of a given pin 314 * @dev: gpio device handle 315 * @pin: the number of the pin 316 * @flags: upon return will contain the current flags of the pin 317 * 318 * Reads the current flags of a given pin, here we actually read the H/W 319 * registers to determine the flags, rather than storing the value in the 320 * setflags call. 321 * 322 * LOCKING: 323 * Internally locks the context 324 * 325 * RETURNS: 326 * Returns 0 on success otherwise an error code 327 */ 328 static int 329 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 330 { 331 struct ti_gpio_softc *sc; 332 333 sc = device_get_softc(dev); 334 if (ti_gpio_valid_pin(sc, pin) != 0) 335 return (EINVAL); 336 337 /* Get the current pin state */ 338 TI_GPIO_LOCK(sc); 339 TI_GPIO_GET_FLAGS(dev, pin, flags); 340 TI_GPIO_UNLOCK(sc); 341 342 return (0); 343 } 344 345 /** 346 * ti_gpio_pin_getname - Gets the name of a given pin 347 * @dev: gpio device handle 348 * @pin: the number of the pin 349 * @name: buffer to put the name in 350 * 351 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 352 * of the pin. 353 * 354 * LOCKING: 355 * No locking required, returns static data. 356 * 357 * RETURNS: 358 * Returns 0 on success otherwise an error code 359 */ 360 static int 361 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 362 { 363 struct ti_gpio_softc *sc; 364 365 sc = device_get_softc(dev); 366 if (ti_gpio_valid_pin(sc, pin) != 0) 367 return (EINVAL); 368 369 /* Set a very simple name */ 370 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 371 name[GPIOMAXNAME - 1] = '\0'; 372 373 return (0); 374 } 375 376 /** 377 * ti_gpio_pin_setflags - Sets the flags for a given pin 378 * @dev: gpio device handle 379 * @pin: the number of the pin 380 * @flags: the flags to set 381 * 382 * The flags of the pin correspond to things like input/output mode, pull-ups, 383 * pull-downs, etc. This driver doesn't support all flags, only the following: 384 * - GPIO_PIN_INPUT 385 * - GPIO_PIN_OUTPUT 386 * - GPIO_PIN_PULLUP 387 * - GPIO_PIN_PULLDOWN 388 * 389 * LOCKING: 390 * Internally locks the context 391 * 392 * RETURNS: 393 * Returns 0 on success otherwise an error code 394 */ 395 static int 396 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 397 { 398 struct ti_gpio_softc *sc; 399 uint32_t oe; 400 401 sc = device_get_softc(dev); 402 if (ti_gpio_valid_pin(sc, pin) != 0) 403 return (EINVAL); 404 405 /* Set the GPIO mode and state */ 406 TI_GPIO_LOCK(sc); 407 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) { 408 TI_GPIO_UNLOCK(sc); 409 return (EINVAL); 410 } 411 412 /* If configuring as an output set the "output enable" bit */ 413 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 414 if (flags & GPIO_PIN_INPUT) 415 oe |= TI_GPIO_MASK(pin); 416 else 417 oe &= ~TI_GPIO_MASK(pin); 418 ti_gpio_write_4(sc, TI_GPIO_OE, oe); 419 TI_GPIO_UNLOCK(sc); 420 421 return (0); 422 } 423 424 /** 425 * ti_gpio_pin_set - Sets the current level on a GPIO pin 426 * @dev: gpio device handle 427 * @pin: the number of the pin 428 * @value: non-zero value will drive the pin high, otherwise the pin is 429 * driven low. 430 * 431 * 432 * LOCKING: 433 * Internally locks the context 434 * 435 * RETURNS: 436 * Returns 0 on success otherwise a error code 437 */ 438 static int 439 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 440 { 441 struct ti_gpio_softc *sc; 442 uint32_t reg; 443 444 sc = device_get_softc(dev); 445 if (ti_gpio_valid_pin(sc, pin) != 0) 446 return (EINVAL); 447 448 TI_GPIO_LOCK(sc); 449 if (value == GPIO_PIN_LOW) 450 reg = TI_GPIO_CLEARDATAOUT; 451 else 452 reg = TI_GPIO_SETDATAOUT; 453 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 454 TI_GPIO_UNLOCK(sc); 455 456 return (0); 457 } 458 459 /** 460 * ti_gpio_pin_get - Gets the current level on a GPIO pin 461 * @dev: gpio device handle 462 * @pin: the number of the pin 463 * @value: pointer to a value that upond return will contain the pin value 464 * 465 * The pin must be configured as an input pin beforehand, otherwise this 466 * function will fail. 467 * 468 * LOCKING: 469 * Internally locks the context 470 * 471 * RETURNS: 472 * Returns 0 on success otherwise a error code 473 */ 474 static int 475 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 476 { 477 struct ti_gpio_softc *sc; 478 uint32_t oe, reg, val; 479 480 sc = device_get_softc(dev); 481 if (ti_gpio_valid_pin(sc, pin) != 0) 482 return (EINVAL); 483 484 /* 485 * Return data from output latch when set as output and from the 486 * input register otherwise. 487 */ 488 TI_GPIO_LOCK(sc); 489 oe = ti_gpio_read_4(sc, TI_GPIO_OE); 490 if (oe & TI_GPIO_MASK(pin)) 491 reg = TI_GPIO_DATAIN; 492 else 493 reg = TI_GPIO_DATAOUT; 494 val = ti_gpio_read_4(sc, reg); 495 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0; 496 TI_GPIO_UNLOCK(sc); 497 498 return (0); 499 } 500 501 /** 502 * ti_gpio_pin_toggle - Toggles a given GPIO pin 503 * @dev: gpio device handle 504 * @pin: the number of the pin 505 * 506 * 507 * LOCKING: 508 * Internally locks the context 509 * 510 * RETURNS: 511 * Returns 0 on success otherwise a error code 512 */ 513 static int 514 ti_gpio_pin_toggle(device_t dev, uint32_t pin) 515 { 516 struct ti_gpio_softc *sc; 517 uint32_t reg, val; 518 519 sc = device_get_softc(dev); 520 if (ti_gpio_valid_pin(sc, pin) != 0) 521 return (EINVAL); 522 523 /* Toggle the pin */ 524 TI_GPIO_LOCK(sc); 525 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT); 526 if (val & TI_GPIO_MASK(pin)) 527 reg = TI_GPIO_CLEARDATAOUT; 528 else 529 reg = TI_GPIO_SETDATAOUT; 530 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin)); 531 TI_GPIO_UNLOCK(sc); 532 533 return (0); 534 } 535 536 /** 537 * ti_gpio_intr - ISR for all GPIO modules 538 * @arg: the soft context pointer 539 * 540 * LOCKING: 541 * Internally locks the context 542 * 543 */ 544 static int 545 ti_gpio_intr(void *arg) 546 { 547 int bank_last, irq; 548 struct intr_event *event; 549 struct ti_gpio_softc *sc; 550 uint32_t reg; 551 552 sc = (struct ti_gpio_softc *)arg; 553 bank_last = -1; 554 reg = 0; /* squelch bogus gcc warning */ 555 reg = ti_gpio_intr_status(sc); 556 for (irq = 0; irq < sc->sc_maxpin; irq++) { 557 if ((reg & TI_GPIO_MASK(irq)) == 0) 558 continue; 559 event = sc->sc_events[irq]; 560 if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers)) 561 intr_event_handle(event, NULL); 562 else 563 device_printf(sc->sc_dev, "Stray IRQ %d\n", irq); 564 /* Ack the IRQ Status bit. */ 565 ti_gpio_intr_ack(sc, TI_GPIO_MASK(irq)); 566 } 567 568 return (FILTER_HANDLED); 569 } 570 571 static int 572 ti_gpio_bank_init(device_t dev) 573 { 574 int pin; 575 struct ti_gpio_softc *sc; 576 uint32_t flags, reg_oe, reg_set, rev; 577 clk_ident_t clk; 578 579 sc = device_get_softc(dev); 580 581 /* Enable the interface and functional clocks for the module. */ 582 clk = ti_hwmods_get_clock(dev); 583 if (clk == INVALID_CLK_IDENT) { 584 device_printf(dev, "failed to get device id based on ti,hwmods\n"); 585 return (EINVAL); 586 } 587 588 sc->sc_bank = clk - GPIO1_CLK + ti_first_gpio_bank(); 589 ti_prcm_clk_enable(clk); 590 591 /* 592 * Read the revision number of the module. TI don't publish the 593 * actual revision numbers, so instead the values have been 594 * determined by experimentation. 595 */ 596 rev = ti_gpio_read_4(sc, TI_GPIO_REVISION); 597 598 /* Check the revision. */ 599 if (rev != ti_gpio_rev()) { 600 device_printf(dev, "Warning: could not determine the revision " 601 "of GPIO module (revision:0x%08x)\n", rev); 602 return (EINVAL); 603 } 604 605 /* Disable interrupts for all pins. */ 606 ti_gpio_intr_clr(sc, 0xffffffff); 607 608 /* Init OE register based on pads configuration. */ 609 reg_oe = 0xffffffff; 610 reg_set = 0; 611 for (pin = 0; pin < PINS_PER_BANK; pin++) { 612 TI_GPIO_GET_FLAGS(dev, pin, &flags); 613 if (flags & GPIO_PIN_OUTPUT) { 614 reg_oe &= ~(1UL << pin); 615 if (flags & GPIO_PIN_PULLUP) 616 reg_set |= (1UL << pin); 617 } 618 } 619 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe); 620 if (reg_set) 621 ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set); 622 623 return (0); 624 } 625 626 /** 627 * ti_gpio_attach - attach function for the driver 628 * @dev: gpio device handle 629 * 630 * Allocates and sets up the driver context for all GPIO banks. This function 631 * expects the memory ranges and IRQs to already be allocated to the driver. 632 * 633 * LOCKING: 634 * None 635 * 636 * RETURNS: 637 * Always returns 0 638 */ 639 static int 640 ti_gpio_attach(device_t dev) 641 { 642 struct ti_gpio_softc *sc; 643 unsigned int i; 644 int err; 645 646 sc = device_get_softc(dev); 647 sc->sc_dev = dev; 648 TI_GPIO_LOCK_INIT(sc); 649 ti_gpio_pin_max(dev, &sc->sc_maxpin); 650 sc->sc_maxpin++; 651 652 sc->sc_mem_rid = 0; 653 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 654 &sc->sc_mem_rid, RF_ACTIVE); 655 if (!sc->sc_mem_res) { 656 device_printf(dev, "Error: could not allocate mem resources\n"); 657 ti_gpio_detach(dev); 658 return (ENXIO); 659 } 660 661 sc->sc_irq_rid = 0; 662 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 663 &sc->sc_irq_rid, RF_ACTIVE); 664 if (!sc->sc_irq_res) { 665 device_printf(dev, "Error: could not allocate irq resources\n"); 666 ti_gpio_detach(dev); 667 return (ENXIO); 668 } 669 670 /* 671 * Register our interrupt filter for each of the IRQ resources. 672 */ 673 if (bus_setup_intr(dev, sc->sc_irq_res, 674 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc, 675 &sc->sc_irq_hdl) != 0) { 676 device_printf(dev, 677 "WARNING: unable to register interrupt filter\n"); 678 ti_gpio_detach(dev); 679 return (ENXIO); 680 } 681 682 /* 683 * Initialize the interrupt settings. The default is active-low 684 * interrupts. 685 */ 686 sc->sc_irq_trigger = malloc( 687 sizeof(*sc->sc_irq_trigger) * sc->sc_maxpin, 688 M_DEVBUF, M_WAITOK | M_ZERO); 689 sc->sc_irq_polarity = malloc( 690 sizeof(*sc->sc_irq_polarity) * sc->sc_maxpin, 691 M_DEVBUF, M_WAITOK | M_ZERO); 692 for (i = 0; i < sc->sc_maxpin; i++) { 693 sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL; 694 sc->sc_irq_polarity[i] = INTR_POLARITY_LOW; 695 } 696 697 sc->sc_events = malloc(sizeof(struct intr_event *) * sc->sc_maxpin, 698 M_DEVBUF, M_WAITOK | M_ZERO); 699 700 sc->sc_mask_args = malloc(sizeof(struct ti_gpio_mask_arg) * sc->sc_maxpin, 701 M_DEVBUF, M_WAITOK | M_ZERO); 702 703 /* We need to go through each block and ensure the clocks are running and 704 * the module is enabled. It might be better to do this only when the 705 * pins are configured which would result in less power used if the GPIO 706 * pins weren't used ... 707 */ 708 if (sc->sc_mem_res != NULL) { 709 /* Initialize the GPIO module. */ 710 err = ti_gpio_bank_init(dev); 711 if (err != 0) { 712 ti_gpio_detach(dev); 713 return (err); 714 } 715 } 716 717 sc->sc_busdev = gpiobus_attach_bus(dev); 718 if (sc->sc_busdev == NULL) { 719 ti_gpio_detach(dev); 720 return (ENXIO); 721 } 722 723 return (0); 724 } 725 726 /** 727 * ti_gpio_detach - detach function for the driver 728 * @dev: scm device handle 729 * 730 * Allocates and sets up the driver context, this simply entails creating a 731 * bus mappings for the SCM register set. 732 * 733 * LOCKING: 734 * None 735 * 736 * RETURNS: 737 * Always returns 0 738 */ 739 static int 740 ti_gpio_detach(device_t dev) 741 { 742 struct ti_gpio_softc *sc = device_get_softc(dev); 743 744 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 745 746 /* Disable all interrupts */ 747 if (sc->sc_mem_res != NULL) 748 ti_gpio_intr_clr(sc, 0xffffffff); 749 gpiobus_detach_bus(dev); 750 if (sc->sc_events) 751 free(sc->sc_events, M_DEVBUF); 752 if (sc->sc_mask_args) 753 free(sc->sc_mask_args, M_DEVBUF); 754 if (sc->sc_irq_polarity) 755 free(sc->sc_irq_polarity, M_DEVBUF); 756 if (sc->sc_irq_trigger) 757 free(sc->sc_irq_trigger, M_DEVBUF); 758 /* Release the memory and IRQ resources. */ 759 if (sc->sc_irq_hdl) { 760 bus_teardown_intr(dev, sc->sc_irq_res, 761 sc->sc_irq_hdl); 762 } 763 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid, 764 sc->sc_irq_res); 765 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 766 sc->sc_mem_res); 767 TI_GPIO_LOCK_DESTROY(sc); 768 769 return (0); 770 } 771 772 static uint32_t 773 ti_gpio_intr_reg(struct ti_gpio_softc *sc, int irq) 774 { 775 776 if (ti_gpio_valid_pin(sc, irq) != 0) 777 return (0); 778 779 if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) { 780 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 781 return (TI_GPIO_LEVELDETECT0); 782 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 783 return (TI_GPIO_LEVELDETECT1); 784 } else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) { 785 if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW) 786 return (TI_GPIO_FALLINGDETECT); 787 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH) 788 return (TI_GPIO_RISINGDETECT); 789 } 790 791 return (0); 792 } 793 794 static void 795 ti_gpio_mask_irq_internal(struct ti_gpio_softc *sc, int irq) 796 { 797 uint32_t reg, val; 798 799 if (ti_gpio_valid_pin(sc, irq) != 0) 800 return; 801 802 TI_GPIO_LOCK(sc); 803 ti_gpio_intr_clr(sc, TI_GPIO_MASK(irq)); 804 reg = ti_gpio_intr_reg(sc, irq); 805 if (reg != 0) { 806 val = ti_gpio_read_4(sc, reg); 807 val &= ~TI_GPIO_MASK(irq); 808 ti_gpio_write_4(sc, reg, val); 809 } 810 TI_GPIO_UNLOCK(sc); 811 } 812 813 static void 814 ti_gpio_unmask_irq_internal(struct ti_gpio_softc *sc, int irq) 815 { 816 uint32_t reg, val; 817 818 if (ti_gpio_valid_pin(sc, irq) != 0) 819 return; 820 821 TI_GPIO_LOCK(sc); 822 reg = ti_gpio_intr_reg(sc, irq); 823 if (reg != 0) { 824 val = ti_gpio_read_4(sc, reg); 825 val |= TI_GPIO_MASK(irq); 826 ti_gpio_write_4(sc, reg, val); 827 ti_gpio_intr_set(sc, TI_GPIO_MASK(irq)); 828 } 829 TI_GPIO_UNLOCK(sc); 830 } 831 832 static void 833 ti_gpio_mask_irq(void *source) 834 { 835 struct ti_gpio_mask_arg *arg = source; 836 837 ti_gpio_mask_irq_internal(arg->softc, arg->pin); 838 } 839 840 static void 841 ti_gpio_unmask_irq(void *source) 842 { 843 struct ti_gpio_mask_arg *arg = source; 844 845 ti_gpio_unmask_irq_internal(arg->softc, arg->pin); 846 } 847 848 static int 849 ti_gpio_activate_resource(device_t dev, device_t child, int type, int rid, 850 struct resource *res) 851 { 852 struct ti_gpio_mask_arg mask_arg; 853 854 if (type != SYS_RES_IRQ) 855 return (ENXIO); 856 857 /* Unmask the interrupt. */ 858 mask_arg.pin = rman_get_start(res); 859 mask_arg.softc = device_get_softc(dev); 860 861 ti_gpio_unmask_irq((void *)&mask_arg); 862 863 return (0); 864 } 865 866 static int 867 ti_gpio_deactivate_resource(device_t dev, device_t child, int type, int rid, 868 struct resource *res) 869 { 870 int pin; 871 872 if (type != SYS_RES_IRQ) 873 return (ENXIO); 874 875 /* Mask the interrupt. */ 876 pin = rman_get_start(res); 877 ti_gpio_mask_irq((void *)(uintptr_t)pin); 878 879 return (0); 880 } 881 882 static int 883 ti_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig, 884 enum intr_polarity pol) 885 { 886 struct ti_gpio_softc *sc; 887 uint32_t oldreg, reg, val; 888 889 sc = device_get_softc(dev); 890 if (ti_gpio_valid_pin(sc, irq) != 0) 891 return (EINVAL); 892 893 /* There is no standard trigger or polarity. */ 894 if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM) 895 return (EINVAL); 896 897 TI_GPIO_LOCK(sc); 898 /* 899 * TRM recommends add the new event before remove the old one to 900 * avoid losing interrupts. 901 */ 902 oldreg = ti_gpio_intr_reg(sc, irq); 903 sc->sc_irq_trigger[irq] = trig; 904 sc->sc_irq_polarity[irq] = pol; 905 reg = ti_gpio_intr_reg(sc, irq); 906 if (reg != 0) { 907 /* Apply the new settings. */ 908 val = ti_gpio_read_4(sc, reg); 909 val |= TI_GPIO_MASK(irq); 910 ti_gpio_write_4(sc, reg, val); 911 } 912 if (reg != oldreg && oldreg != 0) { 913 /* Remove the old settings. */ 914 val = ti_gpio_read_4(sc, oldreg); 915 val &= ~TI_GPIO_MASK(irq); 916 ti_gpio_write_4(sc, oldreg, val); 917 } 918 TI_GPIO_UNLOCK(sc); 919 920 return (0); 921 } 922 923 static int 924 ti_gpio_setup_intr(device_t dev, device_t child, struct resource *ires, 925 int flags, driver_filter_t *filt, driver_intr_t *handler, 926 void *arg, void **cookiep) 927 { 928 struct ti_gpio_softc *sc; 929 struct intr_event *event; 930 int pin, error; 931 932 sc = device_get_softc(dev); 933 pin = rman_get_start(ires); 934 if (ti_gpio_valid_pin(sc, pin) != 0) 935 panic("%s: bad pin %d", __func__, pin); 936 937 event = sc->sc_events[pin]; 938 if (event == NULL) { 939 sc->sc_mask_args[pin].softc = sc; 940 sc->sc_mask_args[pin].pin = pin; 941 error = intr_event_create(&event, (void *)&sc->sc_mask_args[pin], 0, 942 pin, ti_gpio_mask_irq, ti_gpio_unmask_irq, NULL, NULL, 943 "gpio%d pin%d:", device_get_unit(dev), pin); 944 if (error != 0) 945 return (error); 946 sc->sc_events[pin] = event; 947 } 948 intr_event_add_handler(event, device_get_nameunit(child), filt, 949 handler, arg, intr_priority(flags), flags, cookiep); 950 951 return (0); 952 } 953 954 static int 955 ti_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires, 956 void *cookie) 957 { 958 struct ti_gpio_softc *sc; 959 int pin, err; 960 961 sc = device_get_softc(dev); 962 pin = rman_get_start(ires); 963 if (ti_gpio_valid_pin(sc, pin) != 0) 964 panic("%s: bad pin %d", __func__, pin); 965 if (sc->sc_events[pin] == NULL) 966 panic("Trying to teardown unoccupied IRQ"); 967 err = intr_event_remove_handler(cookie); 968 if (!err) 969 sc->sc_events[pin] = NULL; 970 971 return (err); 972 } 973 974 static phandle_t 975 ti_gpio_get_node(device_t bus, device_t dev) 976 { 977 978 /* We only have one child, the GPIO bus, which needs our own node. */ 979 return (ofw_bus_get_node(bus)); 980 } 981 982 static device_method_t ti_gpio_methods[] = { 983 DEVMETHOD(device_attach, ti_gpio_attach), 984 DEVMETHOD(device_detach, ti_gpio_detach), 985 986 /* GPIO protocol */ 987 DEVMETHOD(gpio_get_bus, ti_gpio_get_bus), 988 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 989 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 990 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 991 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 992 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 993 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 994 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 995 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 996 997 /* Bus interface */ 998 DEVMETHOD(bus_activate_resource, ti_gpio_activate_resource), 999 DEVMETHOD(bus_deactivate_resource, ti_gpio_deactivate_resource), 1000 DEVMETHOD(bus_config_intr, ti_gpio_config_intr), 1001 DEVMETHOD(bus_setup_intr, ti_gpio_setup_intr), 1002 DEVMETHOD(bus_teardown_intr, ti_gpio_teardown_intr), 1003 1004 /* ofw_bus interface */ 1005 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 1006 1007 {0, 0}, 1008 }; 1009 1010 driver_t ti_gpio_driver = { 1011 "gpio", 1012 ti_gpio_methods, 1013 sizeof(struct ti_gpio_softc), 1014 }; 1015