1 /*- 2 * Copyright (c) 2011 3 * Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /** 29 * Very simple GPIO (general purpose IO) driver module for TI OMAP SoC's. 30 * 31 * Currently this driver only does the basics, get a value on a pin & set a 32 * value on a pin. Hopefully over time I'll expand this to be a bit more generic 33 * and support interrupts and other various bits on the SoC can do ... in the 34 * meantime this is all you get. 35 * 36 * Beware the OMA datasheet(s) lists GPIO banks 1-6, whereas I've used 0-5 here 37 * in the code. 38 * 39 * 40 */ 41 42 #include <sys/cdefs.h> 43 __FBSDID("$FreeBSD$"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/bus.h> 48 49 #include <sys/kernel.h> 50 #include <sys/module.h> 51 #include <sys/rman.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/gpio.h> 55 56 #include <machine/bus.h> 57 #include <machine/resource.h> 58 59 #include <arm/ti/ti_cpuid.h> 60 #include <arm/ti/ti_gpio.h> 61 #include <arm/ti/ti_scm.h> 62 #include <arm/ti/ti_prcm.h> 63 64 #include <dev/fdt/fdt_common.h> 65 #include <dev/ofw/openfirm.h> 66 #include <dev/ofw/ofw_bus.h> 67 #include <dev/ofw/ofw_bus_subr.h> 68 69 #include "gpio_if.h" 70 #include "ti_gpio_if.h" 71 72 /* Register definitions */ 73 #define TI_GPIO_REVISION 0x0000 74 #define TI_GPIO_SYSCONFIG 0x0010 75 #if defined(SOC_OMAP4) || defined(SOC_TI_AM335X) 76 #define TI_GPIO_IRQSTATUS_RAW_0 0x0024 77 #define TI_GPIO_IRQSTATUS_RAW_1 0x0028 78 #define TI_GPIO_IRQSTATUS_0 0x002C 79 #define TI_GPIO_IRQSTATUS_1 0x0030 80 #define TI_GPIO_IRQSTATUS_SET_0 0x0034 81 #define TI_GPIO_IRQSTATUS_SET_1 0x0038 82 #define TI_GPIO_IRQSTATUS_CLR_0 0x003C 83 #define TI_GPIO_IRQSTATUS_CLR_1 0x0040 84 #define TI_GPIO_IRQWAKEN_0 0x0044 85 #define TI_GPIO_IRQWAKEN_1 0x0048 86 #define TI_GPIO_SYSSTATUS 0x0114 87 #define TI_GPIO_IRQSTATUS1 0x0118 88 #define TI_GPIO_IRQENABLE1 0x011C 89 #define TI_GPIO_WAKEUPENABLE 0x0120 90 #define TI_GPIO_IRQSTATUS2 0x0128 91 #define TI_GPIO_IRQENABLE2 0x012C 92 #define TI_GPIO_CTRL 0x0130 93 #define TI_GPIO_OE 0x0134 94 #define TI_GPIO_DATAIN 0x0138 95 #define TI_GPIO_DATAOUT 0x013C 96 #define TI_GPIO_LEVELDETECT0 0x0140 97 #define TI_GPIO_LEVELDETECT1 0x0144 98 #define TI_GPIO_RISINGDETECT 0x0148 99 #define TI_GPIO_FALLINGDETECT 0x014C 100 #define TI_GPIO_DEBOUNCENABLE 0x0150 101 #define TI_GPIO_DEBOUNCINGTIME 0x0154 102 #define TI_GPIO_CLEARWKUPENA 0x0180 103 #define TI_GPIO_SETWKUENA 0x0184 104 #define TI_GPIO_CLEARDATAOUT 0x0190 105 #define TI_GPIO_SETDATAOUT 0x0194 106 #else 107 #error "Unknown SoC" 108 #endif 109 110 /* Other SoC Specific definitions */ 111 #define OMAP4_MAX_GPIO_BANKS 6 112 #define OMAP4_FIRST_GPIO_BANK 1 113 #define OMAP4_INTR_PER_BANK 1 114 #define OMAP4_GPIO_REV 0x50600801 115 #define AM335X_MAX_GPIO_BANKS 4 116 #define AM335X_FIRST_GPIO_BANK 0 117 #define AM335X_INTR_PER_BANK 2 118 #define AM335X_GPIO_REV 0x50600801 119 #define PINS_PER_BANK 32 120 121 static u_int 122 ti_max_gpio_banks(void) 123 { 124 switch(ti_chip()) { 125 #ifdef SOC_OMAP4 126 case CHIP_OMAP_4: 127 return (OMAP4_MAX_GPIO_BANKS); 128 #endif 129 #ifdef SOC_TI_AM335X 130 case CHIP_AM335X: 131 return (AM335X_MAX_GPIO_BANKS); 132 #endif 133 } 134 return (0); 135 } 136 137 static u_int 138 ti_max_gpio_intrs(void) 139 { 140 switch(ti_chip()) { 141 #ifdef SOC_OMAP4 142 case CHIP_OMAP_4: 143 return (OMAP4_MAX_GPIO_BANKS * OMAP4_INTR_PER_BANK); 144 #endif 145 #ifdef SOC_TI_AM335X 146 case CHIP_AM335X: 147 return (AM335X_MAX_GPIO_BANKS * AM335X_INTR_PER_BANK); 148 #endif 149 } 150 return (0); 151 } 152 153 static u_int 154 ti_first_gpio_bank(void) 155 { 156 switch(ti_chip()) { 157 #ifdef SOC_OMAP4 158 case CHIP_OMAP_4: 159 return (OMAP4_FIRST_GPIO_BANK); 160 #endif 161 #ifdef SOC_TI_AM335X 162 case CHIP_AM335X: 163 return (AM335X_FIRST_GPIO_BANK); 164 #endif 165 } 166 return (0); 167 } 168 169 static uint32_t 170 ti_gpio_rev(void) 171 { 172 switch(ti_chip()) { 173 #ifdef SOC_OMAP4 174 case CHIP_OMAP_4: 175 return (OMAP4_GPIO_REV); 176 #endif 177 #ifdef SOC_TI_AM335X 178 case CHIP_AM335X: 179 return (AM335X_GPIO_REV); 180 #endif 181 } 182 return (0); 183 } 184 185 /** 186 * ti_gpio_mem_spec - Resource specification used when allocating resources 187 * ti_gpio_irq_spec - Resource specification used when allocating resources 188 * 189 * This driver module can have up to six independent memory regions, each 190 * region typically controls 32 GPIO pins. 191 * 192 * On OMAP3 and OMAP4 there is only one physical interrupt line per bank, 193 * but there are two set of registers which control the interrupt delivery 194 * to internal subsystems. The first set of registers control the 195 * interrupts delivery to the MPU and the second set control the 196 * interrupts delivery to the DSP. 197 * 198 * On AM335x there are two physical interrupt lines for each GPIO module. 199 * Each interrupt line is controlled by a set of registers. 200 */ 201 static struct resource_spec ti_gpio_mem_spec[] = { 202 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 203 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL }, 204 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL }, 205 { SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL }, 206 #if !defined(SOC_TI_AM335X) 207 { SYS_RES_MEMORY, 4, RF_ACTIVE | RF_OPTIONAL }, 208 { SYS_RES_MEMORY, 5, RF_ACTIVE | RF_OPTIONAL }, 209 #endif 210 { -1, 0, 0 } 211 }; 212 static struct resource_spec ti_gpio_irq_spec[] = { 213 { SYS_RES_IRQ, 0, RF_ACTIVE }, 214 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, 215 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, 216 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL }, 217 { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL }, 218 { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL }, 219 #if defined(SOC_TI_AM335X) 220 { SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL }, 221 { SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL }, 222 #endif 223 { -1, 0, 0 } 224 }; 225 226 /** 227 * Macros for driver mutex locking 228 */ 229 #define TI_GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 230 #define TI_GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 231 #define TI_GPIO_LOCK_INIT(_sc) \ 232 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 233 "ti_gpio", MTX_DEF) 234 #define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx) 235 #define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) 236 #define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED) 237 238 /** 239 * ti_gpio_read_4 - reads a 16-bit value from one of the PADCONFS registers 240 * @sc: GPIO device context 241 * @bank: The bank to read from 242 * @off: The offset of a register from the GPIO register address range 243 * 244 * 245 * RETURNS: 246 * 32-bit value read from the register. 247 */ 248 static inline uint32_t 249 ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off) 250 { 251 return (bus_read_4(sc->sc_mem_res[bank], off)); 252 } 253 254 /** 255 * ti_gpio_write_4 - writes a 32-bit value to one of the PADCONFS registers 256 * @sc: GPIO device context 257 * @bank: The bank to write to 258 * @off: The offset of a register from the GPIO register address range 259 * @val: The value to write into the register 260 * 261 * RETURNS: 262 * nothing 263 */ 264 static inline void 265 ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off, 266 uint32_t val) 267 { 268 bus_write_4(sc->sc_mem_res[bank], off, val); 269 } 270 271 static inline void 272 ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask) 273 { 274 275 /* We clear both set of registers. */ 276 #if defined(SOC_OMAP4) || defined(SOC_TI_AM335X) 277 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask); 278 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask); 279 #else 280 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE1, mask); 281 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARIRQENABLE2, mask); 282 #endif 283 } 284 285 /** 286 * ti_gpio_pin_max - Returns the maximum number of GPIO pins 287 * @dev: gpio device handle 288 * @maxpin: pointer to a value that upon return will contain the maximum number 289 * of pins in the device. 290 * 291 * 292 * LOCKING: 293 * Internally locks the context 294 * 295 * RETURNS: 296 * Returns 0 on success otherwise an error code 297 */ 298 static int 299 ti_gpio_pin_max(device_t dev, int *maxpin) 300 { 301 struct ti_gpio_softc *sc = device_get_softc(dev); 302 unsigned int i; 303 unsigned int banks = 0; 304 305 TI_GPIO_LOCK(sc); 306 307 /* Calculate how many valid banks we have and then multiply that by 32 to 308 * give use the total number of pins. 309 */ 310 for (i = 0; i < ti_max_gpio_banks(); i++) { 311 if (sc->sc_mem_res[i] != NULL) 312 banks++; 313 } 314 315 *maxpin = (banks * PINS_PER_BANK) - 1; 316 317 TI_GPIO_UNLOCK(sc); 318 319 return (0); 320 } 321 322 /** 323 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin 324 * @dev: gpio device handle 325 * @pin: the number of the pin 326 * @caps: pointer to a value that upon return will contain the capabilities 327 * 328 * Currently all pins have the same capability, notably: 329 * - GPIO_PIN_INPUT 330 * - GPIO_PIN_OUTPUT 331 * - GPIO_PIN_PULLUP 332 * - GPIO_PIN_PULLDOWN 333 * 334 * LOCKING: 335 * Internally locks the context 336 * 337 * RETURNS: 338 * Returns 0 on success otherwise an error code 339 */ 340 static int 341 ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 342 { 343 struct ti_gpio_softc *sc = device_get_softc(dev); 344 uint32_t bank = (pin / PINS_PER_BANK); 345 346 TI_GPIO_LOCK(sc); 347 348 /* Sanity check the pin number is valid */ 349 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 350 TI_GPIO_UNLOCK(sc); 351 return (EINVAL); 352 } 353 354 *caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |GPIO_PIN_PULLUP | 355 GPIO_PIN_PULLDOWN); 356 357 TI_GPIO_UNLOCK(sc); 358 359 return (0); 360 } 361 362 /** 363 * ti_gpio_pin_getflags - Gets the current flags of a given pin 364 * @dev: gpio device handle 365 * @pin: the number of the pin 366 * @flags: upon return will contain the current flags of the pin 367 * 368 * Reads the current flags of a given pin, here we actually read the H/W 369 * registers to determine the flags, rather than storing the value in the 370 * setflags call. 371 * 372 * LOCKING: 373 * Internally locks the context 374 * 375 * RETURNS: 376 * Returns 0 on success otherwise an error code 377 */ 378 static int 379 ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 380 { 381 struct ti_gpio_softc *sc = device_get_softc(dev); 382 uint32_t bank = (pin / PINS_PER_BANK); 383 384 TI_GPIO_LOCK(sc); 385 386 /* Sanity check the pin number is valid */ 387 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 388 TI_GPIO_UNLOCK(sc); 389 return (EINVAL); 390 } 391 392 /* Get the current pin state */ 393 TI_GPIO_GET_FLAGS(dev, pin, flags); 394 395 TI_GPIO_UNLOCK(sc); 396 397 return (0); 398 } 399 400 /** 401 * ti_gpio_pin_getname - Gets the name of a given pin 402 * @dev: gpio device handle 403 * @pin: the number of the pin 404 * @name: buffer to put the name in 405 * 406 * The driver simply calls the pins gpio_n, where 'n' is obviously the number 407 * of the pin. 408 * 409 * LOCKING: 410 * Internally locks the context 411 * 412 * RETURNS: 413 * Returns 0 on success otherwise an error code 414 */ 415 static int 416 ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 417 { 418 struct ti_gpio_softc *sc = device_get_softc(dev); 419 uint32_t bank = (pin / PINS_PER_BANK); 420 421 TI_GPIO_LOCK(sc); 422 423 /* Sanity check the pin number is valid */ 424 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 425 TI_GPIO_UNLOCK(sc); 426 return (EINVAL); 427 } 428 429 /* Set a very simple name */ 430 snprintf(name, GPIOMAXNAME, "gpio_%u", pin); 431 name[GPIOMAXNAME - 1] = '\0'; 432 433 TI_GPIO_UNLOCK(sc); 434 435 return (0); 436 } 437 438 /** 439 * ti_gpio_pin_setflags - Sets the flags for a given pin 440 * @dev: gpio device handle 441 * @pin: the number of the pin 442 * @flags: the flags to set 443 * 444 * The flags of the pin correspond to things like input/output mode, pull-ups, 445 * pull-downs, etc. This driver doesn't support all flags, only the following: 446 * - GPIO_PIN_INPUT 447 * - GPIO_PIN_OUTPUT 448 * - GPIO_PIN_PULLUP 449 * - GPIO_PIN_PULLDOWN 450 * 451 * LOCKING: 452 * Internally locks the context 453 * 454 * RETURNS: 455 * Returns 0 on success otherwise an error code 456 */ 457 static int 458 ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 459 { 460 struct ti_gpio_softc *sc = device_get_softc(dev); 461 uint32_t bank = (pin / PINS_PER_BANK); 462 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 463 uint32_t reg_val; 464 465 /* Sanity check the flags supplied are valid, i.e. not input and output */ 466 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 0x0000) 467 return (EINVAL); 468 if ((flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) == 469 (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) 470 return (EINVAL); 471 if ((flags & (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) == 472 (GPIO_PIN_PULLUP|GPIO_PIN_PULLDOWN)) 473 return (EINVAL); 474 475 TI_GPIO_LOCK(sc); 476 477 /* Sanity check the pin number is valid */ 478 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 479 TI_GPIO_UNLOCK(sc); 480 return (EINVAL); 481 } 482 483 /* Set the GPIO mode and state */ 484 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) { 485 TI_GPIO_UNLOCK(sc); 486 return (EINVAL); 487 } 488 489 /* If configuring as an output set the "output enable" bit */ 490 reg_val = ti_gpio_read_4(sc, bank, TI_GPIO_OE); 491 if (flags & GPIO_PIN_INPUT) 492 reg_val |= mask; 493 else 494 reg_val &= ~mask; 495 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_val); 496 497 TI_GPIO_UNLOCK(sc); 498 499 return (0); 500 } 501 502 /** 503 * ti_gpio_pin_set - Sets the current level on a GPIO pin 504 * @dev: gpio device handle 505 * @pin: the number of the pin 506 * @value: non-zero value will drive the pin high, otherwise the pin is 507 * driven low. 508 * 509 * 510 * LOCKING: 511 * Internally locks the context 512 * 513 * RETURNS: 514 * Returns 0 on success otherwise a error code 515 */ 516 static int 517 ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 518 { 519 struct ti_gpio_softc *sc = device_get_softc(dev); 520 uint32_t bank = (pin / PINS_PER_BANK); 521 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 522 523 TI_GPIO_LOCK(sc); 524 525 /* Sanity check the pin number is valid */ 526 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 527 TI_GPIO_UNLOCK(sc); 528 return (EINVAL); 529 } 530 531 ti_gpio_write_4(sc, bank, (value == GPIO_PIN_LOW) ? TI_GPIO_CLEARDATAOUT 532 : TI_GPIO_SETDATAOUT, mask); 533 534 TI_GPIO_UNLOCK(sc); 535 536 return (0); 537 } 538 539 /** 540 * ti_gpio_pin_get - Gets the current level on a GPIO pin 541 * @dev: gpio device handle 542 * @pin: the number of the pin 543 * @value: pointer to a value that upond return will contain the pin value 544 * 545 * The pin must be configured as an input pin beforehand, otherwise this 546 * function will fail. 547 * 548 * LOCKING: 549 * Internally locks the context 550 * 551 * RETURNS: 552 * Returns 0 on success otherwise a error code 553 */ 554 static int 555 ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) 556 { 557 struct ti_gpio_softc *sc = device_get_softc(dev); 558 uint32_t bank = (pin / PINS_PER_BANK); 559 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 560 uint32_t val = 0; 561 562 TI_GPIO_LOCK(sc); 563 564 /* Sanity check the pin number is valid */ 565 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 566 TI_GPIO_UNLOCK(sc); 567 return (EINVAL); 568 } 569 570 /* Sanity check the pin is not configured as an output */ 571 val = ti_gpio_read_4(sc, bank, TI_GPIO_OE); 572 573 /* Read the value on the pin */ 574 if (val & mask) 575 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAIN) & mask) ? 1 : 0; 576 else 577 *value = (ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT) & mask) ? 1 : 0; 578 579 TI_GPIO_UNLOCK(sc); 580 581 return (0); 582 } 583 584 /** 585 * ti_gpio_pin_toggle - Toggles a given GPIO pin 586 * @dev: gpio device handle 587 * @pin: the number of the pin 588 * 589 * 590 * LOCKING: 591 * Internally locks the context 592 * 593 * RETURNS: 594 * Returns 0 on success otherwise a error code 595 */ 596 static int 597 ti_gpio_pin_toggle(device_t dev, uint32_t pin) 598 { 599 struct ti_gpio_softc *sc = device_get_softc(dev); 600 uint32_t bank = (pin / PINS_PER_BANK); 601 uint32_t mask = (1UL << (pin % PINS_PER_BANK)); 602 uint32_t val; 603 604 TI_GPIO_LOCK(sc); 605 606 /* Sanity check the pin number is valid */ 607 if ((bank >= ti_max_gpio_banks()) || (sc->sc_mem_res[bank] == NULL)) { 608 TI_GPIO_UNLOCK(sc); 609 return (EINVAL); 610 } 611 612 /* Toggle the pin */ 613 val = ti_gpio_read_4(sc, bank, TI_GPIO_DATAOUT); 614 if (val & mask) 615 ti_gpio_write_4(sc, bank, TI_GPIO_CLEARDATAOUT, mask); 616 else 617 ti_gpio_write_4(sc, bank, TI_GPIO_SETDATAOUT, mask); 618 619 TI_GPIO_UNLOCK(sc); 620 621 return (0); 622 } 623 624 /** 625 * ti_gpio_intr - ISR for all GPIO modules 626 * @arg: the soft context pointer 627 * 628 * Unsused 629 * 630 * LOCKING: 631 * Internally locks the context 632 * 633 */ 634 static void 635 ti_gpio_intr(void *arg) 636 { 637 struct ti_gpio_softc *sc = arg; 638 639 TI_GPIO_LOCK(sc); 640 /* TODO: something useful */ 641 TI_GPIO_UNLOCK(sc); 642 } 643 644 static int 645 ti_gpio_attach_intr(device_t dev) 646 { 647 int i; 648 struct ti_gpio_softc *sc; 649 650 sc = device_get_softc(dev); 651 for (i = 0; i < ti_max_gpio_intrs(); i++) { 652 if (sc->sc_irq_res[i] == NULL) 653 break; 654 655 /* 656 * Register our interrupt handler for each of the IRQ resources. 657 */ 658 if (bus_setup_intr(dev, sc->sc_irq_res[i], 659 INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_gpio_intr, sc, 660 &sc->sc_irq_hdl[i]) != 0) { 661 device_printf(dev, 662 "WARNING: unable to register interrupt handler\n"); 663 return (-1); 664 } 665 } 666 667 return (0); 668 } 669 670 static int 671 ti_gpio_detach_intr(device_t dev) 672 { 673 int i; 674 struct ti_gpio_softc *sc; 675 676 /* Teardown our interrupt handlers. */ 677 sc = device_get_softc(dev); 678 for (i = 0; i < ti_max_gpio_intrs(); i++) { 679 if (sc->sc_irq_res[i] == NULL) 680 break; 681 682 if (sc->sc_irq_hdl[i]) { 683 bus_teardown_intr(dev, sc->sc_irq_res[i], 684 sc->sc_irq_hdl[i]); 685 } 686 } 687 688 return (0); 689 } 690 691 static int 692 ti_gpio_bank_init(device_t dev, int bank) 693 { 694 int pin; 695 struct ti_gpio_softc *sc; 696 uint32_t flags, reg_oe; 697 698 sc = device_get_softc(dev); 699 700 /* Enable the interface and functional clocks for the module. */ 701 ti_prcm_clk_enable(GPIO0_CLK + ti_first_gpio_bank() + bank); 702 703 /* 704 * Read the revision number of the module. TI don't publish the 705 * actual revision numbers, so instead the values have been 706 * determined by experimentation. 707 */ 708 sc->sc_revision[bank] = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION); 709 710 /* Check the revision. */ 711 if (sc->sc_revision[bank] != ti_gpio_rev()) { 712 device_printf(dev, "Warning: could not determine the revision " 713 "of %u GPIO module (revision:0x%08x)\n", 714 bank, sc->sc_revision[bank]); 715 return (EINVAL); 716 } 717 718 /* Disable interrupts for all pins. */ 719 ti_gpio_intr_clr(sc, bank, 0xffffffff); 720 721 /* Init OE register based on pads configuration. */ 722 reg_oe = 0xffffffff; 723 for (pin = 0; pin < PINS_PER_BANK; pin++) { 724 TI_GPIO_GET_FLAGS(dev, PINS_PER_BANK * bank + pin, &flags); 725 if (flags & GPIO_PIN_OUTPUT) 726 reg_oe &= ~(1UL << pin); 727 } 728 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe); 729 730 return (0); 731 } 732 733 /** 734 * ti_gpio_attach - attach function for the driver 735 * @dev: gpio device handle 736 * 737 * Allocates and sets up the driver context for all GPIO banks. This function 738 * expects the memory ranges and IRQs to already be allocated to the driver. 739 * 740 * LOCKING: 741 * None 742 * 743 * RETURNS: 744 * Always returns 0 745 */ 746 static int 747 ti_gpio_attach(device_t dev) 748 { 749 struct ti_gpio_softc *sc; 750 unsigned int i; 751 int err; 752 753 sc = device_get_softc(dev); 754 sc->sc_dev = dev; 755 756 TI_GPIO_LOCK_INIT(sc); 757 758 /* There are up to 6 different GPIO register sets located in different 759 * memory areas on the chip. The memory range should have been set for 760 * the driver when it was added as a child. 761 */ 762 if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) { 763 device_printf(dev, "Error: could not allocate mem resources\n"); 764 return (ENXIO); 765 } 766 767 /* Request the IRQ resources */ 768 if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) { 769 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); 770 device_printf(dev, "Error: could not allocate irq resources\n"); 771 return (ENXIO); 772 } 773 774 /* Setup the IRQ resources */ 775 if (ti_gpio_attach_intr(dev) != 0) { 776 ti_gpio_detach_intr(dev); 777 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res); 778 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); 779 return (ENXIO); 780 } 781 782 /* We need to go through each block and ensure the clocks are running and 783 * the module is enabled. It might be better to do this only when the 784 * pins are configured which would result in less power used if the GPIO 785 * pins weren't used ... 786 */ 787 for (i = 0; i < ti_max_gpio_banks(); i++) { 788 if (sc->sc_mem_res[i] != NULL) { 789 /* Initialize the GPIO module. */ 790 err = ti_gpio_bank_init(dev, i); 791 if (err != 0) { 792 ti_gpio_detach_intr(dev); 793 bus_release_resources(dev, ti_gpio_irq_spec, 794 sc->sc_irq_res); 795 bus_release_resources(dev, ti_gpio_mem_spec, 796 sc->sc_mem_res); 797 return (err); 798 } 799 } 800 } 801 802 /* Finish of the probe call */ 803 device_add_child(dev, "gpioc", device_get_unit(dev)); 804 device_add_child(dev, "gpiobus", device_get_unit(dev)); 805 806 return (bus_generic_attach(dev)); 807 } 808 809 /** 810 * ti_gpio_detach - detach function for the driver 811 * @dev: scm device handle 812 * 813 * Allocates and sets up the driver context, this simply entails creating a 814 * bus mappings for the SCM register set. 815 * 816 * LOCKING: 817 * None 818 * 819 * RETURNS: 820 * Always returns 0 821 */ 822 static int 823 ti_gpio_detach(device_t dev) 824 { 825 struct ti_gpio_softc *sc = device_get_softc(dev); 826 unsigned int i; 827 828 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); 829 830 /* Disable all interrupts */ 831 for (i = 0; i < ti_max_gpio_banks(); i++) { 832 if (sc->sc_mem_res[i] != NULL) 833 ti_gpio_intr_clr(sc, i, 0xffffffff); 834 } 835 836 bus_generic_detach(dev); 837 838 /* Release the memory and IRQ resources. */ 839 ti_gpio_detach_intr(dev); 840 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res); 841 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res); 842 843 TI_GPIO_LOCK_DESTROY(sc); 844 845 return (0); 846 } 847 848 static phandle_t 849 ti_gpio_get_node(device_t bus, device_t dev) 850 { 851 852 /* We only have one child, the GPIO bus, which needs our own node. */ 853 return (ofw_bus_get_node(bus)); 854 } 855 856 static device_method_t ti_gpio_methods[] = { 857 DEVMETHOD(device_attach, ti_gpio_attach), 858 DEVMETHOD(device_detach, ti_gpio_detach), 859 860 /* GPIO protocol */ 861 DEVMETHOD(gpio_pin_max, ti_gpio_pin_max), 862 DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname), 863 DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags), 864 DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps), 865 DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags), 866 DEVMETHOD(gpio_pin_get, ti_gpio_pin_get), 867 DEVMETHOD(gpio_pin_set, ti_gpio_pin_set), 868 DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle), 869 870 /* ofw_bus interface */ 871 DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node), 872 873 {0, 0}, 874 }; 875 876 driver_t ti_gpio_driver = { 877 "gpio", 878 ti_gpio_methods, 879 sizeof(struct ti_gpio_softc), 880 }; 881