1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _TI_EDMA3_H_ 30 #define _TI_EDMA3_H_ 31 32 /* Direct Mapped EDMA3 Events */ 33 #define TI_EDMA3_EVENT_SDTXEVT1 2 34 #define TI_EDMA3_EVENT_SDRXEVT1 3 35 #define TI_EDMA3_EVENT_SDTXEVT0 24 36 #define TI_EDMA3_EVENT_SDRXEVT0 25 37 38 struct ti_edma3cc_param_set { 39 struct { 40 uint32_t sam:1; /* Source address mode */ 41 uint32_t dam:1; /* Destination address mode */ 42 uint32_t syncdim:1; /* Transfer synchronization dimension */ 43 uint32_t static_set:1; /* Static Set */ 44 uint32_t :4; 45 uint32_t fwid:3; /* FIFO Width */ 46 uint32_t tccmode:1; /* Transfer complete code mode */ 47 uint32_t tcc:6; /* Transfer complete code */ 48 uint32_t :2; 49 uint32_t tcinten:1; /* Transfer complete interrupt enable */ 50 uint32_t itcinten:1; /* Intermediate xfer completion intr. ena */ 51 uint32_t tcchen:1; /* Transfer complete chaining enable */ 52 uint32_t itcchen:1; /* Intermediate xfer completion chaining ena */ 53 uint32_t privid:4; /* Privilege identification */ 54 uint32_t :3; 55 uint32_t priv:1; /* Privilege level */ 56 } opt; 57 uint32_t src; /* Channel Source Address */ 58 uint16_t acnt; /* Count for 1st Dimension */ 59 uint16_t bcnt; /* Count for 2nd Dimension */ 60 uint32_t dst; /* Channel Destination Address */ 61 int16_t srcbidx; /* Source B Index */ 62 int16_t dstbidx; /* Destination B Index */ 63 uint16_t link; /* Link Address */ 64 uint16_t bcntrld; /* BCNT Reload */ 65 int16_t srccidx; /* Source C Index */ 66 int16_t dstcidx; /* Destination C Index */ 67 uint16_t ccnt; /* Count for 3rd Dimension */ 68 uint16_t reserved; /* Reserved */ 69 }; 70 71 void ti_edma3_init(unsigned int eqn); 72 int ti_edma3_request_dma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn); 73 int ti_edma3_request_qdma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn); 74 int ti_edma3_enable_transfer_manual(unsigned int ch); 75 int ti_edma3_enable_transfer_qdma(unsigned int ch); 76 int ti_edma3_enable_transfer_event(unsigned int ch); 77 78 void ti_edma3_param_write(unsigned int ch, struct ti_edma3cc_param_set *prs); 79 void ti_edma3_param_read(unsigned int ch, struct ti_edma3cc_param_set *prs); 80 81 #endif /* _TI_EDMA3_H_ */ 82