1 /*- 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of authors nor the names of its contributors may be 15 * used to endorse or promote products derived from this software without 16 * specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/endian.h> 37 #include <sys/mbuf.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 45 #include <sys/sockio.h> 46 #include <sys/bus.h> 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <machine/resource.h> 50 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 54 #include <arm/ti/ti_scm.h> 55 #include <arm/ti/ti_prcm.h> 56 57 #include <arm/ti/ti_edma3.h> 58 59 #define TI_EDMA3_NUM_TCS 3 60 #define TI_EDMA3_NUM_IRQS 3 61 #define TI_EDMA3_NUM_DMA_CHS 64 62 #define TI_EDMA3_NUM_QDMA_CHS 8 63 64 #define TI_EDMA3CC_PID 0x000 65 #define TI_EDMA3CC_DCHMAP(p) (0x100 + ((p)*4)) 66 #define TI_EDMA3CC_DMAQNUM(n) (0x240 + ((n)*4)) 67 #define TI_EDMA3CC_QDMAQNUM 0x260 68 #define TI_EDMA3CC_EMCR 0x308 69 #define TI_EDMA3CC_EMCRH 0x30C 70 #define TI_EDMA3CC_QEMCR 0x314 71 #define TI_EDMA3CC_CCERR 0x318 72 #define TI_EDMA3CC_CCERRCLR 0x31C 73 #define TI_EDMA3CC_DRAE(p) (0x340 + ((p)*8)) 74 #define TI_EDMA3CC_DRAEH(p) (0x344 + ((p)*8)) 75 #define TI_EDMA3CC_QRAE(p) (0x380 + ((p)*4)) 76 #define TI_EDMA3CC_S_ESR(p) (0x2010 + ((p)*0x200)) 77 #define TI_EDMA3CC_S_ESRH(p) (0x2014 + ((p)*0x200)) 78 #define TI_EDMA3CC_S_SECR(p) (0x2040 + ((p)*0x200)) 79 #define TI_EDMA3CC_S_SECRH(p) (0x2044 + ((p)*0x200)) 80 #define TI_EDMA3CC_S_EESR(p) (0x2030 + ((p)*0x200)) 81 #define TI_EDMA3CC_S_EESRH(p) (0x2034 + ((p)*0x200)) 82 #define TI_EDMA3CC_S_IESR(p) (0x2060 + ((p)*0x200)) 83 #define TI_EDMA3CC_S_IESRH(p) (0x2064 + ((p)*0x200)) 84 #define TI_EDMA3CC_S_IPR(p) (0x2068 + ((p)*0x200)) 85 #define TI_EDMA3CC_S_IPRH(p) (0x206C + ((p)*0x200)) 86 #define TI_EDMA3CC_S_QEESR(p) (0x208C + ((p)*0x200)) 87 88 #define TI_EDMA3CC_PARAM_OFFSET 0x4000 89 #define TI_EDMA3CC_OPT(p) (TI_EDMA3CC_PARAM_OFFSET + 0x0 + ((p)*0x20)) 90 91 #define TI_EDMA3CC_DMAQNUM_SET(c,q) ((0x7 & (q)) << (((c) % 8) * 4)) 92 #define TI_EDMA3CC_DMAQNUM_CLR(c) (~(0x7 << (((c) % 8) * 4))) 93 #define TI_EDMA3CC_QDMAQNUM_SET(c,q) ((0x7 & (q)) << ((c) * 4)) 94 #define TI_EDMA3CC_QDMAQNUM_CLR(c) (~(0x7 << ((c) * 4))) 95 96 #define TI_EDMA3CC_OPT_TCC_CLR (~(0x3F000)) 97 #define TI_EDMA3CC_OPT_TCC_SET(p) (((0x3F000 >> 12) & (p)) << 12) 98 99 struct ti_edma3_softc { 100 device_t sc_dev; 101 /* 102 * We use one-element array in case if we need to add 103 * mem resources for transfer control windows 104 */ 105 struct resource * mem_res[1]; 106 struct resource * irq_res[TI_EDMA3_NUM_IRQS]; 107 void *ih_cookie[TI_EDMA3_NUM_IRQS]; 108 }; 109 110 static struct ti_edma3_softc *ti_edma3_sc = NULL; 111 112 static struct resource_spec ti_edma3_mem_spec[] = { 113 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 114 { -1, 0, 0 } 115 }; 116 static struct resource_spec ti_edma3_irq_spec[] = { 117 { SYS_RES_IRQ, 0, RF_ACTIVE }, 118 { SYS_RES_IRQ, 1, RF_ACTIVE }, 119 { SYS_RES_IRQ, 2, RF_ACTIVE }, 120 { -1, 0, 0 } 121 }; 122 123 /* Read/Write macros */ 124 #define ti_edma3_cc_rd_4(reg) bus_read_4(ti_edma3_sc->mem_res[0], reg) 125 #define ti_edma3_cc_wr_4(reg, val) bus_write_4(ti_edma3_sc->mem_res[0], reg, val) 126 127 static void ti_edma3_intr_comp(void *arg); 128 static void ti_edma3_intr_mperr(void *arg); 129 static void ti_edma3_intr_err(void *arg); 130 131 static struct { 132 driver_intr_t *handler; 133 char * description; 134 } ti_edma3_intrs[TI_EDMA3_NUM_IRQS] = { 135 { ti_edma3_intr_comp, "EDMA Completion Interrupt" }, 136 { ti_edma3_intr_mperr, "EDMA Memory Protection Error Interrupt" }, 137 { ti_edma3_intr_err, "EDMA Error Interrupt" }, 138 }; 139 140 static int 141 ti_edma3_probe(device_t dev) 142 { 143 144 if (!ofw_bus_status_okay(dev)) 145 return (ENXIO); 146 147 if (!ofw_bus_is_compatible(dev, "ti,edma3")) 148 return (ENXIO); 149 150 device_set_desc(dev, "TI EDMA Controller"); 151 return (0); 152 } 153 154 static int 155 ti_edma3_attach(device_t dev) 156 { 157 struct ti_edma3_softc *sc = device_get_softc(dev); 158 uint32_t reg; 159 int err; 160 int i; 161 162 if (ti_edma3_sc) 163 return (ENXIO); 164 165 ti_edma3_sc = sc; 166 sc->sc_dev = dev; 167 168 /* Request the memory resources */ 169 err = bus_alloc_resources(dev, ti_edma3_mem_spec, sc->mem_res); 170 if (err) { 171 device_printf(dev, "Error: could not allocate mem resources\n"); 172 return (ENXIO); 173 } 174 175 /* Request the IRQ resources */ 176 err = bus_alloc_resources(dev, ti_edma3_irq_spec, sc->irq_res); 177 if (err) { 178 device_printf(dev, "Error: could not allocate irq resources\n"); 179 return (ENXIO); 180 } 181 182 /* Enable Channel Controller */ 183 ti_prcm_clk_enable(EDMA_TPCC_CLK); 184 185 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_PID); 186 187 device_printf(dev, "EDMA revision %08x\n", reg); 188 189 190 /* Attach interrupt handlers */ 191 for (i = 0; i < TI_EDMA3_NUM_IRQS; ++i) { 192 err = bus_setup_intr(dev, sc->irq_res[i], INTR_TYPE_MISC | 193 INTR_MPSAFE, NULL, *ti_edma3_intrs[i].handler, 194 sc, &sc->ih_cookie[i]); 195 if (err) { 196 device_printf(dev, "could not setup %s\n", 197 ti_edma3_intrs[i].description); 198 return (err); 199 } 200 } 201 202 return (0); 203 } 204 205 static device_method_t ti_edma3_methods[] = { 206 DEVMETHOD(device_probe, ti_edma3_probe), 207 DEVMETHOD(device_attach, ti_edma3_attach), 208 {0, 0}, 209 }; 210 211 static driver_t ti_edma3_driver = { 212 "ti_edma3", 213 ti_edma3_methods, 214 sizeof(struct ti_edma3_softc), 215 }; 216 static devclass_t ti_edma3_devclass; 217 218 DRIVER_MODULE(ti_edma3, simplebus, ti_edma3_driver, ti_edma3_devclass, 0, 0); 219 MODULE_DEPEND(ti_edma3, ti_prcm, 1, 1, 1); 220 221 static void 222 ti_edma3_intr_comp(void *arg) 223 { 224 printf("%s: unimplemented\n", __func__); 225 } 226 227 static void 228 ti_edma3_intr_mperr(void *arg) 229 { 230 printf("%s: unimplemented\n", __func__); 231 } 232 233 static void 234 ti_edma3_intr_err(void *arg) 235 { 236 printf("%s: unimplemented\n", __func__); 237 } 238 239 void 240 ti_edma3_init(unsigned int eqn) 241 { 242 uint32_t reg; 243 int i; 244 245 /* on AM335x Event queue 0 is always mapped to Transfer Controller 0, 246 * event queue 1 to TC2, etc. So we are asking PRCM to power on specific 247 * TC based on what event queue we need to initialize */ 248 ti_prcm_clk_enable(EDMA_TPTC0_CLK + eqn); 249 250 /* Clear Event Missed Regs */ 251 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, 0xFFFFFFFF); 252 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 0xFFFFFFFF); 253 ti_edma3_cc_wr_4(TI_EDMA3CC_QEMCR, 0xFFFFFFFF); 254 255 /* Clear Error Reg */ 256 ti_edma3_cc_wr_4(TI_EDMA3CC_CCERRCLR, 0xFFFFFFFF); 257 258 /* Enable DMA channels 0-63 */ 259 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), 0xFFFFFFFF); 260 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), 0xFFFFFFFF); 261 262 for (i = 0; i < 64; i++) { 263 ti_edma3_cc_wr_4(TI_EDMA3CC_DCHMAP(i), i<<5); 264 } 265 266 /* Initialize the DMA Queue Number Registers */ 267 for (i = 0; i < TI_EDMA3_NUM_DMA_CHS; i++) { 268 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(i>>3)); 269 reg &= TI_EDMA3CC_DMAQNUM_CLR(i); 270 reg |= TI_EDMA3CC_DMAQNUM_SET(i, eqn); 271 ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(i>>3), reg); 272 } 273 274 /* Enable the QDMA Region access for all channels */ 275 ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), (1 << TI_EDMA3_NUM_QDMA_CHS) - 1); 276 277 /*Initialize QDMA Queue Number Registers */ 278 for (i = 0; i < TI_EDMA3_NUM_QDMA_CHS; i++) { 279 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM); 280 reg &= TI_EDMA3CC_QDMAQNUM_CLR(i); 281 reg |= TI_EDMA3CC_QDMAQNUM_SET(i, eqn); 282 ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg); 283 } 284 } 285 286 #ifdef notyet 287 int 288 ti_edma3_enable_event_intr(unsigned int ch) 289 { 290 uint32_t reg; 291 292 if (ch >= TI_EDMA3_NUM_DMA_CHS) 293 return (EINVAL); 294 295 if (ch < 32) { 296 ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESR(0), 1 << ch); 297 } else { 298 ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESRH(0), 1 << (ch - 32)); 299 } 300 return 0; 301 } 302 #endif 303 304 int 305 ti_edma3_request_dma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn) 306 { 307 uint32_t reg; 308 309 if (ch >= TI_EDMA3_NUM_DMA_CHS) 310 return (EINVAL); 311 312 /* Enable the DMA channel in the DRAE/DRAEH registers */ 313 if (ch < 32) { 314 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAE(0)); 315 reg |= (0x01 << ch); 316 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), reg); 317 } else { 318 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAEH(0)); 319 reg |= (0x01 << (ch - 32)); 320 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), reg); 321 } 322 323 /* Associate DMA Channel to Event Queue */ 324 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(ch >> 3)); 325 reg &= TI_EDMA3CC_DMAQNUM_CLR(ch); 326 reg |= TI_EDMA3CC_DMAQNUM_SET((ch), eqn); 327 ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(ch >> 3), reg); 328 329 /* Set TCC in corresponding PaRAM Entry */ 330 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch)); 331 reg &= TI_EDMA3CC_OPT_TCC_CLR; 332 reg |= TI_EDMA3CC_OPT_TCC_SET(ch); 333 ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg); 334 335 return 0; 336 } 337 338 int 339 ti_edma3_request_qdma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn) 340 { 341 uint32_t reg; 342 343 if (ch >= TI_EDMA3_NUM_DMA_CHS) 344 return (EINVAL); 345 346 /* Enable the QDMA channel in the QRAE registers */ 347 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QRAE(0)); 348 reg |= (0x01 << ch); 349 ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), reg); 350 351 /* Associate QDMA Channel to Event Queue */ 352 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM); 353 reg |= TI_EDMA3CC_QDMAQNUM_SET(ch, eqn); 354 ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg); 355 356 /* Set TCC in corresponding PaRAM Entry */ 357 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch)); 358 reg &= TI_EDMA3CC_OPT_TCC_CLR; 359 reg |= TI_EDMA3CC_OPT_TCC_SET(ch); 360 ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg); 361 362 return 0; 363 } 364 365 int 366 ti_edma3_enable_transfer_manual(unsigned int ch) 367 { 368 if (ch >= TI_EDMA3_NUM_DMA_CHS) 369 return (EINVAL); 370 371 /* set corresponding bit in ESR/ESRH to set a event */ 372 if (ch < 32) { 373 ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESR(0), 1 << ch); 374 } else { 375 ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESRH(0), 1 << (ch - 32)); 376 } 377 378 return 0; 379 } 380 381 int 382 ti_edma3_enable_transfer_qdma(unsigned int ch) 383 { 384 if (ch >= TI_EDMA3_NUM_QDMA_CHS) 385 return (EINVAL); 386 387 /* set corresponding bit in QEESR to enable QDMA event */ 388 ti_edma3_cc_wr_4(TI_EDMA3CC_S_QEESR(0), (1 << ch)); 389 390 return 0; 391 } 392 393 int 394 ti_edma3_enable_transfer_event(unsigned int ch) 395 { 396 if (ch >= TI_EDMA3_NUM_DMA_CHS) 397 return (EINVAL); 398 399 /* Clear SECR(H) & EMCR(H) to clean any previous NULL request 400 * and set corresponding bit in EESR to enable DMA event */ 401 if(ch < 32) { 402 ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECR(0), (1 << ch)); 403 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, (1 << ch)); 404 ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESR(0), (1 << ch)); 405 } else { 406 ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECRH(0), 1 << (ch - 32)); 407 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 1 << (ch - 32)); 408 ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESRH(0), 1 << (ch - 32)); 409 } 410 411 return 0; 412 } 413 414 void 415 ti_edma3_param_write(unsigned int ch, struct ti_edma3cc_param_set *prs) 416 { 417 bus_write_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch), 418 (uint32_t *) prs, 8); 419 } 420 421 void 422 ti_edma3_param_read(unsigned int ch, struct ti_edma3cc_param_set *prs) 423 { 424 bus_read_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch), 425 (uint32_t *) prs, 8); 426 } 427