1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 5 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of authors nor the names of its contributors may be 17 * used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/endian.h> 39 #include <sys/mbuf.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/socket.h> 45 #include <sys/sysctl.h> 46 47 #include <sys/sockio.h> 48 #include <sys/bus.h> 49 #include <machine/bus.h> 50 #include <sys/rman.h> 51 #include <machine/resource.h> 52 53 #include <dev/ofw/ofw_bus.h> 54 #include <dev/ofw/ofw_bus_subr.h> 55 56 #include <arm/ti/ti_scm.h> 57 #include <arm/ti/ti_sysc.h> 58 59 #include <arm/ti/ti_edma3.h> 60 61 #define TI_EDMA3_NUM_TCS 3 62 #define TI_EDMA3_NUM_IRQS 3 63 #define TI_EDMA3_NUM_DMA_CHS 64 64 #define TI_EDMA3_NUM_QDMA_CHS 8 65 66 #define TI_EDMA3CC_PID 0x000 67 #define TI_EDMA3CC_DCHMAP(p) (0x100 + ((p)*4)) 68 #define TI_EDMA3CC_DMAQNUM(n) (0x240 + ((n)*4)) 69 #define TI_EDMA3CC_QDMAQNUM 0x260 70 #define TI_EDMA3CC_EMCR 0x308 71 #define TI_EDMA3CC_EMCRH 0x30C 72 #define TI_EDMA3CC_QEMCR 0x314 73 #define TI_EDMA3CC_CCERR 0x318 74 #define TI_EDMA3CC_CCERRCLR 0x31C 75 #define TI_EDMA3CC_DRAE(p) (0x340 + ((p)*8)) 76 #define TI_EDMA3CC_DRAEH(p) (0x344 + ((p)*8)) 77 #define TI_EDMA3CC_QRAE(p) (0x380 + ((p)*4)) 78 #define TI_EDMA3CC_S_ESR(p) (0x2010 + ((p)*0x200)) 79 #define TI_EDMA3CC_S_ESRH(p) (0x2014 + ((p)*0x200)) 80 #define TI_EDMA3CC_S_SECR(p) (0x2040 + ((p)*0x200)) 81 #define TI_EDMA3CC_S_SECRH(p) (0x2044 + ((p)*0x200)) 82 #define TI_EDMA3CC_S_EESR(p) (0x2030 + ((p)*0x200)) 83 #define TI_EDMA3CC_S_EESRH(p) (0x2034 + ((p)*0x200)) 84 #define TI_EDMA3CC_S_IESR(p) (0x2060 + ((p)*0x200)) 85 #define TI_EDMA3CC_S_IESRH(p) (0x2064 + ((p)*0x200)) 86 #define TI_EDMA3CC_S_IPR(p) (0x2068 + ((p)*0x200)) 87 #define TI_EDMA3CC_S_IPRH(p) (0x206C + ((p)*0x200)) 88 #define TI_EDMA3CC_S_QEESR(p) (0x208C + ((p)*0x200)) 89 90 #define TI_EDMA3CC_PARAM_OFFSET 0x4000 91 #define TI_EDMA3CC_OPT(p) (TI_EDMA3CC_PARAM_OFFSET + 0x0 + ((p)*0x20)) 92 93 #define TI_EDMA3CC_DMAQNUM_SET(c,q) ((0x7 & (q)) << (((c) % 8) * 4)) 94 #define TI_EDMA3CC_DMAQNUM_CLR(c) (~(0x7 << (((c) % 8) * 4))) 95 #define TI_EDMA3CC_QDMAQNUM_SET(c,q) ((0x7 & (q)) << ((c) * 4)) 96 #define TI_EDMA3CC_QDMAQNUM_CLR(c) (~(0x7 << ((c) * 4))) 97 98 #define TI_EDMA3CC_OPT_TCC_CLR (~(0x3F000)) 99 #define TI_EDMA3CC_OPT_TCC_SET(p) (((0x3F000 >> 12) & (p)) << 12) 100 101 struct ti_edma3_softc { 102 device_t sc_dev; 103 /* 104 * We use one-element array in case if we need to add 105 * mem resources for transfer control windows 106 */ 107 struct resource * mem_res[1]; 108 struct resource * irq_res[TI_EDMA3_NUM_IRQS]; 109 void *ih_cookie[TI_EDMA3_NUM_IRQS]; 110 }; 111 112 static struct ti_edma3_softc *ti_edma3_sc = NULL; 113 114 static struct resource_spec ti_edma3_mem_spec[] = { 115 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 116 { -1, 0, 0 } 117 }; 118 static struct resource_spec ti_edma3_irq_spec[] = { 119 { SYS_RES_IRQ, 0, RF_ACTIVE }, 120 { SYS_RES_IRQ, 1, RF_ACTIVE }, 121 { SYS_RES_IRQ, 2, RF_ACTIVE }, 122 { -1, 0, 0 } 123 }; 124 125 /* Read/Write macros */ 126 #define ti_edma3_cc_rd_4(reg) bus_read_4(ti_edma3_sc->mem_res[0], reg) 127 #define ti_edma3_cc_wr_4(reg, val) bus_write_4(ti_edma3_sc->mem_res[0], reg, val) 128 129 static void ti_edma3_intr_comp(void *arg); 130 static void ti_edma3_intr_mperr(void *arg); 131 static void ti_edma3_intr_err(void *arg); 132 133 static struct { 134 driver_intr_t *handler; 135 char * description; 136 } ti_edma3_intrs[TI_EDMA3_NUM_IRQS] = { 137 { ti_edma3_intr_comp, "EDMA Completion Interrupt" }, 138 { ti_edma3_intr_mperr, "EDMA Memory Protection Error Interrupt" }, 139 { ti_edma3_intr_err, "EDMA Error Interrupt" }, 140 }; 141 142 static int 143 ti_edma3_probe(device_t dev) 144 { 145 146 if (!ofw_bus_status_okay(dev)) 147 return (ENXIO); 148 149 if (!ofw_bus_is_compatible(dev, "ti,edma3")) 150 return (ENXIO); 151 152 device_set_desc(dev, "TI EDMA Controller"); 153 return (0); 154 } 155 156 static int 157 ti_edma3_attach(device_t dev) 158 { 159 struct ti_edma3_softc *sc = device_get_softc(dev); 160 uint32_t reg; 161 int err; 162 int i; 163 164 if (ti_edma3_sc) 165 return (ENXIO); 166 167 ti_edma3_sc = sc; 168 sc->sc_dev = dev; 169 170 /* Request the memory resources */ 171 err = bus_alloc_resources(dev, ti_edma3_mem_spec, sc->mem_res); 172 if (err) { 173 device_printf(dev, "Error: could not allocate mem resources\n"); 174 return (ENXIO); 175 } 176 177 /* Request the IRQ resources */ 178 err = bus_alloc_resources(dev, ti_edma3_irq_spec, sc->irq_res); 179 if (err) { 180 device_printf(dev, "Error: could not allocate irq resources\n"); 181 return (ENXIO); 182 } 183 184 /* FIXME: Require DTS from Linux kernel 5.7 */ 185 /* FIXME: OK to enable clkctrl here? */ 186 /* Enable Channel Controller */ 187 ti_sysc_clock_enable(device_get_parent(dev)); 188 189 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_PID); 190 191 device_printf(dev, "EDMA revision %08x\n", reg); 192 193 194 /* Attach interrupt handlers */ 195 for (i = 0; i < TI_EDMA3_NUM_IRQS; ++i) { 196 err = bus_setup_intr(dev, sc->irq_res[i], INTR_TYPE_MISC | 197 INTR_MPSAFE, NULL, *ti_edma3_intrs[i].handler, 198 sc, &sc->ih_cookie[i]); 199 if (err) { 200 device_printf(dev, "could not setup %s\n", 201 ti_edma3_intrs[i].description); 202 return (err); 203 } 204 } 205 206 return (0); 207 } 208 209 static device_method_t ti_edma3_methods[] = { 210 DEVMETHOD(device_probe, ti_edma3_probe), 211 DEVMETHOD(device_attach, ti_edma3_attach), 212 {0, 0}, 213 }; 214 215 static driver_t ti_edma3_driver = { 216 "ti_edma3", 217 ti_edma3_methods, 218 sizeof(struct ti_edma3_softc), 219 }; 220 static devclass_t ti_edma3_devclass; 221 222 DRIVER_MODULE(ti_edma3, simplebus, ti_edma3_driver, ti_edma3_devclass, 0, 0); 223 MODULE_DEPEND(ti_edma3, ti_sysc, 1, 1, 1); 224 225 static void 226 ti_edma3_intr_comp(void *arg) 227 { 228 printf("%s: unimplemented\n", __func__); 229 } 230 231 static void 232 ti_edma3_intr_mperr(void *arg) 233 { 234 printf("%s: unimplemented\n", __func__); 235 } 236 237 static void 238 ti_edma3_intr_err(void *arg) 239 { 240 printf("%s: unimplemented\n", __func__); 241 } 242 243 void 244 ti_edma3_init(unsigned int eqn) 245 { 246 uint32_t reg; 247 int i; 248 249 /* Clear Event Missed Regs */ 250 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, 0xFFFFFFFF); 251 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 0xFFFFFFFF); 252 ti_edma3_cc_wr_4(TI_EDMA3CC_QEMCR, 0xFFFFFFFF); 253 254 /* Clear Error Reg */ 255 ti_edma3_cc_wr_4(TI_EDMA3CC_CCERRCLR, 0xFFFFFFFF); 256 257 /* Enable DMA channels 0-63 */ 258 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), 0xFFFFFFFF); 259 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), 0xFFFFFFFF); 260 261 for (i = 0; i < 64; i++) { 262 ti_edma3_cc_wr_4(TI_EDMA3CC_DCHMAP(i), i<<5); 263 } 264 265 /* Initialize the DMA Queue Number Registers */ 266 for (i = 0; i < TI_EDMA3_NUM_DMA_CHS; i++) { 267 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(i>>3)); 268 reg &= TI_EDMA3CC_DMAQNUM_CLR(i); 269 reg |= TI_EDMA3CC_DMAQNUM_SET(i, eqn); 270 ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(i>>3), reg); 271 } 272 273 /* Enable the QDMA Region access for all channels */ 274 ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), (1 << TI_EDMA3_NUM_QDMA_CHS) - 1); 275 276 /*Initialize QDMA Queue Number Registers */ 277 for (i = 0; i < TI_EDMA3_NUM_QDMA_CHS; i++) { 278 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM); 279 reg &= TI_EDMA3CC_QDMAQNUM_CLR(i); 280 reg |= TI_EDMA3CC_QDMAQNUM_SET(i, eqn); 281 ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg); 282 } 283 } 284 285 #ifdef notyet 286 int 287 ti_edma3_enable_event_intr(unsigned int ch) 288 { 289 uint32_t reg; 290 291 if (ch >= TI_EDMA3_NUM_DMA_CHS) 292 return (EINVAL); 293 294 if (ch < 32) { 295 ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESR(0), 1 << ch); 296 } else { 297 ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESRH(0), 1 << (ch - 32)); 298 } 299 return 0; 300 } 301 #endif 302 303 int 304 ti_edma3_request_dma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn) 305 { 306 uint32_t reg; 307 308 if (ch >= TI_EDMA3_NUM_DMA_CHS) 309 return (EINVAL); 310 311 /* Enable the DMA channel in the DRAE/DRAEH registers */ 312 if (ch < 32) { 313 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAE(0)); 314 reg |= (0x01 << ch); 315 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), reg); 316 } else { 317 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAEH(0)); 318 reg |= (0x01 << (ch - 32)); 319 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), reg); 320 } 321 322 /* Associate DMA Channel to Event Queue */ 323 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(ch >> 3)); 324 reg &= TI_EDMA3CC_DMAQNUM_CLR(ch); 325 reg |= TI_EDMA3CC_DMAQNUM_SET((ch), eqn); 326 ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(ch >> 3), reg); 327 328 /* Set TCC in corresponding PaRAM Entry */ 329 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch)); 330 reg &= TI_EDMA3CC_OPT_TCC_CLR; 331 reg |= TI_EDMA3CC_OPT_TCC_SET(ch); 332 ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg); 333 334 return 0; 335 } 336 337 int 338 ti_edma3_request_qdma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn) 339 { 340 uint32_t reg; 341 342 if (ch >= TI_EDMA3_NUM_DMA_CHS) 343 return (EINVAL); 344 345 /* Enable the QDMA channel in the QRAE registers */ 346 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QRAE(0)); 347 reg |= (0x01 << ch); 348 ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), reg); 349 350 /* Associate QDMA Channel to Event Queue */ 351 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM); 352 reg |= TI_EDMA3CC_QDMAQNUM_SET(ch, eqn); 353 ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg); 354 355 /* Set TCC in corresponding PaRAM Entry */ 356 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch)); 357 reg &= TI_EDMA3CC_OPT_TCC_CLR; 358 reg |= TI_EDMA3CC_OPT_TCC_SET(ch); 359 ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg); 360 361 return 0; 362 } 363 364 int 365 ti_edma3_enable_transfer_manual(unsigned int ch) 366 { 367 if (ch >= TI_EDMA3_NUM_DMA_CHS) 368 return (EINVAL); 369 370 /* set corresponding bit in ESR/ESRH to set a event */ 371 if (ch < 32) { 372 ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESR(0), 1 << ch); 373 } else { 374 ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESRH(0), 1 << (ch - 32)); 375 } 376 377 return 0; 378 } 379 380 int 381 ti_edma3_enable_transfer_qdma(unsigned int ch) 382 { 383 if (ch >= TI_EDMA3_NUM_QDMA_CHS) 384 return (EINVAL); 385 386 /* set corresponding bit in QEESR to enable QDMA event */ 387 ti_edma3_cc_wr_4(TI_EDMA3CC_S_QEESR(0), (1 << ch)); 388 389 return 0; 390 } 391 392 int 393 ti_edma3_enable_transfer_event(unsigned int ch) 394 { 395 if (ch >= TI_EDMA3_NUM_DMA_CHS) 396 return (EINVAL); 397 398 /* Clear SECR(H) & EMCR(H) to clean any previous NULL request 399 * and set corresponding bit in EESR to enable DMA event */ 400 if(ch < 32) { 401 ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECR(0), (1 << ch)); 402 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, (1 << ch)); 403 ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESR(0), (1 << ch)); 404 } else { 405 ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECRH(0), 1 << (ch - 32)); 406 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 1 << (ch - 32)); 407 ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESRH(0), 1 << (ch - 32)); 408 } 409 410 return 0; 411 } 412 413 void 414 ti_edma3_param_write(unsigned int ch, struct ti_edma3cc_param_set *prs) 415 { 416 bus_write_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch), 417 (uint32_t *) prs, 8); 418 } 419 420 void 421 ti_edma3_param_read(unsigned int ch, struct ti_edma3cc_param_set *prs) 422 { 423 bus_read_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch), 424 (uint32_t *) prs, 8); 425 } 426