1 /*- 2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 3 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of authors nor the names of its contributors may be 15 * used to endorse or promote products derived from this software without 16 * specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/endian.h> 37 #include <sys/mbuf.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/socket.h> 43 #include <sys/sysctl.h> 44 45 #include <sys/sockio.h> 46 #include <sys/bus.h> 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <machine/resource.h> 50 51 #include <dev/fdt/fdt_common.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include <arm/ti/ti_scm.h> 56 #include <arm/ti/ti_prcm.h> 57 58 #include <arm/ti/ti_edma3.h> 59 60 #define TI_EDMA3_NUM_TCS 3 61 #define TI_EDMA3_NUM_IRQS 3 62 #define TI_EDMA3_NUM_DMA_CHS 64 63 #define TI_EDMA3_NUM_QDMA_CHS 8 64 65 #define TI_EDMA3CC_PID 0x000 66 #define TI_EDMA3CC_DCHMAP(p) (0x100 + ((p)*4)) 67 #define TI_EDMA3CC_DMAQNUM(n) (0x240 + ((n)*4)) 68 #define TI_EDMA3CC_QDMAQNUM 0x260 69 #define TI_EDMA3CC_EMCR 0x308 70 #define TI_EDMA3CC_EMCRH 0x30C 71 #define TI_EDMA3CC_QEMCR 0x314 72 #define TI_EDMA3CC_CCERR 0x318 73 #define TI_EDMA3CC_CCERRCLR 0x31C 74 #define TI_EDMA3CC_DRAE(p) (0x340 + ((p)*8)) 75 #define TI_EDMA3CC_DRAEH(p) (0x344 + ((p)*8)) 76 #define TI_EDMA3CC_QRAE(p) (0x380 + ((p)*4)) 77 #define TI_EDMA3CC_S_ESR(p) (0x2010 + ((p)*0x200)) 78 #define TI_EDMA3CC_S_ESRH(p) (0x2014 + ((p)*0x200)) 79 #define TI_EDMA3CC_S_SECR(p) (0x2040 + ((p)*0x200)) 80 #define TI_EDMA3CC_S_SECRH(p) (0x2044 + ((p)*0x200)) 81 #define TI_EDMA3CC_S_EESR(p) (0x2030 + ((p)*0x200)) 82 #define TI_EDMA3CC_S_EESRH(p) (0x2034 + ((p)*0x200)) 83 #define TI_EDMA3CC_S_IESR(p) (0x2060 + ((p)*0x200)) 84 #define TI_EDMA3CC_S_IESRH(p) (0x2064 + ((p)*0x200)) 85 #define TI_EDMA3CC_S_IPR(p) (0x2068 + ((p)*0x200)) 86 #define TI_EDMA3CC_S_IPRH(p) (0x206C + ((p)*0x200)) 87 #define TI_EDMA3CC_S_QEESR(p) (0x208C + ((p)*0x200)) 88 89 #define TI_EDMA3CC_PARAM_OFFSET 0x4000 90 #define TI_EDMA3CC_OPT(p) (TI_EDMA3CC_PARAM_OFFSET + 0x0 + ((p)*0x20)) 91 92 #define TI_EDMA3CC_DMAQNUM_SET(c,q) ((0x7 & (q)) << (((c) % 8) * 4)) 93 #define TI_EDMA3CC_DMAQNUM_CLR(c) (~(0x7 << (((c) % 8) * 4))) 94 #define TI_EDMA3CC_QDMAQNUM_SET(c,q) ((0x7 & (q)) << ((c) * 4)) 95 #define TI_EDMA3CC_QDMAQNUM_CLR(c) (~(0x7 << ((c) * 4))) 96 97 #define TI_EDMA3CC_OPT_TCC_CLR (~(0x3F000)) 98 #define TI_EDMA3CC_OPT_TCC_SET(p) (((0x3F000 >> 12) & (p)) << 12) 99 100 struct ti_edma3_softc { 101 device_t sc_dev; 102 /* 103 * We use one-element array in case if we need to add 104 * mem resources for transfer control windows 105 */ 106 struct resource * mem_res[1]; 107 struct resource * irq_res[TI_EDMA3_NUM_IRQS]; 108 void *ih_cookie[TI_EDMA3_NUM_IRQS]; 109 }; 110 111 static struct ti_edma3_softc *ti_edma3_sc = NULL; 112 113 static struct resource_spec ti_edma3_mem_spec[] = { 114 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 115 { -1, 0, 0 } 116 }; 117 static struct resource_spec ti_edma3_irq_spec[] = { 118 { SYS_RES_IRQ, 0, RF_ACTIVE }, 119 { SYS_RES_IRQ, 1, RF_ACTIVE }, 120 { SYS_RES_IRQ, 2, RF_ACTIVE }, 121 { -1, 0, 0 } 122 }; 123 124 /* Read/Write macros */ 125 #define ti_edma3_cc_rd_4(reg) bus_read_4(ti_edma3_sc->mem_res[0], reg) 126 #define ti_edma3_cc_wr_4(reg, val) bus_write_4(ti_edma3_sc->mem_res[0], reg, val) 127 128 static void ti_edma3_intr_comp(void *arg); 129 static void ti_edma3_intr_mperr(void *arg); 130 static void ti_edma3_intr_err(void *arg); 131 132 static struct { 133 driver_intr_t *handler; 134 char * description; 135 } ti_edma3_intrs[TI_EDMA3_NUM_IRQS] = { 136 { ti_edma3_intr_comp, "EDMA Completion Interrupt" }, 137 { ti_edma3_intr_mperr, "EDMA Memory Protection Error Interrupt" }, 138 { ti_edma3_intr_err, "EDMA Error Interrupt" }, 139 }; 140 141 static int 142 ti_edma3_probe(device_t dev) 143 { 144 145 if (!ofw_bus_status_okay(dev)) 146 return (ENXIO); 147 148 if (!ofw_bus_is_compatible(dev, "ti,edma3")) 149 return (ENXIO); 150 151 device_set_desc(dev, "TI EDMA Controller"); 152 return (0); 153 } 154 155 static int 156 ti_edma3_attach(device_t dev) 157 { 158 struct ti_edma3_softc *sc = device_get_softc(dev); 159 uint32_t reg; 160 int err; 161 int i; 162 163 if (ti_edma3_sc) 164 return (ENXIO); 165 166 ti_edma3_sc = sc; 167 sc->sc_dev = dev; 168 169 /* Request the memory resources */ 170 err = bus_alloc_resources(dev, ti_edma3_mem_spec, sc->mem_res); 171 if (err) { 172 device_printf(dev, "Error: could not allocate mem resources\n"); 173 return (ENXIO); 174 } 175 176 /* Request the IRQ resources */ 177 err = bus_alloc_resources(dev, ti_edma3_irq_spec, sc->irq_res); 178 if (err) { 179 device_printf(dev, "Error: could not allocate irq resources\n"); 180 return (ENXIO); 181 } 182 183 /* Enable Channel Controller */ 184 ti_prcm_clk_enable(EDMA_TPCC_CLK); 185 186 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_PID); 187 188 device_printf(dev, "EDMA revision %08x\n", reg); 189 190 191 /* Attach interrupt handlers */ 192 for (i = 0; i < TI_EDMA3_NUM_IRQS; ++i) { 193 err = bus_setup_intr(dev, sc->irq_res[i], INTR_TYPE_MISC | 194 INTR_MPSAFE, NULL, *ti_edma3_intrs[i].handler, 195 sc, &sc->ih_cookie[i]); 196 if (err) { 197 device_printf(dev, "could not setup %s\n", 198 ti_edma3_intrs[i].description); 199 return (err); 200 } 201 } 202 203 return (0); 204 } 205 206 static device_method_t ti_edma3_methods[] = { 207 DEVMETHOD(device_probe, ti_edma3_probe), 208 DEVMETHOD(device_attach, ti_edma3_attach), 209 {0, 0}, 210 }; 211 212 static driver_t ti_edma3_driver = { 213 "ti_edma3", 214 ti_edma3_methods, 215 sizeof(struct ti_edma3_softc), 216 }; 217 static devclass_t ti_edma3_devclass; 218 219 DRIVER_MODULE(ti_edma3, simplebus, ti_edma3_driver, ti_edma3_devclass, 0, 0); 220 MODULE_DEPEND(ti_edma3, ti_prcm, 1, 1, 1); 221 222 static void 223 ti_edma3_intr_comp(void *arg) 224 { 225 printf("%s: unimplemented\n", __func__); 226 } 227 228 static void 229 ti_edma3_intr_mperr(void *arg) 230 { 231 printf("%s: unimplemented\n", __func__); 232 } 233 234 static void 235 ti_edma3_intr_err(void *arg) 236 { 237 printf("%s: unimplemented\n", __func__); 238 } 239 240 void 241 ti_edma3_init(unsigned int eqn) 242 { 243 uint32_t reg; 244 int i; 245 246 /* on AM335x Event queue 0 is always mapped to Transfer Controller 0, 247 * event queue 1 to TC2, etc. So we are asking PRCM to power on specific 248 * TC based on what event queue we need to initialize */ 249 ti_prcm_clk_enable(EDMA_TPTC0_CLK + eqn); 250 251 /* Clear Event Missed Regs */ 252 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, 0xFFFFFFFF); 253 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 0xFFFFFFFF); 254 ti_edma3_cc_wr_4(TI_EDMA3CC_QEMCR, 0xFFFFFFFF); 255 256 /* Clear Error Reg */ 257 ti_edma3_cc_wr_4(TI_EDMA3CC_CCERRCLR, 0xFFFFFFFF); 258 259 /* Enable DMA channels 0-63 */ 260 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), 0xFFFFFFFF); 261 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), 0xFFFFFFFF); 262 263 for (i = 0; i < 64; i++) { 264 ti_edma3_cc_wr_4(TI_EDMA3CC_DCHMAP(i), i<<5); 265 } 266 267 /* Initialize the DMA Queue Number Registers */ 268 for (i = 0; i < TI_EDMA3_NUM_DMA_CHS; i++) { 269 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(i>>3)); 270 reg &= TI_EDMA3CC_DMAQNUM_CLR(i); 271 reg |= TI_EDMA3CC_DMAQNUM_SET(i, eqn); 272 ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(i>>3), reg); 273 } 274 275 /* Enable the QDMA Region access for all channels */ 276 ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), (1 << TI_EDMA3_NUM_QDMA_CHS) - 1); 277 278 /*Initialize QDMA Queue Number Registers */ 279 for (i = 0; i < TI_EDMA3_NUM_QDMA_CHS; i++) { 280 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM); 281 reg &= TI_EDMA3CC_QDMAQNUM_CLR(i); 282 reg |= TI_EDMA3CC_QDMAQNUM_SET(i, eqn); 283 ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg); 284 } 285 } 286 287 #ifdef notyet 288 int 289 ti_edma3_enable_event_intr(unsigned int ch) 290 { 291 uint32_t reg; 292 293 if (ch >= TI_EDMA3_NUM_DMA_CHS) 294 return (EINVAL); 295 296 if (ch < 32) { 297 ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESR(0), 1 << ch); 298 } else { 299 ti_edma3_cc_wr_4(TI_EDMA3CC_S_IESRH(0), 1 << (ch - 32)); 300 } 301 return 0; 302 } 303 #endif 304 305 int 306 ti_edma3_request_dma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn) 307 { 308 uint32_t reg; 309 310 if (ch >= TI_EDMA3_NUM_DMA_CHS) 311 return (EINVAL); 312 313 /* Enable the DMA channel in the DRAE/DRAEH registers */ 314 if (ch < 32) { 315 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAE(0)); 316 reg |= (0x01 << ch); 317 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), reg); 318 } else { 319 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAEH(0)); 320 reg |= (0x01 << (ch - 32)); 321 ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), reg); 322 } 323 324 /* Associate DMA Channel to Event Queue */ 325 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(ch >> 3)); 326 reg &= TI_EDMA3CC_DMAQNUM_CLR(ch); 327 reg |= TI_EDMA3CC_DMAQNUM_SET((ch), eqn); 328 ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(ch >> 3), reg); 329 330 /* Set TCC in corresponding PaRAM Entry */ 331 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch)); 332 reg &= TI_EDMA3CC_OPT_TCC_CLR; 333 reg |= TI_EDMA3CC_OPT_TCC_SET(ch); 334 ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg); 335 336 return 0; 337 } 338 339 int 340 ti_edma3_request_qdma_ch(unsigned int ch, unsigned int tccn, unsigned int eqn) 341 { 342 uint32_t reg; 343 344 if (ch >= TI_EDMA3_NUM_DMA_CHS) 345 return (EINVAL); 346 347 /* Enable the QDMA channel in the QRAE registers */ 348 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QRAE(0)); 349 reg |= (0x01 << ch); 350 ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), reg); 351 352 /* Associate QDMA Channel to Event Queue */ 353 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM); 354 reg |= TI_EDMA3CC_QDMAQNUM_SET(ch, eqn); 355 ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg); 356 357 /* Set TCC in corresponding PaRAM Entry */ 358 reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch)); 359 reg &= TI_EDMA3CC_OPT_TCC_CLR; 360 reg |= TI_EDMA3CC_OPT_TCC_SET(ch); 361 ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg); 362 363 return 0; 364 } 365 366 int 367 ti_edma3_enable_transfer_manual(unsigned int ch) 368 { 369 if (ch >= TI_EDMA3_NUM_DMA_CHS) 370 return (EINVAL); 371 372 /* set corresponding bit in ESR/ESRH to set a event */ 373 if (ch < 32) { 374 ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESR(0), 1 << ch); 375 } else { 376 ti_edma3_cc_wr_4(TI_EDMA3CC_S_ESRH(0), 1 << (ch - 32)); 377 } 378 379 return 0; 380 } 381 382 int 383 ti_edma3_enable_transfer_qdma(unsigned int ch) 384 { 385 if (ch >= TI_EDMA3_NUM_QDMA_CHS) 386 return (EINVAL); 387 388 /* set corresponding bit in QEESR to enable QDMA event */ 389 ti_edma3_cc_wr_4(TI_EDMA3CC_S_QEESR(0), (1 << ch)); 390 391 return 0; 392 } 393 394 int 395 ti_edma3_enable_transfer_event(unsigned int ch) 396 { 397 if (ch >= TI_EDMA3_NUM_DMA_CHS) 398 return (EINVAL); 399 400 /* Clear SECR(H) & EMCR(H) to clean any previous NULL request 401 * and set corresponding bit in EESR to enable DMA event */ 402 if(ch < 32) { 403 ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECR(0), (1 << ch)); 404 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCR, (1 << ch)); 405 ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESR(0), (1 << ch)); 406 } else { 407 ti_edma3_cc_wr_4(TI_EDMA3CC_S_SECRH(0), 1 << (ch - 32)); 408 ti_edma3_cc_wr_4(TI_EDMA3CC_EMCRH, 1 << (ch - 32)); 409 ti_edma3_cc_wr_4(TI_EDMA3CC_S_EESRH(0), 1 << (ch - 32)); 410 } 411 412 return 0; 413 } 414 415 void 416 ti_edma3_param_write(unsigned int ch, struct ti_edma3cc_param_set *prs) 417 { 418 bus_write_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch), 419 (uint32_t *) prs, 8); 420 } 421 422 void 423 ti_edma3_param_read(unsigned int ch, struct ti_edma3cc_param_set *prs) 424 { 425 bus_read_region_4(ti_edma3_sc->mem_res[0], TI_EDMA3CC_OPT(ch), 426 (uint32_t *) prs, 8); 427 } 428