1 /*- 2 * Copyright 2014 Luiz Otavio O Souza <loos@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 34 #include <sys/kernel.h> 35 #include <sys/limits.h> 36 #include <sys/lock.h> 37 #include <sys/module.h> 38 #include <sys/mutex.h> 39 #include <sys/resource.h> 40 #include <sys/rman.h> 41 #include <sys/sysctl.h> 42 43 #include <machine/bus.h> 44 45 #include <dev/ofw/openfirm.h> 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include <arm/ti/ti_prcm.h> 50 #include <arm/ti/ti_adcreg.h> 51 #include <arm/ti/ti_adcvar.h> 52 53 /* Define our 7 steps, one for each input channel. */ 54 static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = { 55 { .stepconfig = ADC_STEPCFG1, .stepdelay = ADC_STEPDLY1 }, 56 { .stepconfig = ADC_STEPCFG2, .stepdelay = ADC_STEPDLY2 }, 57 { .stepconfig = ADC_STEPCFG3, .stepdelay = ADC_STEPDLY3 }, 58 { .stepconfig = ADC_STEPCFG4, .stepdelay = ADC_STEPDLY4 }, 59 { .stepconfig = ADC_STEPCFG5, .stepdelay = ADC_STEPDLY5 }, 60 { .stepconfig = ADC_STEPCFG6, .stepdelay = ADC_STEPDLY6 }, 61 { .stepconfig = ADC_STEPCFG7, .stepdelay = ADC_STEPDLY7 }, 62 }; 63 64 static int ti_adc_samples[5] = { 0, 2, 4, 8, 16 }; 65 66 static void 67 ti_adc_enable(struct ti_adc_softc *sc) 68 { 69 70 TI_ADC_LOCK_ASSERT(sc); 71 72 if (sc->sc_last_state == 1) 73 return; 74 75 /* Enable the FIFO0 threshold and the end of sequence interrupt. */ 76 ADC_WRITE4(sc, ADC_IRQENABLE_SET, 77 ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ); 78 79 /* Enable the ADC. Run thru enabled steps, start the conversions. */ 80 ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) | ADC_CTRL_ENABLE); 81 82 sc->sc_last_state = 1; 83 } 84 85 static void 86 ti_adc_disable(struct ti_adc_softc *sc) 87 { 88 int count; 89 uint32_t data; 90 91 TI_ADC_LOCK_ASSERT(sc); 92 93 if (sc->sc_last_state == 0) 94 return; 95 96 /* Disable all the enabled steps. */ 97 ADC_WRITE4(sc, ADC_STEPENABLE, 0); 98 99 /* Disable the ADC. */ 100 ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE); 101 102 /* Disable the FIFO0 threshold and the end of sequence interrupt. */ 103 ADC_WRITE4(sc, ADC_IRQENABLE_CLR, 104 ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ); 105 106 /* ACK any pending interrupt. */ 107 ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS)); 108 109 /* Drain the FIFO data. */ 110 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 111 while (count > 0) { 112 data = ADC_READ4(sc, ADC_FIFO0DATA); 113 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 114 } 115 116 sc->sc_last_state = 0; 117 } 118 119 static int 120 ti_adc_setup(struct ti_adc_softc *sc) 121 { 122 int ain; 123 uint32_t enabled; 124 125 TI_ADC_LOCK_ASSERT(sc); 126 127 /* Check for enabled inputs. */ 128 enabled = 0; 129 for (ain = 0; ain < TI_ADC_NPINS; ain++) { 130 if (ti_adc_inputs[ain].enable) 131 enabled |= (1U << (ain + 1)); 132 } 133 134 /* Set the ADC global status. */ 135 if (enabled != 0) { 136 ti_adc_enable(sc); 137 /* Update the enabled steps. */ 138 if (enabled != ADC_READ4(sc, ADC_STEPENABLE)) 139 ADC_WRITE4(sc, ADC_STEPENABLE, enabled); 140 } else 141 ti_adc_disable(sc); 142 143 return (0); 144 } 145 146 static void 147 ti_adc_input_setup(struct ti_adc_softc *sc, int32_t ain) 148 { 149 struct ti_adc_input *input; 150 uint32_t reg, val; 151 152 TI_ADC_LOCK_ASSERT(sc); 153 154 input = &ti_adc_inputs[ain]; 155 reg = input->stepconfig; 156 val = ADC_READ4(sc, reg); 157 158 /* Set single ended operation. */ 159 val &= ~ADC_STEP_DIFF_CNTRL; 160 161 /* Set the negative voltage reference. */ 162 val &= ~ADC_STEP_RFM_MSK; 163 val |= ADC_STEP_RFM_VREFN << ADC_STEP_RFM_SHIFT; 164 165 /* Set the positive voltage reference. */ 166 val &= ~ADC_STEP_RFP_MSK; 167 val |= ADC_STEP_RFP_VREFP << ADC_STEP_RFP_SHIFT; 168 169 /* Set the samples average. */ 170 val &= ~ADC_STEP_AVG_MSK; 171 val |= input->samples << ADC_STEP_AVG_SHIFT; 172 173 /* Select the desired input. */ 174 val &= ~ADC_STEP_INP_MSK; 175 val |= ain << ADC_STEP_INP_SHIFT; 176 177 /* Set the ADC to one-shot mode. */ 178 val &= ~ADC_STEP_MODE_MSK; 179 180 ADC_WRITE4(sc, reg, val); 181 } 182 183 static void 184 ti_adc_reset(struct ti_adc_softc *sc) 185 { 186 int ain; 187 188 TI_ADC_LOCK_ASSERT(sc); 189 190 /* Disable all the inputs. */ 191 for (ain = 0; ain < TI_ADC_NPINS; ain++) 192 ti_adc_inputs[ain].enable = 0; 193 } 194 195 static int 196 ti_adc_clockdiv_proc(SYSCTL_HANDLER_ARGS) 197 { 198 int error, reg; 199 struct ti_adc_softc *sc; 200 201 sc = (struct ti_adc_softc *)arg1; 202 203 TI_ADC_LOCK(sc); 204 reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1; 205 TI_ADC_UNLOCK(sc); 206 207 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 208 if (error != 0 || req->newptr == NULL) 209 return (error); 210 211 /* 212 * The actual written value is the prescaler setting - 1. 213 * Enforce a minimum value of 10 (i.e. 9) which limits the maximum 214 * ADC clock to ~2.4Mhz (CLK_M_OSC / 10). 215 */ 216 reg--; 217 if (reg < 9) 218 reg = 9; 219 if (reg > USHRT_MAX) 220 reg = USHRT_MAX; 221 222 TI_ADC_LOCK(sc); 223 /* Disable the ADC. */ 224 ti_adc_disable(sc); 225 /* Update the ADC prescaler setting. */ 226 ADC_WRITE4(sc, ADC_CLKDIV, reg); 227 /* Enable the ADC again. */ 228 ti_adc_setup(sc); 229 TI_ADC_UNLOCK(sc); 230 231 return (0); 232 } 233 234 static int 235 ti_adc_enable_proc(SYSCTL_HANDLER_ARGS) 236 { 237 int error; 238 int32_t enable; 239 struct ti_adc_softc *sc; 240 struct ti_adc_input *input; 241 242 input = (struct ti_adc_input *)arg1; 243 sc = input->sc; 244 245 enable = input->enable; 246 error = sysctl_handle_int(oidp, &enable, sizeof(enable), 247 req); 248 if (error != 0 || req->newptr == NULL) 249 return (error); 250 251 if (enable) 252 enable = 1; 253 254 TI_ADC_LOCK(sc); 255 /* Setup the ADC as needed. */ 256 if (input->enable != enable) { 257 input->enable = enable; 258 ti_adc_setup(sc); 259 if (input->enable == 0) 260 input->value = 0; 261 } 262 TI_ADC_UNLOCK(sc); 263 264 return (0); 265 } 266 267 static int 268 ti_adc_open_delay_proc(SYSCTL_HANDLER_ARGS) 269 { 270 int error, reg; 271 struct ti_adc_softc *sc; 272 struct ti_adc_input *input; 273 274 input = (struct ti_adc_input *)arg1; 275 sc = input->sc; 276 277 TI_ADC_LOCK(sc); 278 reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY; 279 TI_ADC_UNLOCK(sc); 280 281 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 282 if (error != 0 || req->newptr == NULL) 283 return (error); 284 285 if (reg < 0) 286 reg = 0; 287 288 TI_ADC_LOCK(sc); 289 ADC_WRITE4(sc, input->stepdelay, reg & ADC_STEP_OPEN_DELAY); 290 TI_ADC_UNLOCK(sc); 291 292 return (0); 293 } 294 295 static int 296 ti_adc_samples_avg_proc(SYSCTL_HANDLER_ARGS) 297 { 298 int error, samples, i; 299 struct ti_adc_softc *sc; 300 struct ti_adc_input *input; 301 302 input = (struct ti_adc_input *)arg1; 303 sc = input->sc; 304 305 if (input->samples > nitems(ti_adc_samples)) 306 input->samples = nitems(ti_adc_samples); 307 samples = ti_adc_samples[input->samples]; 308 309 error = sysctl_handle_int(oidp, &samples, 0, req); 310 if (error != 0 || req->newptr == NULL) 311 return (error); 312 313 TI_ADC_LOCK(sc); 314 if (samples != ti_adc_samples[input->samples]) { 315 input->samples = 0; 316 for (i = 0; i < nitems(ti_adc_samples); i++) 317 if (samples >= ti_adc_samples[i]) 318 input->samples = i; 319 ti_adc_input_setup(sc, input->input); 320 } 321 TI_ADC_UNLOCK(sc); 322 323 return (error); 324 } 325 326 static void 327 ti_adc_read_data(struct ti_adc_softc *sc) 328 { 329 int count, ain; 330 struct ti_adc_input *input; 331 uint32_t data; 332 333 TI_ADC_LOCK_ASSERT(sc); 334 335 /* Read the available data. */ 336 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 337 while (count > 0) { 338 data = ADC_READ4(sc, ADC_FIFO0DATA); 339 ain = (data & ADC_FIFO_STEP_ID_MSK) >> ADC_FIFO_STEP_ID_SHIFT; 340 input = &ti_adc_inputs[ain]; 341 if (input->enable == 0) 342 input->value = 0; 343 else 344 input->value = (int32_t)(data & ADC_FIFO_DATA_MSK); 345 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 346 } 347 } 348 349 static void 350 ti_adc_intr(void *arg) 351 { 352 struct ti_adc_softc *sc; 353 uint32_t status; 354 355 sc = (struct ti_adc_softc *)arg; 356 357 status = ADC_READ4(sc, ADC_IRQSTATUS); 358 if (status == 0) 359 return; 360 if (status & ~(ADC_IRQ_FIFO0_THRES | ADC_IRQ_END_OF_SEQ)) 361 device_printf(sc->sc_dev, "stray interrupt: %#x\n", status); 362 363 TI_ADC_LOCK(sc); 364 /* ACK the interrupt. */ 365 ADC_WRITE4(sc, ADC_IRQSTATUS, status); 366 367 /* Read the available data. */ 368 if (status & ADC_IRQ_FIFO0_THRES) 369 ti_adc_read_data(sc); 370 371 /* Start the next conversion ? */ 372 if (status & ADC_IRQ_END_OF_SEQ) 373 ti_adc_setup(sc); 374 TI_ADC_UNLOCK(sc); 375 } 376 377 static void 378 ti_adc_sysctl_init(struct ti_adc_softc *sc) 379 { 380 char pinbuf[3]; 381 struct sysctl_ctx_list *ctx; 382 struct sysctl_oid *tree_node, *inp_node, *inpN_node; 383 struct sysctl_oid_list *tree, *inp_tree, *inpN_tree; 384 int ain; 385 386 /* 387 * Add per-pin sysctl tree/handlers. 388 */ 389 ctx = device_get_sysctl_ctx(sc->sc_dev); 390 tree_node = device_get_sysctl_tree(sc->sc_dev); 391 tree = SYSCTL_CHILDREN(tree_node); 392 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clockdiv", 393 CTLFLAG_RW | CTLTYPE_UINT, sc, 0, 394 ti_adc_clockdiv_proc, "IU", "ADC clock prescaler"); 395 inp_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "ain", 396 CTLFLAG_RD, NULL, "ADC inputs"); 397 inp_tree = SYSCTL_CHILDREN(inp_node); 398 399 for (ain = 0; ain < TI_ADC_NPINS; ain++) { 400 401 snprintf(pinbuf, sizeof(pinbuf), "%d", ain); 402 inpN_node = SYSCTL_ADD_NODE(ctx, inp_tree, OID_AUTO, pinbuf, 403 CTLFLAG_RD, NULL, "ADC input"); 404 inpN_tree = SYSCTL_CHILDREN(inpN_node); 405 406 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "enable", 407 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0, 408 ti_adc_enable_proc, "IU", "Enable ADC input"); 409 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "open_delay", 410 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0, 411 ti_adc_open_delay_proc, "IU", "ADC open delay"); 412 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "samples_avg", 413 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0, 414 ti_adc_samples_avg_proc, "IU", "ADC samples average"); 415 SYSCTL_ADD_INT(ctx, inpN_tree, OID_AUTO, "input", 416 CTLFLAG_RD, &ti_adc_inputs[ain].value, 0, 417 "Converted raw value for the ADC input"); 418 } 419 } 420 421 static void 422 ti_adc_inputs_init(struct ti_adc_softc *sc) 423 { 424 int ain; 425 struct ti_adc_input *input; 426 427 TI_ADC_LOCK(sc); 428 for (ain = 0; ain < TI_ADC_NPINS; ain++) { 429 input = &ti_adc_inputs[ain]; 430 input->sc = sc; 431 input->input = ain; 432 input->value = 0; 433 input->enable = 0; 434 input->samples = 0; 435 ti_adc_input_setup(sc, ain); 436 } 437 TI_ADC_UNLOCK(sc); 438 } 439 440 static void 441 ti_adc_idlestep_init(struct ti_adc_softc *sc) 442 { 443 uint32_t val; 444 445 val = ADC_READ4(sc, ADC_IDLECONFIG); 446 447 /* Set single ended operation. */ 448 val &= ~ADC_STEP_DIFF_CNTRL; 449 450 /* Set the negative voltage reference. */ 451 val &= ~ADC_STEP_RFM_MSK; 452 val |= ADC_STEP_RFM_VREFN << ADC_STEP_RFM_SHIFT; 453 454 /* Set the positive voltage reference. */ 455 val &= ~ADC_STEP_RFP_MSK; 456 val |= ADC_STEP_RFP_VREFP << ADC_STEP_RFP_SHIFT; 457 458 /* Connect the input to VREFN. */ 459 val &= ~ADC_STEP_INP_MSK; 460 val |= ADC_STEP_IN_VREFN << ADC_STEP_INP_SHIFT; 461 462 ADC_WRITE4(sc, ADC_IDLECONFIG, val); 463 } 464 465 static int 466 ti_adc_probe(device_t dev) 467 { 468 469 if (!ofw_bus_is_compatible(dev, "ti,adc")) 470 return (ENXIO); 471 device_set_desc(dev, "TI ADC controller"); 472 473 return (BUS_PROBE_DEFAULT); 474 } 475 476 static int 477 ti_adc_attach(device_t dev) 478 { 479 int err, rid; 480 struct ti_adc_softc *sc; 481 uint32_t reg, rev; 482 483 sc = device_get_softc(dev); 484 sc->sc_dev = dev; 485 486 rid = 0; 487 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 488 RF_ACTIVE); 489 if (!sc->sc_mem_res) { 490 device_printf(dev, "cannot allocate memory window\n"); 491 return (ENXIO); 492 } 493 494 rid = 0; 495 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 496 RF_ACTIVE); 497 if (!sc->sc_irq_res) { 498 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 499 device_printf(dev, "cannot allocate interrupt\n"); 500 return (ENXIO); 501 } 502 503 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 504 NULL, ti_adc_intr, sc, &sc->sc_intrhand) != 0) { 505 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 506 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 507 device_printf(dev, "Unable to setup the irq handler.\n"); 508 return (ENXIO); 509 } 510 511 /* Activate the ADC_TSC module. */ 512 err = ti_prcm_clk_enable(TSC_ADC_CLK); 513 if (err) 514 return (err); 515 516 /* Check the ADC revision. */ 517 rev = ADC_READ4(sc, ADC_REVISION); 518 device_printf(dev, 519 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n", 520 (rev & ADC_REV_SCHEME_MSK) >> ADC_REV_SCHEME_SHIFT, 521 (rev & ADC_REV_FUNC_MSK) >> ADC_REV_FUNC_SHIFT, 522 (rev & ADC_REV_RTL_MSK) >> ADC_REV_RTL_SHIFT, 523 (rev & ADC_REV_MAJOR_MSK) >> ADC_REV_MAJOR_SHIFT, 524 rev & ADC_REV_MINOR_MSK, 525 (rev & ADC_REV_CUSTOM_MSK) >> ADC_REV_CUSTOM_SHIFT); 526 527 /* 528 * Disable the step write protect and make it store the step ID for 529 * the captured data on FIFO. 530 */ 531 reg = ADC_READ4(sc, ADC_CTRL); 532 ADC_WRITE4(sc, ADC_CTRL, reg | ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID); 533 534 /* 535 * Set the ADC prescaler to 2400 (yes, the actual value written here 536 * is 2400 - 1). 537 * This sets the ADC clock to ~10Khz (CLK_M_OSC / 2400). 538 */ 539 ADC_WRITE4(sc, ADC_CLKDIV, 2399); 540 541 TI_ADC_LOCK_INIT(sc); 542 543 ti_adc_idlestep_init(sc); 544 ti_adc_inputs_init(sc); 545 ti_adc_sysctl_init(sc); 546 547 return (0); 548 } 549 550 static int 551 ti_adc_detach(device_t dev) 552 { 553 struct ti_adc_softc *sc; 554 555 sc = device_get_softc(dev); 556 557 /* Turn off the ADC. */ 558 TI_ADC_LOCK(sc); 559 ti_adc_reset(sc); 560 ti_adc_setup(sc); 561 TI_ADC_UNLOCK(sc); 562 563 TI_ADC_LOCK_DESTROY(sc); 564 565 if (sc->sc_intrhand) 566 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 567 if (sc->sc_irq_res) 568 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 569 if (sc->sc_mem_res) 570 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 571 572 return (bus_generic_detach(dev)); 573 } 574 575 static device_method_t ti_adc_methods[] = { 576 DEVMETHOD(device_probe, ti_adc_probe), 577 DEVMETHOD(device_attach, ti_adc_attach), 578 DEVMETHOD(device_detach, ti_adc_detach), 579 580 DEVMETHOD_END 581 }; 582 583 static driver_t ti_adc_driver = { 584 "ti_adc", 585 ti_adc_methods, 586 sizeof(struct ti_adc_softc), 587 }; 588 589 static devclass_t ti_adc_devclass; 590 591 DRIVER_MODULE(ti_adc, simplebus, ti_adc_driver, ti_adc_devclass, 0, 0); 592 MODULE_VERSION(ti_adc, 1); 593 MODULE_DEPEND(ti_adc, simplebus, 1, 1, 1); 594