1 /*- 2 * Copyright 2014 Luiz Otavio O Souza <loos@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 34 #include <sys/conf.h> 35 #include <sys/kernel.h> 36 #include <sys/limits.h> 37 #include <sys/lock.h> 38 #include <sys/module.h> 39 #include <sys/mutex.h> 40 #include <sys/condvar.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 #include <sys/selinfo.h> 45 #include <sys/poll.h> 46 #include <sys/uio.h> 47 48 #include <machine/bus.h> 49 50 #include <dev/fdt/fdt_common.h> 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include <arm/ti/ti_prcm.h> 56 #include <arm/ti/ti_adcreg.h> 57 #include <arm/ti/ti_adcvar.h> 58 59 #undef DEBUG_TSC 60 61 #define DEFAULT_CHARGE_DELAY 0x400 62 #define STEPDLY_OPEN 0x98 63 64 #define ORDER_XP 0 65 #define ORDER_XN 1 66 #define ORDER_YP 2 67 #define ORDER_YN 3 68 69 /* Define our 8 steps, one for each input channel. */ 70 static struct ti_adc_input ti_adc_inputs[TI_ADC_NPINS] = { 71 { .stepconfig = ADC_STEPCFG(1), .stepdelay = ADC_STEPDLY(1) }, 72 { .stepconfig = ADC_STEPCFG(2), .stepdelay = ADC_STEPDLY(2) }, 73 { .stepconfig = ADC_STEPCFG(3), .stepdelay = ADC_STEPDLY(3) }, 74 { .stepconfig = ADC_STEPCFG(4), .stepdelay = ADC_STEPDLY(4) }, 75 { .stepconfig = ADC_STEPCFG(5), .stepdelay = ADC_STEPDLY(5) }, 76 { .stepconfig = ADC_STEPCFG(6), .stepdelay = ADC_STEPDLY(6) }, 77 { .stepconfig = ADC_STEPCFG(7), .stepdelay = ADC_STEPDLY(7) }, 78 { .stepconfig = ADC_STEPCFG(8), .stepdelay = ADC_STEPDLY(8) }, 79 }; 80 81 static int ti_adc_samples[5] = { 0, 2, 4, 8, 16 }; 82 83 static void 84 ti_adc_enable(struct ti_adc_softc *sc) 85 { 86 uint32_t reg; 87 88 TI_ADC_LOCK_ASSERT(sc); 89 90 if (sc->sc_last_state == 1) 91 return; 92 93 /* Enable the FIFO0 threshold and the end of sequence interrupt. */ 94 ADC_WRITE4(sc, ADC_IRQENABLE_SET, 95 ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ); 96 97 reg = ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID; 98 if (sc->sc_tsc_wires > 0) { 99 reg |= ADC_CTRL_TSC_ENABLE; 100 switch (sc->sc_tsc_wires) { 101 case 4: 102 reg |= ADC_CTRL_TSC_4WIRE; 103 break; 104 case 5: 105 reg |= ADC_CTRL_TSC_5WIRE; 106 break; 107 case 8: 108 reg |= ADC_CTRL_TSC_8WIRE; 109 break; 110 default: 111 break; 112 } 113 } 114 reg |= ADC_CTRL_ENABLE; 115 /* Enable the ADC. Run thru enabled steps, start the conversions. */ 116 ADC_WRITE4(sc, ADC_CTRL, reg); 117 118 sc->sc_last_state = 1; 119 } 120 121 static void 122 ti_adc_disable(struct ti_adc_softc *sc) 123 { 124 int count; 125 uint32_t data; 126 127 TI_ADC_LOCK_ASSERT(sc); 128 129 if (sc->sc_last_state == 0) 130 return; 131 132 /* Disable all the enabled steps. */ 133 ADC_WRITE4(sc, ADC_STEPENABLE, 0); 134 135 /* Disable the ADC. */ 136 ADC_WRITE4(sc, ADC_CTRL, ADC_READ4(sc, ADC_CTRL) & ~ADC_CTRL_ENABLE); 137 138 /* Disable the FIFO0 threshold and the end of sequence interrupt. */ 139 ADC_WRITE4(sc, ADC_IRQENABLE_CLR, 140 ADC_IRQ_FIFO0_THRES | ADC_IRQ_FIFO1_THRES | ADC_IRQ_END_OF_SEQ); 141 142 /* ACK any pending interrupt. */ 143 ADC_WRITE4(sc, ADC_IRQSTATUS, ADC_READ4(sc, ADC_IRQSTATUS)); 144 145 /* Drain the FIFO data. */ 146 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 147 while (count > 0) { 148 data = ADC_READ4(sc, ADC_FIFO0DATA); 149 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 150 } 151 152 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK; 153 while (count > 0) { 154 data = ADC_READ4(sc, ADC_FIFO1DATA); 155 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK; 156 } 157 158 sc->sc_last_state = 0; 159 } 160 161 static int 162 ti_adc_setup(struct ti_adc_softc *sc) 163 { 164 int ain, i; 165 uint32_t enabled; 166 167 TI_ADC_LOCK_ASSERT(sc); 168 169 /* Check for enabled inputs. */ 170 enabled = sc->sc_tsc_enabled; 171 for (i = 0; i < sc->sc_adc_nchannels; i++) { 172 ain = sc->sc_adc_channels[i]; 173 if (ti_adc_inputs[ain].enable) 174 enabled |= (1U << (ain + 1)); 175 } 176 177 /* Set the ADC global status. */ 178 if (enabled != 0) { 179 ti_adc_enable(sc); 180 /* Update the enabled steps. */ 181 if (enabled != ADC_READ4(sc, ADC_STEPENABLE)) 182 ADC_WRITE4(sc, ADC_STEPENABLE, enabled); 183 } else 184 ti_adc_disable(sc); 185 186 return (0); 187 } 188 189 static void 190 ti_adc_input_setup(struct ti_adc_softc *sc, int32_t ain) 191 { 192 struct ti_adc_input *input; 193 uint32_t reg, val; 194 195 TI_ADC_LOCK_ASSERT(sc); 196 197 input = &ti_adc_inputs[ain]; 198 reg = input->stepconfig; 199 val = ADC_READ4(sc, reg); 200 201 /* Set single ended operation. */ 202 val &= ~ADC_STEP_DIFF_CNTRL; 203 204 /* Set the negative voltage reference. */ 205 val &= ~ADC_STEP_RFM_MSK; 206 207 /* Set the positive voltage reference. */ 208 val &= ~ADC_STEP_RFP_MSK; 209 210 /* Set the samples average. */ 211 val &= ~ADC_STEP_AVG_MSK; 212 val |= input->samples << ADC_STEP_AVG_SHIFT; 213 214 /* Select the desired input. */ 215 val &= ~ADC_STEP_INP_MSK; 216 val |= ain << ADC_STEP_INP_SHIFT; 217 218 /* Set the ADC to one-shot mode. */ 219 val &= ~ADC_STEP_MODE_MSK; 220 221 ADC_WRITE4(sc, reg, val); 222 } 223 224 static void 225 ti_adc_reset(struct ti_adc_softc *sc) 226 { 227 int ain, i; 228 229 TI_ADC_LOCK_ASSERT(sc); 230 231 /* Disable all the inputs. */ 232 for (i = 0; i < sc->sc_adc_nchannels; i++) { 233 ain = sc->sc_adc_channels[i]; 234 ti_adc_inputs[ain].enable = 0; 235 } 236 } 237 238 static int 239 ti_adc_clockdiv_proc(SYSCTL_HANDLER_ARGS) 240 { 241 int error, reg; 242 struct ti_adc_softc *sc; 243 244 sc = (struct ti_adc_softc *)arg1; 245 246 TI_ADC_LOCK(sc); 247 reg = (int)ADC_READ4(sc, ADC_CLKDIV) + 1; 248 TI_ADC_UNLOCK(sc); 249 250 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 251 if (error != 0 || req->newptr == NULL) 252 return (error); 253 254 /* 255 * The actual written value is the prescaler setting - 1. 256 * Enforce a minimum value of 10 (i.e. 9) which limits the maximum 257 * ADC clock to ~2.4Mhz (CLK_M_OSC / 10). 258 */ 259 reg--; 260 if (reg < 9) 261 reg = 9; 262 if (reg > USHRT_MAX) 263 reg = USHRT_MAX; 264 265 TI_ADC_LOCK(sc); 266 /* Disable the ADC. */ 267 ti_adc_disable(sc); 268 /* Update the ADC prescaler setting. */ 269 ADC_WRITE4(sc, ADC_CLKDIV, reg); 270 /* Enable the ADC again. */ 271 ti_adc_setup(sc); 272 TI_ADC_UNLOCK(sc); 273 274 return (0); 275 } 276 277 static int 278 ti_adc_enable_proc(SYSCTL_HANDLER_ARGS) 279 { 280 int error; 281 int32_t enable; 282 struct ti_adc_softc *sc; 283 struct ti_adc_input *input; 284 285 input = (struct ti_adc_input *)arg1; 286 sc = input->sc; 287 288 enable = input->enable; 289 error = sysctl_handle_int(oidp, &enable, sizeof(enable), 290 req); 291 if (error != 0 || req->newptr == NULL) 292 return (error); 293 294 if (enable) 295 enable = 1; 296 297 TI_ADC_LOCK(sc); 298 /* Setup the ADC as needed. */ 299 if (input->enable != enable) { 300 input->enable = enable; 301 ti_adc_setup(sc); 302 if (input->enable == 0) 303 input->value = 0; 304 } 305 TI_ADC_UNLOCK(sc); 306 307 return (0); 308 } 309 310 static int 311 ti_adc_open_delay_proc(SYSCTL_HANDLER_ARGS) 312 { 313 int error, reg; 314 struct ti_adc_softc *sc; 315 struct ti_adc_input *input; 316 317 input = (struct ti_adc_input *)arg1; 318 sc = input->sc; 319 320 TI_ADC_LOCK(sc); 321 reg = (int)ADC_READ4(sc, input->stepdelay) & ADC_STEP_OPEN_DELAY; 322 TI_ADC_UNLOCK(sc); 323 324 error = sysctl_handle_int(oidp, ®, sizeof(reg), req); 325 if (error != 0 || req->newptr == NULL) 326 return (error); 327 328 if (reg < 0) 329 reg = 0; 330 331 TI_ADC_LOCK(sc); 332 ADC_WRITE4(sc, input->stepdelay, reg & ADC_STEP_OPEN_DELAY); 333 TI_ADC_UNLOCK(sc); 334 335 return (0); 336 } 337 338 static int 339 ti_adc_samples_avg_proc(SYSCTL_HANDLER_ARGS) 340 { 341 int error, samples, i; 342 struct ti_adc_softc *sc; 343 struct ti_adc_input *input; 344 345 input = (struct ti_adc_input *)arg1; 346 sc = input->sc; 347 348 if (input->samples > nitems(ti_adc_samples)) 349 input->samples = nitems(ti_adc_samples); 350 samples = ti_adc_samples[input->samples]; 351 352 error = sysctl_handle_int(oidp, &samples, 0, req); 353 if (error != 0 || req->newptr == NULL) 354 return (error); 355 356 TI_ADC_LOCK(sc); 357 if (samples != ti_adc_samples[input->samples]) { 358 input->samples = 0; 359 for (i = 0; i < nitems(ti_adc_samples); i++) 360 if (samples >= ti_adc_samples[i]) 361 input->samples = i; 362 ti_adc_input_setup(sc, input->input); 363 } 364 TI_ADC_UNLOCK(sc); 365 366 return (error); 367 } 368 369 static void 370 ti_adc_read_data(struct ti_adc_softc *sc) 371 { 372 int count, ain; 373 struct ti_adc_input *input; 374 uint32_t data; 375 376 TI_ADC_LOCK_ASSERT(sc); 377 378 /* Read the available data. */ 379 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 380 while (count > 0) { 381 data = ADC_READ4(sc, ADC_FIFO0DATA); 382 ain = (data & ADC_FIFO_STEP_ID_MSK) >> ADC_FIFO_STEP_ID_SHIFT; 383 input = &ti_adc_inputs[ain]; 384 if (input->enable == 0) 385 input->value = 0; 386 else 387 input->value = (int32_t)(data & ADC_FIFO_DATA_MSK); 388 count = ADC_READ4(sc, ADC_FIFO0COUNT) & ADC_FIFO_COUNT_MSK; 389 } 390 } 391 392 static int 393 cmp_values(const void *a, const void *b) 394 { 395 const uint32_t *v1, *v2; 396 v1 = a; 397 v2 = b; 398 if (*v1 < *v2) 399 return -1; 400 if (*v1 > *v2) 401 return 1; 402 403 return (0); 404 } 405 406 static void 407 ti_adc_tsc_read_data(struct ti_adc_softc *sc) 408 { 409 int count; 410 uint32_t data[16]; 411 uint32_t x, y; 412 int i, start, end; 413 414 TI_ADC_LOCK_ASSERT(sc); 415 416 /* Read the available data. */ 417 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK; 418 if (count == 0) 419 return; 420 421 i = 0; 422 while (count > 0) { 423 data[i++] = ADC_READ4(sc, ADC_FIFO1DATA) & ADC_FIFO_DATA_MSK; 424 count = ADC_READ4(sc, ADC_FIFO1COUNT) & ADC_FIFO_COUNT_MSK; 425 } 426 427 if (sc->sc_coord_readouts > 3) { 428 start = 1; 429 end = sc->sc_coord_readouts - 1; 430 qsort(data, sc->sc_coord_readouts, 431 sizeof(data[0]), &cmp_values); 432 qsort(&data[sc->sc_coord_readouts + 2], 433 sc->sc_coord_readouts, 434 sizeof(data[0]), &cmp_values); 435 } 436 else { 437 start = 0; 438 end = sc->sc_coord_readouts; 439 } 440 441 x = y = 0; 442 for (i = start; i < end; i++) 443 y += data[i]; 444 y /= (end - start); 445 446 for (i = sc->sc_coord_readouts + 2 + start; i < sc->sc_coord_readouts + 2 + end; i++) 447 x += data[i]; 448 x /= (end - start); 449 450 #ifdef DEBUG_TSC 451 device_printf(sc->sc_dev, "touchscreen x: %d, y: %d\n", x, y); 452 #endif 453 /* TODO: That's where actual event reporting should take place */ 454 } 455 456 static void 457 ti_adc_intr_locked(struct ti_adc_softc *sc, uint32_t status) 458 { 459 /* Read the available data. */ 460 if (status & ADC_IRQ_FIFO0_THRES) 461 ti_adc_read_data(sc); 462 } 463 464 static void 465 ti_adc_tsc_intr_locked(struct ti_adc_softc *sc, uint32_t status) 466 { 467 /* Read the available data. */ 468 if (status & ADC_IRQ_FIFO1_THRES) 469 ti_adc_tsc_read_data(sc); 470 471 } 472 473 static void 474 ti_adc_intr(void *arg) 475 { 476 struct ti_adc_softc *sc; 477 uint32_t status, rawstatus; 478 479 sc = (struct ti_adc_softc *)arg; 480 481 TI_ADC_LOCK(sc); 482 483 rawstatus = ADC_READ4(sc, ADC_IRQSTATUS_RAW); 484 status = ADC_READ4(sc, ADC_IRQSTATUS); 485 486 if (rawstatus & ADC_IRQ_HW_PEN_ASYNC) { 487 sc->sc_pen_down = 1; 488 status |= ADC_IRQ_HW_PEN_ASYNC; 489 ADC_WRITE4(sc, ADC_IRQENABLE_CLR, 490 ADC_IRQ_HW_PEN_ASYNC); 491 } 492 493 if (rawstatus & ADC_IRQ_PEN_UP) { 494 sc->sc_pen_down = 0; 495 status |= ADC_IRQ_PEN_UP; 496 } 497 498 if (status & ADC_IRQ_FIFO0_THRES) 499 ti_adc_intr_locked(sc, status); 500 501 if (status & ADC_IRQ_FIFO1_THRES) 502 ti_adc_tsc_intr_locked(sc, status); 503 504 if (status) { 505 /* ACK the interrupt. */ 506 ADC_WRITE4(sc, ADC_IRQSTATUS, status); 507 } 508 509 /* Start the next conversion ? */ 510 if (status & ADC_IRQ_END_OF_SEQ) 511 ti_adc_setup(sc); 512 513 TI_ADC_UNLOCK(sc); 514 } 515 516 static void 517 ti_adc_sysctl_init(struct ti_adc_softc *sc) 518 { 519 char pinbuf[3]; 520 struct sysctl_ctx_list *ctx; 521 struct sysctl_oid *tree_node, *inp_node, *inpN_node; 522 struct sysctl_oid_list *tree, *inp_tree, *inpN_tree; 523 int ain, i; 524 525 /* 526 * Add per-pin sysctl tree/handlers. 527 */ 528 ctx = device_get_sysctl_ctx(sc->sc_dev); 529 tree_node = device_get_sysctl_tree(sc->sc_dev); 530 tree = SYSCTL_CHILDREN(tree_node); 531 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clockdiv", 532 CTLFLAG_RW | CTLTYPE_UINT, sc, 0, 533 ti_adc_clockdiv_proc, "IU", "ADC clock prescaler"); 534 inp_node = SYSCTL_ADD_NODE(ctx, tree, OID_AUTO, "ain", 535 CTLFLAG_RD, NULL, "ADC inputs"); 536 inp_tree = SYSCTL_CHILDREN(inp_node); 537 538 for (i = 0; i < sc->sc_adc_nchannels; i++) { 539 ain = sc->sc_adc_channels[i]; 540 541 snprintf(pinbuf, sizeof(pinbuf), "%d", ain); 542 inpN_node = SYSCTL_ADD_NODE(ctx, inp_tree, OID_AUTO, pinbuf, 543 CTLFLAG_RD, NULL, "ADC input"); 544 inpN_tree = SYSCTL_CHILDREN(inpN_node); 545 546 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "enable", 547 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0, 548 ti_adc_enable_proc, "IU", "Enable ADC input"); 549 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "open_delay", 550 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0, 551 ti_adc_open_delay_proc, "IU", "ADC open delay"); 552 SYSCTL_ADD_PROC(ctx, inpN_tree, OID_AUTO, "samples_avg", 553 CTLFLAG_RW | CTLTYPE_UINT, &ti_adc_inputs[ain], 0, 554 ti_adc_samples_avg_proc, "IU", "ADC samples average"); 555 SYSCTL_ADD_INT(ctx, inpN_tree, OID_AUTO, "input", 556 CTLFLAG_RD, &ti_adc_inputs[ain].value, 0, 557 "Converted raw value for the ADC input"); 558 } 559 } 560 561 static void 562 ti_adc_inputs_init(struct ti_adc_softc *sc) 563 { 564 int ain, i; 565 struct ti_adc_input *input; 566 567 TI_ADC_LOCK(sc); 568 for (i = 0; i < sc->sc_adc_nchannels; i++) { 569 ain = sc->sc_adc_channels[i]; 570 input = &ti_adc_inputs[ain]; 571 input->sc = sc; 572 input->input = ain; 573 input->value = 0; 574 input->enable = 0; 575 input->samples = 0; 576 ti_adc_input_setup(sc, ain); 577 } 578 TI_ADC_UNLOCK(sc); 579 } 580 581 static void 582 ti_adc_tsc_init(struct ti_adc_softc *sc) 583 { 584 int i, start_step, end_step; 585 uint32_t stepconfig, val; 586 587 TI_ADC_LOCK(sc); 588 589 /* X coordinates */ 590 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) | 591 ADC_STEP_MODE_HW_ONESHOT | sc->sc_xp_bit; 592 if (sc->sc_tsc_wires == 4) 593 stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit; 594 else if (sc->sc_tsc_wires == 5) 595 stepconfig |= ADC_STEP_INP(4) | 596 sc->sc_xn_bit | sc->sc_yn_bit | sc->sc_yp_bit; 597 else if (sc->sc_tsc_wires == 8) 598 stepconfig |= ADC_STEP_INP(sc->sc_yp_inp) | sc->sc_xn_bit; 599 600 start_step = ADC_STEPS - sc->sc_coord_readouts + 1; 601 end_step = start_step + sc->sc_coord_readouts - 1; 602 for (i = start_step; i <= end_step; i++) { 603 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig); 604 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN); 605 } 606 607 /* Y coordinates */ 608 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) | 609 ADC_STEP_MODE_HW_ONESHOT | sc->sc_yn_bit | 610 ADC_STEP_INM(8); 611 if (sc->sc_tsc_wires == 4) 612 stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit; 613 else if (sc->sc_tsc_wires == 5) 614 stepconfig |= ADC_STEP_INP(4) | 615 sc->sc_xp_bit | sc->sc_xn_bit | sc->sc_yp_bit; 616 else if (sc->sc_tsc_wires == 8) 617 stepconfig |= ADC_STEP_INP(sc->sc_xp_inp) | sc->sc_yp_bit; 618 619 start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1; 620 end_step = start_step + sc->sc_coord_readouts - 1; 621 for (i = start_step; i <= end_step; i++) { 622 ADC_WRITE4(sc, ADC_STEPCFG(i), stepconfig); 623 ADC_WRITE4(sc, ADC_STEPDLY(i), STEPDLY_OPEN); 624 } 625 626 /* Charge config */ 627 val = ADC_READ4(sc, ADC_IDLECONFIG); 628 ADC_WRITE4(sc, ADC_TC_CHARGE_STEPCONFIG, val); 629 ADC_WRITE4(sc, ADC_TC_CHARGE_DELAY, sc->sc_charge_delay); 630 631 /* 2 steps for Z */ 632 start_step = ADC_STEPS - (sc->sc_coord_readouts + 2) + 1; 633 stepconfig = ADC_STEP_FIFO1 | (4 << ADC_STEP_AVG_SHIFT) | 634 ADC_STEP_MODE_HW_ONESHOT | sc->sc_yp_bit | 635 sc->sc_xn_bit | ADC_STEP_INP(sc->sc_xp_inp) | 636 ADC_STEP_INM(8); 637 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig); 638 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN); 639 start_step++; 640 stepconfig |= ADC_STEP_INP(sc->sc_yn_inp); 641 ADC_WRITE4(sc, ADC_STEPCFG(start_step), stepconfig); 642 ADC_WRITE4(sc, ADC_STEPDLY(start_step), STEPDLY_OPEN); 643 644 ADC_WRITE4(sc, ADC_FIFO1THRESHOLD, (sc->sc_coord_readouts*2 + 2) - 1); 645 646 sc->sc_tsc_enabled = 1; 647 start_step = ADC_STEPS - (sc->sc_coord_readouts*2 + 2) + 1; 648 end_step = ADC_STEPS; 649 for (i = start_step; i <= end_step; i++) { 650 sc->sc_tsc_enabled |= (1 << i); 651 } 652 653 654 TI_ADC_UNLOCK(sc); 655 } 656 657 static void 658 ti_adc_idlestep_init(struct ti_adc_softc *sc) 659 { 660 uint32_t val; 661 662 val = ADC_STEP_YNN_SW | ADC_STEP_INM(8) | ADC_STEP_INP(8) | ADC_STEP_YPN_SW; 663 664 ADC_WRITE4(sc, ADC_IDLECONFIG, val); 665 } 666 667 static int 668 ti_adc_config_wires(struct ti_adc_softc *sc, int *wire_configs, int nwire_configs) 669 { 670 int i; 671 int wire, ai; 672 673 for (i = 0; i < nwire_configs; i++) { 674 wire = wire_configs[i] & 0xf; 675 ai = (wire_configs[i] >> 4) & 0xf; 676 switch (wire) { 677 case ORDER_XP: 678 sc->sc_xp_bit = ADC_STEP_XPP_SW; 679 sc->sc_xp_inp = ai; 680 break; 681 case ORDER_XN: 682 sc->sc_xn_bit = ADC_STEP_XNN_SW; 683 sc->sc_xn_inp = ai; 684 break; 685 case ORDER_YP: 686 sc->sc_yp_bit = ADC_STEP_YPP_SW; 687 sc->sc_yp_inp = ai; 688 break; 689 case ORDER_YN: 690 sc->sc_yn_bit = ADC_STEP_YNN_SW; 691 sc->sc_yn_inp = ai; 692 break; 693 default: 694 device_printf(sc->sc_dev, "Invalid wire config\n"); 695 return (-1); 696 } 697 } 698 return (0); 699 } 700 701 static int 702 ti_adc_probe(device_t dev) 703 { 704 705 if (!ofw_bus_is_compatible(dev, "ti,am3359-tscadc")) 706 return (ENXIO); 707 device_set_desc(dev, "TI ADC controller"); 708 709 return (BUS_PROBE_DEFAULT); 710 } 711 712 static int 713 ti_adc_attach(device_t dev) 714 { 715 int err, rid, i; 716 struct ti_adc_softc *sc; 717 uint32_t rev, reg; 718 phandle_t node, child; 719 pcell_t cell; 720 int *channels; 721 int nwire_configs; 722 int *wire_configs; 723 724 sc = device_get_softc(dev); 725 sc->sc_dev = dev; 726 727 node = ofw_bus_get_node(dev); 728 729 sc->sc_tsc_wires = 0; 730 sc->sc_coord_readouts = 1; 731 sc->sc_x_plate_resistance = 0; 732 sc->sc_charge_delay = DEFAULT_CHARGE_DELAY; 733 /* Read "tsc" node properties */ 734 child = ofw_bus_find_child(node, "tsc"); 735 if (child != 0 && OF_hasprop(child, "ti,wires")) { 736 if ((OF_getprop(child, "ti,wires", &cell, sizeof(cell))) > 0) 737 sc->sc_tsc_wires = fdt32_to_cpu(cell); 738 if ((OF_getprop(child, "ti,coordinate-readouts", &cell, sizeof(cell))) > 0) 739 sc->sc_coord_readouts = fdt32_to_cpu(cell); 740 if ((OF_getprop(child, "ti,x-plate-resistance", &cell, sizeof(cell))) > 0) 741 sc->sc_x_plate_resistance = fdt32_to_cpu(cell); 742 if ((OF_getprop(child, "ti,charge-delay", &cell, sizeof(cell))) > 0) 743 sc->sc_charge_delay = fdt32_to_cpu(cell); 744 nwire_configs = OF_getencprop_alloc(child, "ti,wire-config", 745 sizeof(*wire_configs), (void **)&wire_configs); 746 if (nwire_configs != sc->sc_tsc_wires) { 747 device_printf(sc->sc_dev, 748 "invalid number of ti,wire-config: %d (should be %d)\n", 749 nwire_configs, sc->sc_tsc_wires); 750 OF_prop_free(wire_configs); 751 return (EINVAL); 752 } 753 err = ti_adc_config_wires(sc, wire_configs, nwire_configs); 754 OF_prop_free(wire_configs); 755 if (err) 756 return (EINVAL); 757 } 758 759 /* Read "adc" node properties */ 760 child = ofw_bus_find_child(node, "adc"); 761 if (child != 0) { 762 sc->sc_adc_nchannels = OF_getencprop_alloc(child, "ti,adc-channels", 763 sizeof(*channels), (void **)&channels); 764 if (sc->sc_adc_nchannels > 0) { 765 for (i = 0; i < sc->sc_adc_nchannels; i++) 766 sc->sc_adc_channels[i] = channels[i]; 767 OF_prop_free(channels); 768 } 769 } 770 771 /* Sanity check FDT data */ 772 if (sc->sc_tsc_wires + sc->sc_adc_nchannels > TI_ADC_NPINS) { 773 device_printf(dev, "total number of chanels (%d) is larger than %d\n", 774 sc->sc_tsc_wires + sc->sc_adc_nchannels, TI_ADC_NPINS); 775 return (ENXIO); 776 } 777 778 rid = 0; 779 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 780 RF_ACTIVE); 781 if (!sc->sc_mem_res) { 782 device_printf(dev, "cannot allocate memory window\n"); 783 return (ENXIO); 784 } 785 786 /* Activate the ADC_TSC module. */ 787 err = ti_prcm_clk_enable(TSC_ADC_CLK); 788 if (err) 789 return (err); 790 791 rid = 0; 792 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 793 RF_ACTIVE); 794 if (!sc->sc_irq_res) { 795 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 796 device_printf(dev, "cannot allocate interrupt\n"); 797 return (ENXIO); 798 } 799 800 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 801 NULL, ti_adc_intr, sc, &sc->sc_intrhand) != 0) { 802 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 803 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 804 device_printf(dev, "Unable to setup the irq handler.\n"); 805 return (ENXIO); 806 } 807 808 /* Check the ADC revision. */ 809 rev = ADC_READ4(sc, ADC_REVISION); 810 device_printf(dev, 811 "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n", 812 (rev & ADC_REV_SCHEME_MSK) >> ADC_REV_SCHEME_SHIFT, 813 (rev & ADC_REV_FUNC_MSK) >> ADC_REV_FUNC_SHIFT, 814 (rev & ADC_REV_RTL_MSK) >> ADC_REV_RTL_SHIFT, 815 (rev & ADC_REV_MAJOR_MSK) >> ADC_REV_MAJOR_SHIFT, 816 rev & ADC_REV_MINOR_MSK, 817 (rev & ADC_REV_CUSTOM_MSK) >> ADC_REV_CUSTOM_SHIFT); 818 819 reg = ADC_READ4(sc, ADC_CTRL); 820 ADC_WRITE4(sc, ADC_CTRL, reg | ADC_CTRL_STEP_WP | ADC_CTRL_STEP_ID); 821 822 /* 823 * Set the ADC prescaler to 2400 if touchscreen is not enabled 824 * and to 24 if it is. This sets the ADC clock to ~10Khz and 825 * ~1Mhz respectively (CLK_M_OSC / prescaler). 826 */ 827 if (sc->sc_tsc_wires) 828 ADC_WRITE4(sc, ADC_CLKDIV, 24 - 1); 829 else 830 ADC_WRITE4(sc, ADC_CLKDIV, 2400 - 1); 831 832 TI_ADC_LOCK_INIT(sc); 833 834 ti_adc_idlestep_init(sc); 835 ti_adc_inputs_init(sc); 836 ti_adc_sysctl_init(sc); 837 ti_adc_tsc_init(sc); 838 839 TI_ADC_LOCK(sc); 840 ti_adc_setup(sc); 841 TI_ADC_UNLOCK(sc); 842 843 return (0); 844 } 845 846 static int 847 ti_adc_detach(device_t dev) 848 { 849 struct ti_adc_softc *sc; 850 851 sc = device_get_softc(dev); 852 853 /* Turn off the ADC. */ 854 TI_ADC_LOCK(sc); 855 ti_adc_reset(sc); 856 ti_adc_setup(sc); 857 TI_ADC_UNLOCK(sc); 858 859 TI_ADC_LOCK_DESTROY(sc); 860 861 if (sc->sc_intrhand) 862 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 863 if (sc->sc_irq_res) 864 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 865 if (sc->sc_mem_res) 866 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 867 868 return (bus_generic_detach(dev)); 869 } 870 871 static device_method_t ti_adc_methods[] = { 872 DEVMETHOD(device_probe, ti_adc_probe), 873 DEVMETHOD(device_attach, ti_adc_attach), 874 DEVMETHOD(device_detach, ti_adc_detach), 875 876 DEVMETHOD_END 877 }; 878 879 static driver_t ti_adc_driver = { 880 "ti_adc", 881 ti_adc_methods, 882 sizeof(struct ti_adc_softc), 883 }; 884 885 static devclass_t ti_adc_devclass; 886 887 DRIVER_MODULE(ti_adc, simplebus, ti_adc_driver, ti_adc_devclass, 0, 0); 888 MODULE_VERSION(ti_adc, 1); 889 MODULE_DEPEND(ti_adc, simplebus, 1, 1, 1); 890