1 /*- 2 * Copyright (c) 2011 3 * Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 /* 31 * Texas Instruments - OMAP44xx series processors 32 * 33 * Reference: 34 * OMAP44xx Applications Processor 35 * Technical Reference Manual 36 * (omap44xx_techref.pdf) 37 * 38 * 39 * Note: 40 * The devices are mapped into address above 0xD000_0000 as the kernel space 41 * memory is at 0xC000_0000 and above. The first 256MB after this is reserved 42 * for the size of the kernel, everything above that is reserved for SoC 43 * devices. 44 * 45 */ 46 #ifndef _OMAP44XX_REG_H_ 47 #define _OMAP44XX_REG_H_ 48 49 #ifndef _LOCORE 50 #include <sys/types.h> /* for uint32_t */ 51 #endif 52 53 54 55 56 57 /* Physical/Virtual address for SDRAM controller */ 58 59 #define OMAP44XX_SMS_VBASE 0x6C000000UL 60 #define OMAP44XX_SMS_HWBASE 0x6C000000UL 61 #define OMAP44XX_SMS_SIZE 0x01000000UL 62 63 #define OMAP44XX_SDRC_VBASE 0x6D000000UL 64 #define OMAP44XX_SDRC_HWBASE 0x6D000000UL 65 #define OMAP44XX_SDRC_SIZE 0x01000000UL 66 67 68 69 /* Physical/Virtual address for I/O space */ 70 71 #define OMAP44XX_L3_EMU_VBASE 0xD4000000UL 72 #define OMAP44XX_L3_EMU_HWBASE 0x54000000UL 73 #define OMAP44XX_L3_EMU_SIZE 0x00200000UL 74 75 #define OMAP44XX_L3_EMIF1_VBASE 0xEC000000UL 76 #define OMAP44XX_L3_EMIF1_HWBASE 0x4C000000UL 77 #define OMAP44XX_L3_EMIF1_SIZE 0x01000000UL 78 79 #define OMAP44XX_L3_EMIF2_VBASE 0xED000000UL 80 #define OMAP44XX_L3_EMIF2_HWBASE 0x4D000000UL 81 #define OMAP44XX_L3_EMIF2_SIZE 0x01000000UL 82 83 84 #define OMAP44XX_L4_CORE_VBASE 0xEA000000UL 85 #define OMAP44XX_L4_CORE_HWBASE 0x4A000000UL 86 #define OMAP44XX_L4_CORE_SIZE 0x01000000UL 87 88 #define OMAP44XX_L4_WAKEUP_VBASE 0xEA300000UL 89 #define OMAP44XX_L4_WAKEUP_HWBASE 0x4A300000UL 90 #define OMAP44XX_L4_WAKEUP_SIZE 0x00040000UL 91 92 #define OMAP44XX_L4_PERIPH_VBASE 0xE8000000UL 93 #define OMAP44XX_L4_PERIPH_HWBASE 0x48000000UL 94 #define OMAP44XX_L4_PERIPH_SIZE 0x01000000UL 95 96 #define OMAP44XX_L4_ABE_VBASE 0xE9000000UL 97 #define OMAP44XX_L4_ABE_HWBASE 0x49000000UL 98 #define OMAP44XX_L4_ABE_SIZE 0x00100000UL 99 100 101 /* Physical/Virtual address for MPU Subsystem space */ 102 103 #define OMAP44XX_MPU_SUBSYS_VBASE (OMAP44XX_L4_PERIPH_VBASE + 0x00240000UL) 104 #define OMAP44XX_MPU_SUBSYS_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + 0x00240000UL) 105 #define OMAP44XX_MPU_SUBSYS_SIZE 0x00004000UL 106 107 /* 108 * MPU Subsystem addresss offsets 109 */ 110 #define OMAP44XX_SCU_OFFSET 0x00000000UL 111 #define OMAP44XX_GIC_CPU_OFFSET 0x00000100UL 112 #define OMAP44XX_GBL_TIMER_OFFSET 0x00000200UL 113 #define OMAP44XX_PRV_TIMER_OFFSET 0x00000600UL 114 #define OMAP44XX_GIC_DIST_OFFSET 0x00001000UL 115 #define OMAP44XX_PL310_OFFSET 0x00002000UL 116 #define OMAP44XX_CORTEXA9_SOCKET_PRCM_OFFSET 0x00003000UL 117 #define OMAP44XX_CORTEXA9_PRM_OFFSET 0x00003200UL 118 #define OMAP44XX_CORTEXA9_CPU0_OFFSET 0x00003400UL 119 #define OMAP44XX_CORTEXA9_CPU1_OFFSET 0x00003800UL 120 121 #define OMAP44XX_SCU_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_SCU_OFFSET) 122 #define OMAP44XX_SCU_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_SCU_OFFSET) 123 #define OMAP44XX_SCU_SIZE 0x00000080UL 124 #define OMAP44XX_GIC_CPU_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_GIC_CPU_OFFSET) 125 #define OMAP44XX_GIC_CPU_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_GIC_CPU_OFFSET) 126 #define OMAP44XX_GIC_CPU_SIZE 0x00000100UL 127 #define OMAP44XX_GBL_TIMER_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_GBL_TIMER_OFFSET) 128 #define OMAP44XX_GBL_TIMER_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_GBL_TIMER_OFFSET) 129 #define OMAP44XX_GBL_TIMER_SIZE 0x00000100UL 130 #define OMAP44XX_PRV_TIMER_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_PRV_TIMER_OFFSET) 131 #define OMAP44XX_PRV_TIMER_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_PRV_TIMER_OFFSET) 132 #define OMAP44XX_PRV_TIMER_SIZE 0x00000100UL 133 #define OMAP44XX_GIC_DIST_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_GIC_DIST_OFFSET) 134 #define OMAP44XX_GIC_DIST_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_GIC_DIST_OFFSET) 135 #define OMAP44XX_GIC_DIST_SIZE 0x00000100UL 136 #define OMAP44XX_PL310_HWBASE (OMAP44XX_MPU_SUBSYS_HWBASE + OMAP44XX_PL310_OFFSET) 137 #define OMAP44XX_PL310_VBASE (OMAP44XX_MPU_SUBSYS_VBASE + OMAP44XX_PL310_OFFSET) 138 #define OMAP44XX_PL310_SIZE 0x00001000UL 139 140 141 142 143 /* 144 * L4-CORE Physical/Virtual addresss offsets 145 */ 146 #define OMAP44XX_SCM_OFFSET 0x00002000UL 147 #define OMAP44XX_CM_OFFSET 0x00004000UL 148 #define OMAP44XX_SDMA_OFFSET 0x00056000UL 149 #define OMAP44XX_USB_TLL_OFFSET 0x00062000UL 150 #define OMAP44XX_USB_UHH_OFFSET 0x00064000UL 151 #define OMAP44XX_USB_OHCI_OFFSET 0x00064800UL 152 #define OMAP44XX_USB_EHCI_OFFSET 0x00064C00UL 153 #define OMAP44XX_MCBSP1_OFFSET 0x00074000UL 154 #define OMAP44XX_MCBSP5_OFFSET 0x00096000UL 155 #define OMAP44XX_SCM_PADCONF_OFFSET 0x00100000UL 156 157 /* 158 * L4-WAKEUP Physical/Virtual addresss offsets 159 */ 160 #define OMAP44XX_PRM_OFFSET 0x00006000UL 161 #define OMAP44XX_SCRM_OFFSET 0x0000A000UL 162 #define OMAP44XX_GPIO1_OFFSET 0x00010000UL 163 #define OMAP44XX_GPTIMER1_OFFSET 0x00018000UL 164 165 166 167 /* 168 * L4-PERIPH Physical/Virtual addresss offsets 169 */ 170 #define OMAP44XX_UART3_OFFSET 0x00020000UL 171 #define OMAP44XX_GPTIMER2_OFFSET 0x00032000UL 172 #define OMAP44XX_GPTIMER3_OFFSET 0x00034000UL 173 #define OMAP44XX_GPTIMER4_OFFSET 0x00036000UL 174 #define OMAP44XX_GPTIMER9_OFFSET 0x0003E000UL 175 #define OMAP44XX_GPIO2_OFFSET 0x00055000UL 176 #define OMAP44XX_GPIO3_OFFSET 0x00057000UL 177 #define OMAP44XX_GPIO4_OFFSET 0x00059000UL 178 #define OMAP44XX_GPIO5_OFFSET 0x0005B000UL 179 #define OMAP44XX_GPIO6_OFFSET 0x0005D000UL 180 #define OMAP44XX_I2C3_OFFSET 0x00060000UL 181 #define OMAP44XX_UART1_OFFSET 0x0006A000UL 182 #define OMAP44XX_UART2_OFFSET 0x0006C000UL 183 #define OMAP44XX_UART4_OFFSET 0x0006E000UL 184 #define OMAP44XX_I2C1_OFFSET 0x00070000UL 185 #define OMAP44XX_I2C2_OFFSET 0x00072000UL 186 #define OMAP44XX_SLIMBUS2_OFFSET 0x00076000UL 187 #define OMAP44XX_ELM_OFFSET 0x00078000UL 188 #define OMAP44XX_GPTIMER10_OFFSET 0x00086000UL 189 #define OMAP44XX_GPTIMER11_OFFSET 0x00088000UL 190 #define OMAP44XX_MCBSP4_OFFSET 0x00096000UL 191 #define OMAP44XX_MCSPI1_OFFSET 0x00098000UL 192 #define OMAP44XX_MCSPI2_OFFSET 0x0009A000UL 193 #define OMAP44XX_MMCHS1_OFFSET 0x0009C000UL 194 #define OMAP44XX_MMCSD3_OFFSET 0x000AD000UL 195 #define OMAP44XX_MMCHS2_OFFSET 0x000B4000UL 196 #define OMAP44XX_MMCSD4_OFFSET 0x000D1000UL 197 #define OMAP44XX_MMCSD5_OFFSET 0x000D5000UL 198 #define OMAP44XX_I2C4_OFFSET 0x00350000UL 199 200 /* The following are registers defined as part of the ARM MPCORE system, 201 * they are not SoC components rather registers that control the MPCORE core. 202 */ 203 // #define OMAP44XX_SCU_OFFSET 0x48240000 /* Snoop control unit */ 204 // #define OMAP44XX_GIC_PROC_OFFSET 0x48240100 /* Interrupt controller unit */ 205 // #define OMAP44XX_MPU_TIMER_OFFSET 0x48240600 206 // #define OMAP44XX_GIC_INTR_OFFSET 0x48241000 207 // #define OMAP44XX_PL310_OFFSET 0x48242000 /* L2 Cache controller */ 208 209 210 /* 211 * L4-ABE Physical/Virtual addresss offsets 212 */ 213 #define OMAP44XX_GPTIMER5_OFFSET 0x00038000UL 214 #define OMAP44XX_GPTIMER6_OFFSET 0x0003A000UL 215 #define OMAP44XX_GPTIMER7_OFFSET 0x0003C000UL 216 #define OMAP44XX_GPTIMER8_OFFSET 0x0003E000UL 217 218 219 220 221 222 /* 223 * System Control Module 224 */ 225 #define OMAP44XX_SCM_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_SCM_OFFSET) 226 #define OMAP44XX_SCM_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_SCM_OFFSET) 227 #define OMAP44XX_SCM_SIZE 0x00001000UL 228 229 230 231 /* 232 * 233 */ 234 #define OMAP44XX_CM_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_CM_OFFSET) 235 #define OMAP44XX_CM_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_CM_OFFSET) 236 #define OMAP44XX_CM_SIZE 0x00001500UL 237 238 239 /* 240 * 241 */ 242 #define OMAP44XX_PRM_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_PRM_OFFSET) 243 #define OMAP44XX_PRM_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_PRM_OFFSET) 244 #define OMAP44XX_PRM_SIZE 0x00001600UL 245 246 /* 247 * 248 */ 249 #define OMAP44XX_SCRM_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_SCRM_OFFSET) 250 #define OMAP44XX_SCRM_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_SCRM_OFFSET) 251 #define OMAP44XX_SCRM_SIZE 0x00000800UL 252 253 254 255 /* 256 * Uarts 257 */ 258 #define OMAP44XX_UART1_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_UART1_OFFSET) 259 #define OMAP44XX_UART1_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_UART1_OFFSET) 260 #define OMAP44XX_UART1_SIZE 0x00001000UL 261 #define OMAP44XX_UART2_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_UART2_OFFSET) 262 #define OMAP44XX_UART2_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_UART2_OFFSET) 263 #define OMAP44XX_UART2_SIZE 0x00001000UL 264 #define OMAP44XX_UART3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_UART3_OFFSET) 265 #define OMAP44XX_UART3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_UART3_OFFSET) 266 #define OMAP44XX_UART3_SIZE 0x00001000UL 267 #define OMAP44XX_UART4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_UART4_OFFSET) 268 #define OMAP44XX_UART4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_UART4_OFFSET) 269 #define OMAP44XX_UART4_SIZE 0x00001000UL 270 271 272 273 274 /* 275 * I2C Modules 276 */ 277 #define OMAP44XX_I2C1_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_I2C1_OFFSET) 278 #define OMAP44XX_I2C1_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_I2C1_OFFSET) 279 #define OMAP44XX_I2C1_SIZE 0x00000080UL 280 #define OMAP44XX_I2C2_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_I2C2_OFFSET) 281 #define OMAP44XX_I2C2_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_I2C2_OFFSET) 282 #define OMAP44XX_I2C2_SIZE 0x00000080UL 283 #define OMAP44XX_I2C3_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_I2C3_OFFSET) 284 #define OMAP44XX_I2C3_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_I2C3_OFFSET) 285 #define OMAP44XX_I2C3_SIZE 0x00000080UL 286 287 288 289 /* 290 * McBSP Modules 291 */ 292 #define OMAP44XX_MCBSP1_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_MCBSP1_OFFSET) 293 #define OMAP44XX_MCBSP1_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_MCBSP1_OFFSET) 294 #define OMAP44XX_MCBSP1_SIZE 0x00001000UL 295 #define OMAP44XX_MCBSP2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MCBSP2_OFFSET) 296 #define OMAP44XX_MCBSP2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MCBSP2_OFFSET) 297 #define OMAP44XX_MCBSP2_SIZE 0x00001000UL 298 #define OMAP44XX_MCBSP3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MCBSP3_OFFSET) 299 #define OMAP44XX_MCBSP3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MCBSP3_OFFSET) 300 #define OMAP44XX_MCBSP3_SIZE 0x00001000UL 301 #define OMAP44XX_MCBSP4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MCBSP4_OFFSET) 302 #define OMAP44XX_MCBSP4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MCBSP4_OFFSET) 303 #define OMAP44XX_MCBSP4_SIZE 0x00001000UL 304 #define OMAP44XX_MCBSP5_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_MCBSP5_OFFSET) 305 #define OMAP44XX_MCBSP5_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_MCBSP5_OFFSET) 306 #define OMAP44XX_MCBSP5_SIZE 0x00001000UL 307 308 309 310 /* 311 * USB TTL Module 312 */ 313 #define OMAP44XX_USB_TLL_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_TLL_OFFSET) 314 #define OMAP44XX_USB_TLL_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_TLL_OFFSET) 315 #define OMAP44XX_USB_TLL_SIZE 0x00001000UL 316 317 /* 318 * USB Host Module 319 */ 320 #define OMAP44XX_USB_UHH_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_UHH_OFFSET) 321 #define OMAP44XX_USB_UHH_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_UHH_OFFSET) 322 #define OMAP44XX_USB_UHH_SIZE 0x00000700UL 323 324 /* 325 * USB OHCI Module 326 */ 327 #define OMAP44XX_USB_OHCI_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_OHCI_OFFSET) 328 #define OMAP44XX_USB_OHCI_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_OHCI_OFFSET) 329 #define OMAP44XX_USB_OHCI_SIZE 0x00000400UL 330 331 /* 332 * USB EHCI Module 333 */ 334 #define OMAP44XX_USB_EHCI_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_USB_EHCI_OFFSET) 335 #define OMAP44XX_USB_EHCI_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_USB_EHCI_OFFSET) 336 #define OMAP44XX_USB_EHCI_SIZE 0x0000400UL 337 338 339 340 341 342 /* 343 * SDMA Offset 344 * PA 0x4805 6000 345 */ 346 347 #define OMAP44XX_SDMA_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_SDMA_OFFSET) 348 #define OMAP44XX_SDMA_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_SDMA_OFFSET) 349 #define OMAP44XX_SDMA_SIZE 0x00001000UL 350 351 352 353 /* 354 * Interrupt Controller Unit. 355 * 356 * Refer to the omap4_intr.c file for interrupt controller (GIC) 357 * implementation. 358 * 359 * Note: 360 * - 16 Interprocessor interrupts (IPI): ID[15:0] 361 * - 2 private Timer/Watchdog interrupts: ID[30:29] 362 * - 2 legacy nFIQ & nIRQ: one per CPU, bypasses the interrupt distributor 363 * logic and directly drives interrupt requests into CPU if used in 364 * legacy mode (else treated like other interrupts lines with ID28 365 * and ID31 respectively) 366 * - 128 hardware interrupts: ID[159:32] (rising-edge or high-level sensitive). 367 */ 368 #define OMAP44XX_HARDIRQ(x) (32 + (x)) 369 370 #define OMAP44XX_IRQ_L2CACHE OMAP44XX_HARDIRQ(0) /* L2 cache controller interrupt */ 371 #define OMAP44XX_IRQ_CTI_0 OMAP44XX_HARDIRQ(1) /* Cross-trigger module 0 (CTI0) interrupt */ 372 #define OMAP44XX_IRQ_CTI_1 OMAP44XX_HARDIRQ(2) /* Cross-trigger module 1 (CTI1) interrupt */ 373 #define OMAP44XX_IRQ_RESERVED3 OMAP44XX_HARDIRQ(3) /* RESERVED */ 374 #define OMAP44XX_IRQ_ELM OMAP44XX_HARDIRQ(4) /* Error location process completion */ 375 #define OMAP44XX_IRQ_RESERVED5 OMAP44XX_HARDIRQ(5) /* RESERVED */ 376 #define OMAP44XX_IRQ_RESERVED6 OMAP44XX_HARDIRQ(6) /* RESERVED */ 377 #define OMAP44XX_IRQ_SYS_NIRQ OMAP44XX_HARDIRQ(7) /* External source (active low) */ 378 #define OMAP44XX_IRQ_RESERVED8 OMAP44XX_HARDIRQ(8) /* RESERVED */ 379 #define OMAP44XX_IRQ_L3_DBG OMAP44XX_HARDIRQ(9) /* L3 interconnect debug error */ 380 #define OMAP44XX_IRQ_L3_APP OMAP44XX_HARDIRQ(10) /* L3 interconnect application error */ 381 #define OMAP44XX_IRQ_PRCM_MPU OMAP44XX_HARDIRQ(11) /* PRCM module IRQ */ 382 #define OMAP44XX_IRQ_SDMA0 OMAP44XX_HARDIRQ(12) /* System DMA request 0(3) */ 383 #define OMAP44XX_IRQ_SDMA1 OMAP44XX_HARDIRQ(13) /* System DMA request 1(3) */ 384 #define OMAP44XX_IRQ_SDMA2 OMAP44XX_HARDIRQ(14) /* System DMA request 2 */ 385 #define OMAP44XX_IRQ_SDMA3 OMAP44XX_HARDIRQ(15) /* System DMA request 3 */ 386 #define OMAP44XX_IRQ_MCBSP4 OMAP44XX_HARDIRQ(16) /* McBSP module 4 IRQ */ 387 #define OMAP44XX_IRQ_MCBSP1 OMAP44XX_HARDIRQ(17) /* McBSP module 1 IRQ */ 388 #define OMAP44XX_IRQ_SR1 OMAP44XX_HARDIRQ(18) /* SmartReflex™ 1 */ 389 #define OMAP44XX_IRQ_SR2 OMAP44XX_HARDIRQ(19) /* SmartReflex™ 2 */ 390 #define OMAP44XX_IRQ_GPMC OMAP44XX_HARDIRQ(20) /* General-purpose memory controller module */ 391 #define OMAP44XX_IRQ_SGX OMAP44XX_HARDIRQ(21) /* 2D/3D graphics module */ 392 #define OMAP44XX_IRQ_MCBSP2 OMAP44XX_HARDIRQ(22) /* McBSP module 2 */ 393 #define OMAP44XX_IRQ_MCBSP3 OMAP44XX_HARDIRQ(23) /* McBSP module 3 */ 394 #define OMAP44XX_IRQ_ISS5 OMAP44XX_HARDIRQ(24) /* Imaging subsystem interrupt 5 */ 395 #define OMAP44XX_IRQ_DSS OMAP44XX_HARDIRQ(25) /* Display subsystem module(3) */ 396 #define OMAP44XX_IRQ_MAIL_U0 OMAP44XX_HARDIRQ(26) /* Mailbox user 0 request */ 397 #define OMAP44XX_IRQ_C2C_SSCM OMAP44XX_HARDIRQ(27) /* C2C status interrupt */ 398 #define OMAP44XX_IRQ_DSP_MMU OMAP44XX_HARDIRQ(28) /* DSP MMU */ 399 #define OMAP44XX_IRQ_GPIO1_MPU OMAP44XX_HARDIRQ(29) /* GPIO module 1(3) */ 400 #define OMAP44XX_IRQ_GPIO2_MPU OMAP44XX_HARDIRQ(30) /* GPIO module 2(3) */ 401 #define OMAP44XX_IRQ_GPIO3_MPU OMAP44XX_HARDIRQ(31) /* GPIO module 3(3) */ 402 #define OMAP44XX_IRQ_GPIO4_MPU OMAP44XX_HARDIRQ(32) /* GPIO module 4(3) */ 403 #define OMAP44XX_IRQ_GPIO5_MPU OMAP44XX_HARDIRQ(33) /* GPIO module 5(3) */ 404 #define OMAP44XX_IRQ_GPIO6_MPU OMAP44XX_HARDIRQ(34) /* GPIO module 6(3) */ 405 #define OMAP44XX_IRQ_RESERVED35 OMAP44XX_HARDIRQ(35) /* RESERVED */ 406 #define OMAP44XX_IRQ_WDT3 OMAP44XX_HARDIRQ(36) /* Watchdog timer module 3 overflow */ 407 #define OMAP44XX_IRQ_GPT1 OMAP44XX_HARDIRQ(37) /* General-purpose timer module 1 */ 408 #define OMAP44XX_IRQ_GPT2 OMAP44XX_HARDIRQ(38) /* General-purpose timer module 2 */ 409 #define OMAP44XX_IRQ_GPT3 OMAP44XX_HARDIRQ(39) /* General-purpose timer module 3 */ 410 #define OMAP44XX_IRQ_GPT4 OMAP44XX_HARDIRQ(40) /* General-purpose timer module 4 */ 411 #define OMAP44XX_IRQ_GPT5 OMAP44XX_HARDIRQ(41) /* General-purpose timer module 5 */ 412 #define OMAP44XX_IRQ_GPT6 OMAP44XX_HARDIRQ(42) /* General-purpose timer module 6 */ 413 #define OMAP44XX_IRQ_GPT7 OMAP44XX_HARDIRQ(43) /* General-purpose timer module 7 */ 414 #define OMAP44XX_IRQ_GPT8 OMAP44XX_HARDIRQ(44) /* General-purpose timer module 8 */ 415 #define OMAP44XX_IRQ_GPT9 OMAP44XX_HARDIRQ(45) /* General-purpose timer module 9 */ 416 #define OMAP44XX_IRQ_GPT10 OMAP44XX_HARDIRQ(46) /* General-purpose timer module 10 */ 417 #define OMAP44XX_IRQ_GPT11 OMAP44XX_HARDIRQ(47) /* General-purpose timer module 11 */ 418 #define OMAP44XX_IRQ_MCSPI4 OMAP44XX_HARDIRQ(48) /* McSPI module 4 */ 419 #define OMAP44XX_IRQ_RESERVED49 OMAP44XX_HARDIRQ(49) /* RESERVED */ 420 #define OMAP44XX_IRQ_RESERVED50 OMAP44XX_HARDIRQ(50) /* RESERVED */ 421 #define OMAP44XX_IRQ_RESERVED51 OMAP44XX_HARDIRQ(51) /* RESERVED */ 422 #define OMAP44XX_IRQ_RESERVED52 OMAP44XX_HARDIRQ(52) /* RESERVED */ 423 #define OMAP44XX_IRQ_DSS_DSI1 OMAP44XX_HARDIRQ(53) /* Display Subsystem DSI1 interrupt */ 424 #define OMAP44XX_IRQ_RESERVED54 OMAP44XX_HARDIRQ(54) /* RESERVED */ 425 #define OMAP44XX_IRQ_RESERVED55 OMAP44XX_HARDIRQ(55) /* RESERVED */ 426 #define OMAP44XX_IRQ_I2C1 OMAP44XX_HARDIRQ(56) /* I2C module 1 */ 427 #define OMAP44XX_IRQ_I2C2 OMAP44XX_HARDIRQ(57) /* I2C module 2 */ 428 #define OMAP44XX_IRQ_HDQ OMAP44XX_HARDIRQ(58) /* HDQ / One-wire */ 429 #define OMAP44XX_IRQ_MMC5 OMAP44XX_HARDIRQ(59) /* MMC5 interrupt */ 430 #define OMAP44XX_IRQ_RESERVED60 OMAP44XX_HARDIRQ(60) /* RESERVED */ 431 #define OMAP44XX_IRQ_I2C3 OMAP44XX_HARDIRQ(61) /* I2C module 3 */ 432 #define OMAP44XX_IRQ_I2C4 OMAP44XX_HARDIRQ(62) /* I2C module 4 */ 433 #define OMAP44XX_IRQ_RESERVED63 OMAP44XX_HARDIRQ(63) /* RESERVED */ 434 #define OMAP44XX_IRQ_RESERVED64 OMAP44XX_HARDIRQ(64) /* RESERVED */ 435 #define OMAP44XX_IRQ_MCSPI1 OMAP44XX_HARDIRQ(65) /* McSPI module 1 */ 436 #define OMAP44XX_IRQ_MCSPI2 OMAP44XX_HARDIRQ(66) /* McSPI module 2 */ 437 #define OMAP44XX_IRQ_HSI_P1 OMAP44XX_HARDIRQ(67) /* HSI Port 1 interrupt */ 438 #define OMAP44XX_IRQ_HSI_P2 OMAP44XX_HARDIRQ(68) /* HSI Port 2 interrupt */ 439 #define OMAP44XX_IRQ_FDIF_3 OMAP44XX_HARDIRQ(69) /* Face detect interrupt 3 */ 440 #define OMAP44XX_IRQ_UART4 OMAP44XX_HARDIRQ(70) /* UART module 4 interrupt */ 441 #define OMAP44XX_IRQ_HSI_DMA OMAP44XX_HARDIRQ(71) /* HSI DMA engine MPU request */ 442 #define OMAP44XX_IRQ_UART1 OMAP44XX_HARDIRQ(72) /* UART module 1 */ 443 #define OMAP44XX_IRQ_UART2 OMAP44XX_HARDIRQ(73) /* UART module 2 */ 444 #define OMAP44XX_IRQ_UART3 OMAP44XX_HARDIRQ(74) /* UART module 3 (also infrared)(3) */ 445 #define OMAP44XX_IRQ_PBIAS OMAP44XX_HARDIRQ(75) /* Merged interrupt for PBIASlite1 and 2 */ 446 #define OMAP44XX_IRQ_OHCI OMAP44XX_HARDIRQ(76) /* OHCI controller HSUSB MP Host Interrupt */ 447 #define OMAP44XX_IRQ_EHCI OMAP44XX_HARDIRQ(77) /* EHCI controller HSUSB MP Host Interrupt */ 448 #define OMAP44XX_IRQ_TLL OMAP44XX_HARDIRQ(78) /* HSUSB MP TLL Interrupt */ 449 #define OMAP44XX_IRQ_RESERVED79 OMAP44XX_HARDIRQ(79) /* RESERVED */ 450 #define OMAP44XX_IRQ_WDT2 OMAP44XX_HARDIRQ(80) /* WDTIMER2 interrupt */ 451 #define OMAP44XX_IRQ_RESERVED81 OMAP44XX_HARDIRQ(81) /* RESERVED */ 452 #define OMAP44XX_IRQ_RESERVED82 OMAP44XX_HARDIRQ(82) /* RESERVED */ 453 #define OMAP44XX_IRQ_MMC1 OMAP44XX_HARDIRQ(83) /* MMC/SD module 1 */ 454 #define OMAP44XX_IRQ_DSS_DSI2 OMAP44XX_HARDIRQ(84) /* Display subsystem DSI2 interrupt */ 455 #define OMAP44XX_IRQ_RESERVED85 OMAP44XX_HARDIRQ(85) /* Reserved */ 456 #define OMAP44XX_IRQ_MMC2 OMAP44XX_HARDIRQ(86) /* MMC/SD module 2 */ 457 #define OMAP44XX_IRQ_MPU_ICR OMAP44XX_HARDIRQ(87) /* MPU ICR */ 458 #define OMAP44XX_IRQ_C2C_GPI OMAP44XX_HARDIRQ(88) /* C2C GPI interrupt */ 459 #define OMAP44XX_IRQ_FSUSB OMAP44XX_HARDIRQ(89) /* FS-USB - host controller Interrupt */ 460 #define OMAP44XX_IRQ_FSUSB_SMI OMAP44XX_HARDIRQ(90) /* FS-USB - host controller SMI Interrupt */ 461 #define OMAP44XX_IRQ_MCSPI3 OMAP44XX_HARDIRQ(91) /* McSPI module 3 */ 462 #define OMAP44XX_IRQ_HSUSB_OTG OMAP44XX_HARDIRQ(92) /* High-Speed USB OTG controller */ 463 #define OMAP44XX_IRQ_HSUSB_OTG_DMA OMAP44XX_HARDIRQ(93) /* High-Speed USB OTG DMA controller */ 464 #define OMAP44XX_IRQ_MMC3 OMAP44XX_HARDIRQ(94) /* MMC/SD module 3 */ 465 #define OMAP44XX_IRQ_RESERVED95 OMAP44XX_HARDIRQ(95) /* RESERVED */ 466 #define OMAP44XX_IRQ_MMC4 OMAP44XX_HARDIRQ(96) /* MMC4 interrupt */ 467 #define OMAP44XX_IRQ_SLIMBUS1 OMAP44XX_HARDIRQ(97) /* SLIMBUS1 interrupt */ 468 #define OMAP44XX_IRQ_SLIMBUS2 OMAP44XX_HARDIRQ(98) /* SLIMBUS2 interrupt */ 469 #define OMAP44XX_IRQ_ABE OMAP44XX_HARDIRQ(99) /* Audio back-end interrupt */ 470 #define OMAP44XX_IRQ_CORTEXM3_MMU OMAP44XX_HARDIRQ(100) /* Cortex-M3 MMU interrupt */ 471 #define OMAP44XX_IRQ_DSS_HDMI OMAP44XX_HARDIRQ(101) /* Display subsystem HDMI interrupt */ 472 #define OMAP44XX_IRQ_SR_IVA OMAP44XX_HARDIRQ(102) /* SmartReflex IVA interrupt */ 473 #define OMAP44XX_IRQ_IVAHD1 OMAP44XX_HARDIRQ(103) /* Sync interrupt from iCONT2 (vDMA) */ 474 #define OMAP44XX_IRQ_IVAHD2 OMAP44XX_HARDIRQ(104) /* Sync interrupt from iCONT1 */ 475 #define OMAP44XX_IRQ_RESERVED105 OMAP44XX_HARDIRQ(105) /* RESERVED */ 476 #define OMAP44XX_IRQ_RESERVED106 OMAP44XX_HARDIRQ(106) /* RESERVED */ 477 #define OMAP44XX_IRQ_IVAHD_MAILBOX0 OMAP44XX_HARDIRQ(107) /* IVAHD mailbox interrupt */ 478 #define OMAP44XX_IRQ_RESERVED108 OMAP44XX_HARDIRQ(108) /* RESERVED */ 479 #define OMAP44XX_IRQ_MCASP1 OMAP44XX_HARDIRQ(109) /* McASP1 transmit interrupt */ 480 #define OMAP44XX_IRQ_EMIF1 OMAP44XX_HARDIRQ(110) /* EMIF1 interrupt */ 481 #define OMAP44XX_IRQ_EMIF2 OMAP44XX_HARDIRQ(111) /* EMIF2 interrupt */ 482 #define OMAP44XX_IRQ_MCPDM OMAP44XX_HARDIRQ(112) /* MCPDM interrupt */ 483 #define OMAP44XX_IRQ_DMM OMAP44XX_HARDIRQ(113) /* DMM interrupt */ 484 #define OMAP44XX_IRQ_DMIC OMAP44XX_HARDIRQ(114) /* DMIC interrupt */ 485 #define OMAP44XX_IRQ_RESERVED115 OMAP44XX_HARDIRQ(115) /* RESERVED */ 486 #define OMAP44XX_IRQ_RESERVED116 OMAP44XX_HARDIRQ(116) /* RESERVED */ 487 #define OMAP44XX_IRQ_RESERVED117 OMAP44XX_HARDIRQ(117) /* RESERVED */ 488 #define OMAP44XX_IRQ_RESERVED118 OMAP44XX_HARDIRQ(118) /* RESERVED */ 489 #define OMAP44XX_IRQ_SYS_NIRQ2 OMAP44XX_HARDIRQ(119) /* External source 2 (active low) */ 490 #define OMAP44XX_IRQ_KBD OMAP44XX_HARDIRQ(120) /* Keyboard controller interrupt */ 491 #define OMAP44XX_IRQ_RESERVED121 OMAP44XX_HARDIRQ(121) /* RESERVED */ 492 #define OMAP44XX_IRQ_RESERVED122 OMAP44XX_HARDIRQ(122) /* RESERVED */ 493 #define OMAP44XX_IRQ_RESERVED123 OMAP44XX_HARDIRQ(123) /* RESERVED */ 494 #define OMAP44XX_IRQ_RESERVED124 OMAP44XX_HARDIRQ(124) /* RESERVED */ 495 #define OMAP44XX_IRQ_RESERVED125 OMAP44XX_HARDIRQ(125) /* RESERVED */ 496 #define OMAP44XX_IRQ_RESERVED126 OMAP44XX_HARDIRQ(126) /* RESERVED */ 497 #define OMAP44XX_IRQ_RESERVED127 OMAP44XX_HARDIRQ(127) /* RESERVED */ 498 499 500 501 /* 502 * General Purpose Timers 503 */ 504 #define OMAP44XX_GPTIMER1_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_GPTIMER1_OFFSET) 505 #define OMAP44XX_GPTIMER1_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_GPTIMER1_OFFSET) 506 #define OMAP44XX_GPTIMER2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER2_OFFSET) 507 #define OMAP44XX_GPTIMER2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER2_OFFSET) 508 #define OMAP44XX_GPTIMER3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER3_OFFSET) 509 #define OMAP44XX_GPTIMER3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER3_OFFSET) 510 #define OMAP44XX_GPTIMER4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER4_OFFSET) 511 #define OMAP44XX_GPTIMER4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER4_OFFSET) 512 #define OMAP44XX_GPTIMER5_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER5_OFFSET) 513 #define OMAP44XX_GPTIMER5_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER5_OFFSET) 514 #define OMAP44XX_GPTIMER6_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER6_OFFSET) 515 #define OMAP44XX_GPTIMER6_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER6_OFFSET) 516 #define OMAP44XX_GPTIMER7_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER7_OFFSET) 517 #define OMAP44XX_GPTIMER7_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER7_OFFSET) 518 #define OMAP44XX_GPTIMER8_VBASE (OMAP44XX_L4_ABE_VBASE + OMAP44XX_GPTIMER8_OFFSET) 519 #define OMAP44XX_GPTIMER8_HWBASE (OMAP44XX_L4_ABE_HWBASE + OMAP44XX_GPTIMER8_OFFSET) 520 #define OMAP44XX_GPTIMER9_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER9_OFFSET) 521 #define OMAP44XX_GPTIMER9_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER9_OFFSET) 522 #define OMAP44XX_GPTIMER10_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER10_OFFSET) 523 #define OMAP44XX_GPTIMER10_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER10_OFFSET) 524 #define OMAP44XX_GPTIMER11_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPTIMER11_OFFSET) 525 #define OMAP44XX_GPTIMER11_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPTIMER11_OFFSET) 526 #define OMAP44XX_GPTIMER_SIZE 0x00001000UL 527 528 529 530 /* 531 * GPIO - General Purpose IO 532 */ 533 534 /* Base addresses for the GPIO modules */ 535 #define OMAP44XX_GPIO1_HWBASE (OMAP44XX_L4_WAKEUP_HWBASE + OMAP44XX_GPIO1_OFFSET) 536 #define OMAP44XX_GPIO1_VBASE (OMAP44XX_L4_WAKEUP_VBASE + OMAP44XX_GPIO1_OFFSET) 537 #define OMAP44XX_GPIO1_SIZE 0x00001000UL 538 #define OMAP44XX_GPIO2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO2_OFFSET) 539 #define OMAP44XX_GPIO2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO2_OFFSET) 540 #define OMAP44XX_GPIO2_SIZE 0x00001000UL 541 #define OMAP44XX_GPIO3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO3_OFFSET) 542 #define OMAP44XX_GPIO3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO3_OFFSET) 543 #define OMAP44XX_GPIO3_SIZE 0x00001000UL 544 #define OMAP44XX_GPIO4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO4_OFFSET) 545 #define OMAP44XX_GPIO4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO4_OFFSET) 546 #define OMAP44XX_GPIO4_SIZE 0x00001000UL 547 #define OMAP44XX_GPIO5_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO5_OFFSET) 548 #define OMAP44XX_GPIO5_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO5_OFFSET) 549 #define OMAP44XX_GPIO5_SIZE 0x00001000UL 550 #define OMAP44XX_GPIO6_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_GPIO6_OFFSET) 551 #define OMAP44XX_GPIO6_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_GPIO6_OFFSET) 552 #define OMAP44XX_GPIO6_SIZE 0x00001000UL 553 554 555 /* 556 * MMC/SD/SDIO 557 */ 558 559 /* Base addresses for the MMC/SD/SDIO modules */ 560 #define OMAP44XX_MMCHS1_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCHS1_OFFSET) 561 #define OMAP44XX_MMCHS1_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCHS1_OFFSET) 562 #define OMAP44XX_MMCHS2_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCHS2_OFFSET) 563 #define OMAP44XX_MMCHS2_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCHS2_OFFSET) 564 #define OMAP44XX_MMCHS3_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCSD3_OFFSET) 565 #define OMAP44XX_MMCHS3_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCSD3_OFFSET) 566 #define OMAP44XX_MMCHS4_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCSD4_OFFSET) 567 #define OMAP44XX_MMCHS4_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCSD4_OFFSET) 568 #define OMAP44XX_MMCHS5_HWBASE (OMAP44XX_L4_PERIPH_HWBASE + OMAP44XX_MMCSD5_OFFSET) 569 #define OMAP44XX_MMCHS5_VBASE (OMAP44XX_L4_PERIPH_VBASE + OMAP44XX_MMCSD5_OFFSET) 570 #define OMAP44XX_MMCHS_SIZE 0x00001000UL 571 572 573 574 /* 575 * SCM - System Control Module 576 */ 577 578 /* Base addresses for the SC modules */ 579 #define OMAP44XX_SCM_PADCONF_HWBASE (OMAP44XX_L4_CORE_HWBASE + OMAP44XX_SCM_PADCONF_OFFSET) 580 #define OMAP44XX_SCM_PADCONF_VBASE (OMAP44XX_L4_CORE_VBASE + OMAP44XX_SCM_PADCONF_OFFSET) 581 #define OMAP44XX_SCM_PADCONF_SIZE 0x00001000UL 582 583 584 585 586 #endif /* _OMAP44XX_REG_H_ */ 587