1 /*- 2 * Copyright (c) 2011 3 * Ben Gray <ben.r.gray@gmail.com>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the company nor the name of the author may be used to 15 * endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 23 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 24 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 25 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 26 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 27 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/intr.h> 46 47 #include <arm/arm/mpcore_timervar.h> 48 #include <arm/ti/tivar.h> 49 #include <arm/ti/ti_prcm.h> 50 #include <arm/ti/omap4/omap4_reg.h> 51 52 #include <dev/ofw/openfirm.h> 53 #include <dev/ofw/ofw_bus.h> 54 #include <dev/ofw/ofw_bus_subr.h> 55 56 /* 57 * This file defines the clock configuration for the OMAP4xxx series of 58 * devices. 59 * 60 * How This is Suppose to Work 61 * =========================== 62 * - There is a top level omap_prcm module that defines all OMAP SoC drivers 63 * should use to enable/disable the system clocks regardless of the version 64 * of OMAP device they are running on. This top level PRCM module is just 65 * a thin shim to chip specific functions that perform the donkey work of 66 * configuring the clock - this file is the 'donkey' for OMAP44xx devices. 67 * 68 * - The key bit in this file is the omap_clk_devmap array, it's 69 * used by the omap_prcm driver to determine what clocks are valid and which 70 * functions to call to manipulate them. 71 * 72 * - In essence you just need to define some callbacks for each of the 73 * clocks and then you're done. 74 * 75 * - The other thing that is worth noting is that when the omap_prcm device 76 * is registered you typically pass in some memory ranges which are the 77 * SYS_MEMORY resources. These resources are in turn allocated using 78 * bus_allocate_resources(...) and the resource handles are passed to all 79 * individual clock callback handlers. 80 * 81 * 82 * 83 * OMAP4 devices are different from the previous OMAP3 devices in that there 84 * is no longer a separate functional and interface clock for each module, 85 * instead there is typically an interface clock that spans many modules. 86 */ 87 88 #define FREQ_96MHZ 96000000 89 #define FREQ_64MHZ 64000000 90 #define FREQ_48MHZ 48000000 91 #define FREQ_32KHZ 32000 92 93 #define PRM_INSTANCE 1 94 #define CM1_INSTANCE 2 95 #define CM2_INSTANCE 3 96 97 /** 98 * Address offsets from the PRM memory region to the top level clock control 99 * registers. 100 */ 101 #define CKGEN_PRM_OFFSET 0x00000100UL 102 #define MPU_PRM_OFFSET 0x00000300UL 103 #define DSP_PRM_OFFSET 0x00000400UL 104 #define ABE_PRM_OFFSET 0x00000500UL 105 #define ALWAYS_ON_PRM_OFFSET 0x00000600UL 106 #define CORE_PRM_OFFSET 0x00000700UL 107 #define IVAHD_PRM_OFFSET 0x00000F00UL 108 #define CAM_PRM_OFFSET 0x00001000UL 109 #define DSS_PRM_OFFSET 0x00001100UL 110 #define SGX_PRM_OFFSET 0x00001200UL 111 #define L3INIT_PRM_OFFSET 0x00001300UL 112 #define L4PER_PRM_OFFSET 0x00001400UL 113 #define WKUP_PRM_OFFSET 0x00001700UL 114 #define WKUP_CM_OFFSET 0x00001800UL 115 #define EMU_PRM_OFFSET 0x00001900UL 116 #define EMU_CM_OFFSET 0x00001A00UL 117 #define DEVICE_PRM_OFFSET 0x00001B00UL 118 #define INSTR_PRM_OFFSET 0x00001F00UL 119 120 #define CM_ABE_DSS_SYS_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x0000UL) 121 #define CM_L4_WKUP_CLKSELL_OFFSET (CKGEN_PRM_OFFSET + 0x0008UL) 122 #define CM_ABE_PLL_REF_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x000CUL) 123 #define CM_SYS_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x0010UL) 124 125 /** 126 * Address offsets from the CM1 memory region to the top level clock control 127 * registers. 128 */ 129 #define CKGEN_CM1_OFFSET 0x00000100UL 130 #define MPU_CM1_OFFSET 0x00000300UL 131 #define DSP_CM1_OFFSET 0x00000400UL 132 #define ABE_CM1_OFFSET 0x00000500UL 133 #define RESTORE_CM1_OFFSET 0x00000E00UL 134 #define INSTR_CM1_OFFSET 0x00000F00UL 135 136 #define CM_CLKSEL_DPLL_MPU (CKGEN_CM1_OFFSET + 0x006CUL) 137 138 /** 139 * Address offsets from the CM2 memory region to the top level clock control 140 * registers. 141 */ 142 #define INTRCONN_SOCKET_CM2_OFFSET 0x00000000UL 143 #define CKGEN_CM2_OFFSET 0x00000100UL 144 #define ALWAYS_ON_CM2_OFFSET 0x00000600UL 145 #define CORE_CM2_OFFSET 0x00000700UL 146 #define IVAHD_CM2_OFFSET 0x00000F00UL 147 #define CAM_CM2_OFFSET 0x00001000UL 148 #define DSS_CM2_OFFSET 0x00001100UL 149 #define SGX_CM2_OFFSET 0x00001200UL 150 #define L3INIT_CM2_OFFSET 0x00001300UL 151 #define L4PER_CM2_OFFSET 0x00001400UL 152 #define RESTORE_CM2_OFFSET 0x00001E00UL 153 #define INSTR_CM2_OFFSET 0x00001F00UL 154 155 #define CLKCTRL_MODULEMODE_MASK 0x00000003UL 156 #define CLKCTRL_MODULEMODE_DISABLE 0x00000000UL 157 #define CLKCTRL_MODULEMODE_AUTO 0x00000001UL 158 #define CLKCTRL_MODULEMODE_ENABLE 0x00000001UL 159 160 #define CLKCTRL_IDLEST_MASK 0x00030000UL 161 #define CLKCTRL_IDLEST_ENABLED 0x00000000UL 162 #define CLKCTRL_IDLEST_WAKING 0x00010000UL 163 #define CLKCTRL_IDLEST_IDLE 0x00020000UL 164 #define CLKCTRL_IDLEST_DISABLED 0x00030000UL 165 166 static struct ofw_compat_data compat_data[] = { 167 {"ti,omap4-cm1", (uintptr_t)CM1_INSTANCE}, 168 {"ti,omap4-cm2", (uintptr_t)CM2_INSTANCE}, 169 {"ti,omap4-prm", (uintptr_t)PRM_INSTANCE}, 170 {NULL, (uintptr_t)0}, 171 }; 172 173 struct omap4_prcm_softc { 174 struct resource *sc_res; 175 int sc_rid; 176 int sc_instance; 177 }; 178 179 static int omap4_clk_generic_activate(struct ti_clock_dev *clkdev); 180 static int omap4_clk_generic_deactivate(struct ti_clock_dev *clkdev); 181 static int omap4_clk_generic_accessible(struct ti_clock_dev *clkdev); 182 static int omap4_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 183 static int omap4_clk_generic_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 184 185 static int omap4_clk_gptimer_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 186 static int omap4_clk_gptimer_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 187 188 static int omap4_clk_hsmmc_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 189 static int omap4_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 190 191 static int omap4_clk_hsusbhost_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 192 static int omap4_clk_hsusbhost_activate(struct ti_clock_dev *clkdev); 193 static int omap4_clk_hsusbhost_deactivate(struct ti_clock_dev *clkdev); 194 static int omap4_clk_hsusbhost_accessible(struct ti_clock_dev *clkdev); 195 196 static int omap4_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 197 static int omap4_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 198 199 /** 200 * omap_clk_devmap - Array of clock devices available on OMAP4xxx devices 201 * 202 * This map only defines which clocks are valid and the callback functions 203 * for clock activate, deactivate, etc. It is used by the top level omap_prcm 204 * driver. 205 * 206 * The actual details of the clocks (config registers, bit fields, sources, 207 * etc) are in the private g_omap3_clk_details array below. 208 * 209 */ 210 211 #define OMAP4_GENERIC_CLOCK_DEV(i) \ 212 { .id = (i), \ 213 .clk_activate = omap4_clk_generic_activate, \ 214 .clk_deactivate = omap4_clk_generic_deactivate, \ 215 .clk_set_source = omap4_clk_generic_set_source, \ 216 .clk_accessible = omap4_clk_generic_accessible, \ 217 .clk_get_source_freq = omap4_clk_generic_get_source_freq, \ 218 .clk_set_source_freq = NULL \ 219 } 220 221 #define OMAP4_GPTIMER_CLOCK_DEV(i) \ 222 { .id = (i), \ 223 .clk_activate = omap4_clk_generic_activate, \ 224 .clk_deactivate = omap4_clk_generic_deactivate, \ 225 .clk_set_source = omap4_clk_gptimer_set_source, \ 226 .clk_accessible = omap4_clk_generic_accessible, \ 227 .clk_get_source_freq = omap4_clk_gptimer_get_source_freq, \ 228 .clk_set_source_freq = NULL \ 229 } 230 231 #define OMAP4_HSMMC_CLOCK_DEV(i) \ 232 { .id = (i), \ 233 .clk_activate = omap4_clk_generic_activate, \ 234 .clk_deactivate = omap4_clk_generic_deactivate, \ 235 .clk_set_source = omap4_clk_hsmmc_set_source, \ 236 .clk_accessible = omap4_clk_generic_accessible, \ 237 .clk_get_source_freq = omap4_clk_hsmmc_get_source_freq, \ 238 .clk_set_source_freq = NULL \ 239 } 240 241 #define OMAP4_HSUSBHOST_CLOCK_DEV(i) \ 242 { .id = (i), \ 243 .clk_activate = omap4_clk_hsusbhost_activate, \ 244 .clk_deactivate = omap4_clk_hsusbhost_deactivate, \ 245 .clk_set_source = omap4_clk_hsusbhost_set_source, \ 246 .clk_accessible = omap4_clk_hsusbhost_accessible, \ 247 .clk_get_source_freq = NULL, \ 248 .clk_set_source_freq = NULL \ 249 } 250 251 252 struct ti_clock_dev ti_omap4_clk_devmap[] = { 253 254 /* System clocks */ 255 { .id = SYS_CLK, 256 .clk_activate = NULL, 257 .clk_deactivate = NULL, 258 .clk_set_source = NULL, 259 .clk_accessible = NULL, 260 .clk_get_source_freq = omap4_clk_get_sysclk_freq, 261 .clk_set_source_freq = NULL, 262 }, 263 /* MPU (ARM) core clocks */ 264 { .id = MPU_CLK, 265 .clk_activate = NULL, 266 .clk_deactivate = NULL, 267 .clk_set_source = NULL, 268 .clk_accessible = NULL, 269 .clk_get_source_freq = omap4_clk_get_arm_fclk_freq, 270 .clk_set_source_freq = NULL, 271 }, 272 273 274 /* UART device clocks */ 275 OMAP4_GENERIC_CLOCK_DEV(UART1_CLK), 276 OMAP4_GENERIC_CLOCK_DEV(UART2_CLK), 277 OMAP4_GENERIC_CLOCK_DEV(UART3_CLK), 278 OMAP4_GENERIC_CLOCK_DEV(UART4_CLK), 279 280 /* Timer device source clocks */ 281 OMAP4_GPTIMER_CLOCK_DEV(TIMER1_CLK), 282 OMAP4_GPTIMER_CLOCK_DEV(TIMER2_CLK), 283 OMAP4_GPTIMER_CLOCK_DEV(TIMER3_CLK), 284 OMAP4_GPTIMER_CLOCK_DEV(TIMER4_CLK), 285 OMAP4_GPTIMER_CLOCK_DEV(TIMER5_CLK), 286 OMAP4_GPTIMER_CLOCK_DEV(TIMER6_CLK), 287 OMAP4_GPTIMER_CLOCK_DEV(TIMER7_CLK), 288 OMAP4_GPTIMER_CLOCK_DEV(TIMER8_CLK), 289 OMAP4_GPTIMER_CLOCK_DEV(TIMER9_CLK), 290 OMAP4_GPTIMER_CLOCK_DEV(TIMER10_CLK), 291 OMAP4_GPTIMER_CLOCK_DEV(TIMER11_CLK), 292 293 /* MMC device clocks (MMC1 and MMC2 can have different input clocks) */ 294 OMAP4_HSMMC_CLOCK_DEV(MMC1_CLK), 295 OMAP4_HSMMC_CLOCK_DEV(MMC2_CLK), 296 OMAP4_GENERIC_CLOCK_DEV(MMC3_CLK), 297 OMAP4_GENERIC_CLOCK_DEV(MMC4_CLK), 298 OMAP4_GENERIC_CLOCK_DEV(MMC5_CLK), 299 300 /* USB HS (high speed TLL, EHCI and OHCI) */ 301 OMAP4_HSUSBHOST_CLOCK_DEV(USBTLL_CLK), 302 OMAP4_HSUSBHOST_CLOCK_DEV(USBHSHOST_CLK), 303 OMAP4_HSUSBHOST_CLOCK_DEV(USBFSHOST_CLK), 304 OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_PHY_CLK), 305 OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_PHY_CLK), 306 OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_UTMI_CLK), 307 OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_UTMI_CLK), 308 OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_HSIC_CLK), 309 OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_HSIC_CLK), 310 311 /* GPIO */ 312 OMAP4_GENERIC_CLOCK_DEV(GPIO1_CLK), 313 OMAP4_GENERIC_CLOCK_DEV(GPIO2_CLK), 314 OMAP4_GENERIC_CLOCK_DEV(GPIO3_CLK), 315 OMAP4_GENERIC_CLOCK_DEV(GPIO4_CLK), 316 OMAP4_GENERIC_CLOCK_DEV(GPIO5_CLK), 317 OMAP4_GENERIC_CLOCK_DEV(GPIO6_CLK), 318 319 /* sDMA */ 320 OMAP4_GENERIC_CLOCK_DEV(SDMA_CLK), 321 322 /* I2C */ 323 OMAP4_GENERIC_CLOCK_DEV(I2C1_CLK), 324 OMAP4_GENERIC_CLOCK_DEV(I2C2_CLK), 325 OMAP4_GENERIC_CLOCK_DEV(I2C3_CLK), 326 OMAP4_GENERIC_CLOCK_DEV(I2C4_CLK), 327 328 { INVALID_CLK_IDENT, NULL, NULL, NULL, NULL } 329 }; 330 331 /** 332 * omap4_clk_details - Stores details for all the different clocks supported 333 * 334 * Whenever an operation on a clock is being performed (activated, deactivated, 335 * etc) this array is looked up to find the correct register and bit(s) we 336 * should be modifying. 337 * 338 */ 339 struct omap4_clk_details { 340 clk_ident_t id; 341 342 uint32_t instance; 343 uint32_t clksel_reg; 344 345 int32_t src_freq; 346 347 uint32_t enable_mode; 348 }; 349 350 #define OMAP4_GENERIC_CLOCK_DETAILS(i, f, di, r, e) \ 351 { .id = (i), \ 352 .instance = (di), \ 353 .clksel_reg = (r), \ 354 .src_freq = (f), \ 355 .enable_mode = (e), \ 356 } 357 358 static struct omap4_clk_details g_omap4_clk_details[] = { 359 360 /* UART */ 361 OMAP4_GENERIC_CLOCK_DETAILS(UART1_CLK, FREQ_48MHZ, CM2_INSTANCE, 362 (L4PER_CM2_OFFSET + 0x0140), CLKCTRL_MODULEMODE_ENABLE), 363 OMAP4_GENERIC_CLOCK_DETAILS(UART2_CLK, FREQ_48MHZ, CM2_INSTANCE, 364 (L4PER_CM2_OFFSET + 0x0148), CLKCTRL_MODULEMODE_ENABLE), 365 OMAP4_GENERIC_CLOCK_DETAILS(UART3_CLK, FREQ_48MHZ, CM2_INSTANCE, 366 (L4PER_CM2_OFFSET + 0x0150), CLKCTRL_MODULEMODE_ENABLE), 367 OMAP4_GENERIC_CLOCK_DETAILS(UART4_CLK, FREQ_48MHZ, CM2_INSTANCE, 368 (L4PER_CM2_OFFSET + 0x0158), CLKCTRL_MODULEMODE_ENABLE), 369 370 /* General purpose timers */ 371 OMAP4_GENERIC_CLOCK_DETAILS(TIMER1_CLK, -1, PRM_INSTANCE, 372 (WKUP_CM_OFFSET + 0x040), CLKCTRL_MODULEMODE_ENABLE), 373 OMAP4_GENERIC_CLOCK_DETAILS(TIMER2_CLK, -1, CM2_INSTANCE, 374 (L4PER_CM2_OFFSET + 0x038), CLKCTRL_MODULEMODE_ENABLE), 375 OMAP4_GENERIC_CLOCK_DETAILS(TIMER3_CLK, -1, CM2_INSTANCE, 376 (L4PER_CM2_OFFSET + 0x040), CLKCTRL_MODULEMODE_ENABLE), 377 OMAP4_GENERIC_CLOCK_DETAILS(TIMER4_CLK, -1, CM2_INSTANCE, 378 (L4PER_CM2_OFFSET + 0x048), CLKCTRL_MODULEMODE_ENABLE), 379 OMAP4_GENERIC_CLOCK_DETAILS(TIMER5_CLK, -1, CM1_INSTANCE, 380 (ABE_CM1_OFFSET + 0x068), CLKCTRL_MODULEMODE_ENABLE), 381 OMAP4_GENERIC_CLOCK_DETAILS(TIMER6_CLK, -1, CM1_INSTANCE, 382 (ABE_CM1_OFFSET + 0x070), CLKCTRL_MODULEMODE_ENABLE), 383 OMAP4_GENERIC_CLOCK_DETAILS(TIMER7_CLK, -1, CM1_INSTANCE, 384 (ABE_CM1_OFFSET + 0x078), CLKCTRL_MODULEMODE_ENABLE), 385 OMAP4_GENERIC_CLOCK_DETAILS(TIMER8_CLK, -1, CM1_INSTANCE, 386 (ABE_CM1_OFFSET + 0x080), CLKCTRL_MODULEMODE_ENABLE), 387 OMAP4_GENERIC_CLOCK_DETAILS(TIMER9_CLK, -1, CM2_INSTANCE, 388 (L4PER_CM2_OFFSET + 0x050), CLKCTRL_MODULEMODE_ENABLE), 389 OMAP4_GENERIC_CLOCK_DETAILS(TIMER10_CLK, -1, CM2_INSTANCE, 390 (L4PER_CM2_OFFSET + 0x028), CLKCTRL_MODULEMODE_ENABLE), 391 OMAP4_GENERIC_CLOCK_DETAILS(TIMER11_CLK, -1, CM2_INSTANCE, 392 (L4PER_CM2_OFFSET + 0x030), CLKCTRL_MODULEMODE_ENABLE), 393 394 /* HSMMC (MMC1 and MMC2 can have different input clocks) */ 395 OMAP4_GENERIC_CLOCK_DETAILS(MMC1_CLK, -1, CM2_INSTANCE, 396 (L3INIT_CM2_OFFSET + 0x028), /*CLKCTRL_MODULEMODE_ENABLE*/2), 397 OMAP4_GENERIC_CLOCK_DETAILS(MMC2_CLK, -1, CM2_INSTANCE, 398 (L3INIT_CM2_OFFSET + 0x030), /*CLKCTRL_MODULEMODE_ENABLE*/2), 399 OMAP4_GENERIC_CLOCK_DETAILS(MMC3_CLK, FREQ_48MHZ, CM2_INSTANCE, 400 (L4PER_CM2_OFFSET + 0x120), /*CLKCTRL_MODULEMODE_ENABLE*/2), 401 OMAP4_GENERIC_CLOCK_DETAILS(MMC4_CLK, FREQ_48MHZ, CM2_INSTANCE, 402 (L4PER_CM2_OFFSET + 0x128), /*CLKCTRL_MODULEMODE_ENABLE*/2), 403 OMAP4_GENERIC_CLOCK_DETAILS(MMC5_CLK, FREQ_48MHZ, CM2_INSTANCE, 404 (L4PER_CM2_OFFSET + 0x160), /*CLKCTRL_MODULEMODE_ENABLE*/1), 405 406 /* GPIO modules */ 407 OMAP4_GENERIC_CLOCK_DETAILS(GPIO1_CLK, -1, PRM_INSTANCE, 408 (WKUP_CM_OFFSET + 0x038), CLKCTRL_MODULEMODE_AUTO), 409 OMAP4_GENERIC_CLOCK_DETAILS(GPIO2_CLK, -1, CM2_INSTANCE, 410 (L4PER_CM2_OFFSET + 0x060), CLKCTRL_MODULEMODE_AUTO), 411 OMAP4_GENERIC_CLOCK_DETAILS(GPIO3_CLK, -1, CM2_INSTANCE, 412 (L4PER_CM2_OFFSET + 0x068), CLKCTRL_MODULEMODE_AUTO), 413 OMAP4_GENERIC_CLOCK_DETAILS(GPIO4_CLK, -1, CM2_INSTANCE, 414 (L4PER_CM2_OFFSET + 0x070), CLKCTRL_MODULEMODE_AUTO), 415 OMAP4_GENERIC_CLOCK_DETAILS(GPIO5_CLK, -1, CM2_INSTANCE, 416 (L4PER_CM2_OFFSET + 0x078), CLKCTRL_MODULEMODE_AUTO), 417 OMAP4_GENERIC_CLOCK_DETAILS(GPIO6_CLK, -1, CM2_INSTANCE, 418 (L4PER_CM2_OFFSET + 0x080), CLKCTRL_MODULEMODE_AUTO), 419 420 /* sDMA block */ 421 OMAP4_GENERIC_CLOCK_DETAILS(SDMA_CLK, -1, CM2_INSTANCE, 422 (CORE_CM2_OFFSET + 0x300), CLKCTRL_MODULEMODE_AUTO), 423 424 /* I2C modules */ 425 OMAP4_GENERIC_CLOCK_DETAILS(I2C1_CLK, -1, CM2_INSTANCE, 426 (L4PER_CM2_OFFSET + 0x0A0), CLKCTRL_MODULEMODE_ENABLE), 427 OMAP4_GENERIC_CLOCK_DETAILS(I2C2_CLK, -1, CM2_INSTANCE, 428 (L4PER_CM2_OFFSET + 0x0A8), CLKCTRL_MODULEMODE_ENABLE), 429 OMAP4_GENERIC_CLOCK_DETAILS(I2C3_CLK, -1, CM2_INSTANCE, 430 (L4PER_CM2_OFFSET + 0x0B0), CLKCTRL_MODULEMODE_ENABLE), 431 OMAP4_GENERIC_CLOCK_DETAILS(I2C4_CLK, -1, CM2_INSTANCE, 432 (L4PER_CM2_OFFSET + 0x0B8), CLKCTRL_MODULEMODE_ENABLE), 433 434 { INVALID_CLK_IDENT, 0, 0, 0, 0 }, 435 }; 436 437 /** 438 * MAX_MODULE_ENABLE_WAIT - the number of loops to wait for the module to come 439 * alive. 440 * 441 */ 442 #define MAX_MODULE_ENABLE_WAIT 100 443 444 /** 445 * ARRAY_SIZE - Macro to return the number of elements in a static const array. 446 * 447 */ 448 #define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 449 450 /** 451 * omap4_clk_details - writes a 32-bit value to one of the timer registers 452 * @timer: Timer device context 453 * @off: The offset of a register from the timer register address range 454 * @val: The value to write into the register 455 * 456 * 457 * RETURNS: 458 * nothing 459 */ 460 static struct omap4_clk_details* 461 omap4_clk_details(clk_ident_t id) 462 { 463 struct omap4_clk_details *walker; 464 465 for (walker = g_omap4_clk_details; walker->id != INVALID_CLK_IDENT; walker++) { 466 if (id == walker->id) 467 return (walker); 468 } 469 470 return NULL; 471 } 472 473 static struct omap4_prcm_softc * 474 omap4_prcm_get_instance_softc(int module_instance) 475 { 476 int i, maxunit; 477 devclass_t prcm_devclass; 478 device_t dev; 479 struct omap4_prcm_softc *sc; 480 481 prcm_devclass = devclass_find("omap4_prcm"); 482 maxunit = devclass_get_maxunit(prcm_devclass); 483 484 for (i = 0; i < maxunit; i++) { 485 dev = devclass_get_device(prcm_devclass, i); 486 sc = device_get_softc(dev); 487 if (sc->sc_instance == module_instance) 488 return (sc); 489 } 490 491 return (NULL); 492 } 493 494 /** 495 * omap4_clk_generic_activate - checks if a module is accessible 496 * @module: identifier for the module to check, see omap3_prcm.h for a list 497 * of possible modules. 498 * Example: OMAP3_MODULE_MMC1 499 * 500 * 501 * 502 * LOCKING: 503 * Inherits the locks from the omap_prcm driver, no internal locking. 504 * 505 * RETURNS: 506 * Returns 0 on success or a positive error code on failure. 507 */ 508 static int 509 omap4_clk_generic_activate(struct ti_clock_dev *clkdev) 510 { 511 struct omap4_prcm_softc *sc; 512 struct omap4_clk_details* clk_details; 513 struct resource* clk_mem_res; 514 uint32_t clksel; 515 unsigned int i; 516 clk_details = omap4_clk_details(clkdev->id); 517 518 if (clk_details == NULL) 519 return (ENXIO); 520 521 sc = omap4_prcm_get_instance_softc(clk_details->instance); 522 if (sc == NULL) 523 return ENXIO; 524 525 clk_mem_res = sc->sc_res; 526 527 if (clk_mem_res == NULL) 528 return (EINVAL); 529 530 /* All the 'generic' clocks have a CLKCTRL register which is more or less 531 * generic - the have at least two fielda called MODULEMODE and IDLEST. 532 */ 533 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 534 clksel &= ~CLKCTRL_MODULEMODE_MASK; 535 clksel |= clk_details->enable_mode; 536 bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); 537 538 /* Now poll on the IDLEST register to tell us if the module has come up. 539 * TODO: We need to take into account the parent clocks. 540 */ 541 542 /* Try MAX_MODULE_ENABLE_WAIT number of times to check if enabled */ 543 for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) { 544 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 545 if ((clksel & CLKCTRL_IDLEST_MASK) == CLKCTRL_IDLEST_ENABLED) 546 break; 547 DELAY(10); 548 } 549 550 /* Check the enabled state */ 551 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) { 552 printf("Error: failed to enable module with clock %d\n", clkdev->id); 553 printf("Error: 0x%08x => 0x%08x\n", clk_details->clksel_reg, clksel); 554 return (ETIMEDOUT); 555 } 556 557 return (0); 558 } 559 560 /** 561 * omap4_clk_generic_deactivate - checks if a module is accessible 562 * @module: identifier for the module to check, see omap3_prcm.h for a list 563 * of possible modules. 564 * Example: OMAP3_MODULE_MMC1 565 * 566 * 567 * 568 * LOCKING: 569 * Inherits the locks from the omap_prcm driver, no internal locking. 570 * 571 * RETURNS: 572 * Returns 0 on success or a positive error code on failure. 573 */ 574 static int 575 omap4_clk_generic_deactivate(struct ti_clock_dev *clkdev) 576 { 577 struct omap4_prcm_softc *sc; 578 struct omap4_clk_details* clk_details; 579 struct resource* clk_mem_res; 580 uint32_t clksel; 581 582 clk_details = omap4_clk_details(clkdev->id); 583 584 if (clk_details == NULL) 585 return (ENXIO); 586 587 sc = omap4_prcm_get_instance_softc(clk_details->instance); 588 if (sc == NULL) 589 return ENXIO; 590 591 clk_mem_res = sc->sc_res; 592 593 if (clk_mem_res == NULL) 594 return (EINVAL); 595 596 /* All the 'generic' clocks have a CLKCTRL register which is more or less 597 * generic - the have at least two fielda called MODULEMODE and IDLEST. 598 */ 599 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 600 clksel &= ~CLKCTRL_MODULEMODE_MASK; 601 clksel |= CLKCTRL_MODULEMODE_DISABLE; 602 bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); 603 604 return (0); 605 } 606 607 /** 608 * omap4_clk_generic_set_source - checks if a module is accessible 609 * @module: identifier for the module to check, see omap3_prcm.h for a list 610 * of possible modules. 611 * Example: OMAP3_MODULE_MMC1 612 * 613 * 614 * 615 * LOCKING: 616 * Inherits the locks from the omap_prcm driver, no internal locking. 617 * 618 * RETURNS: 619 * Returns 0 on success or a positive error code on failure. 620 */ 621 static int 622 omap4_clk_generic_set_source(struct ti_clock_dev *clkdev, 623 clk_src_t clksrc) 624 { 625 626 return (0); 627 } 628 629 /** 630 * omap4_clk_generic_accessible - checks if a module is accessible 631 * @module: identifier for the module to check, see omap3_prcm.h for a list 632 * of possible modules. 633 * Example: OMAP3_MODULE_MMC1 634 * 635 * 636 * 637 * LOCKING: 638 * Inherits the locks from the omap_prcm driver, no internal locking. 639 * 640 * RETURNS: 641 * Returns 0 on success or a negative error code on failure. 642 */ 643 static int 644 omap4_clk_generic_accessible(struct ti_clock_dev *clkdev) 645 { 646 struct omap4_prcm_softc *sc; 647 struct omap4_clk_details* clk_details; 648 struct resource* clk_mem_res; 649 uint32_t clksel; 650 651 clk_details = omap4_clk_details(clkdev->id); 652 653 if (clk_details == NULL) 654 return (ENXIO); 655 656 sc = omap4_prcm_get_instance_softc(clk_details->instance); 657 if (sc == NULL) 658 return ENXIO; 659 660 clk_mem_res = sc->sc_res; 661 662 if (clk_mem_res == NULL) 663 return (EINVAL); 664 665 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 666 667 /* Check the enabled state */ 668 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) 669 return (0); 670 671 return (1); 672 } 673 674 /** 675 * omap4_clk_generic_get_source_freq - checks if a module is accessible 676 * @module: identifier for the module to check, see omap3_prcm.h for a list 677 * of possible modules. 678 * Example: OMAP3_MODULE_MMC1 679 * 680 * 681 * 682 * LOCKING: 683 * Inherits the locks from the omap_prcm driver, no internal locking. 684 * 685 * RETURNS: 686 * Returns 0 on success or a negative error code on failure. 687 */ 688 static int 689 omap4_clk_generic_get_source_freq(struct ti_clock_dev *clkdev, 690 unsigned int *freq 691 ) 692 { 693 struct omap4_clk_details* clk_details = omap4_clk_details(clkdev->id); 694 695 if (clk_details == NULL) 696 return (ENXIO); 697 698 /* Simply return the stored frequency */ 699 if (freq) 700 *freq = (unsigned int)clk_details->src_freq; 701 702 return (0); 703 } 704 705 706 /** 707 * omap4_clk_gptimer_set_source - checks if a module is accessible 708 * @module: identifier for the module to check, see omap3_prcm.h for a list 709 * of possible modules. 710 * Example: OMAP3_MODULE_MMC1 711 * 712 * 713 * 714 * LOCKING: 715 * Inherits the locks from the omap_prcm driver, no internal locking. 716 * 717 * RETURNS: 718 * Returns 0 on success or a negative error code on failure. 719 */ 720 static int 721 omap4_clk_gptimer_set_source(struct ti_clock_dev *clkdev, 722 clk_src_t clksrc) 723 { 724 struct omap4_prcm_softc *sc; 725 struct omap4_clk_details* clk_details; 726 struct resource* clk_mem_res; 727 728 clk_details = omap4_clk_details(clkdev->id); 729 730 if (clk_details == NULL) 731 return (ENXIO); 732 733 sc = omap4_prcm_get_instance_softc(clk_details->instance); 734 if (sc == NULL) 735 return ENXIO; 736 737 clk_mem_res = sc->sc_res; 738 739 if (clk_mem_res == NULL) 740 return (EINVAL); 741 742 /* TODO: Implement */ 743 744 return (0); 745 } 746 747 /** 748 * omap4_clk_gptimer_get_source_freq - checks if a module is accessible 749 * @module: identifier for the module to check, see omap3_prcm.h for a list 750 * of possible modules. 751 * Example: OMAP3_MODULE_MMC1 752 * 753 * 754 * 755 * LOCKING: 756 * Inherits the locks from the omap_prcm driver, no internal locking. 757 * 758 * RETURNS: 759 * Returns 0 on success or a negative error code on failure. 760 */ 761 static int 762 omap4_clk_gptimer_get_source_freq(struct ti_clock_dev *clkdev, 763 unsigned int *freq 764 ) 765 { 766 struct omap4_prcm_softc *sc; 767 struct omap4_clk_details* clk_details; 768 struct resource* clk_mem_res; 769 uint32_t clksel; 770 unsigned int src_freq; 771 772 clk_details = omap4_clk_details(clkdev->id); 773 774 if (clk_details == NULL) 775 return (ENXIO); 776 777 sc = omap4_prcm_get_instance_softc(clk_details->instance); 778 if (sc == NULL) 779 return ENXIO; 780 781 clk_mem_res = sc->sc_res; 782 783 if (clk_mem_res == NULL) 784 return (EINVAL); 785 786 /* Need to read the CLKSEL field to determine the clock source */ 787 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 788 if (clksel & (0x1UL << 24)) 789 src_freq = FREQ_32KHZ; 790 else 791 omap4_clk_get_sysclk_freq(NULL, &src_freq); 792 793 /* Return the frequency */ 794 if (freq) 795 *freq = src_freq; 796 797 return (0); 798 } 799 800 /** 801 * omap4_clk_hsmmc_set_source - sets the source clock (freq) 802 * @clkdev: pointer to the clockdev structure (id field will contain clock id) 803 * 804 * The MMC 1 and 2 clocks can be source from either a 64MHz or 96MHz clock. 805 * 806 * LOCKING: 807 * Inherits the locks from the omap_prcm driver, no internal locking. 808 * 809 * RETURNS: 810 * Returns 0 on success or a negative error code on failure. 811 */ 812 static int 813 omap4_clk_hsmmc_set_source(struct ti_clock_dev *clkdev, 814 clk_src_t clksrc) 815 { 816 struct omap4_prcm_softc *sc; 817 struct omap4_clk_details* clk_details; 818 struct resource* clk_mem_res; 819 uint32_t clksel; 820 821 clk_details = omap4_clk_details(clkdev->id); 822 823 if (clk_details == NULL) 824 return (ENXIO); 825 826 827 sc = omap4_prcm_get_instance_softc(clk_details->instance); 828 if (sc == NULL) 829 return ENXIO; 830 831 clk_mem_res = sc->sc_res; 832 833 if (clk_mem_res == NULL) 834 return (EINVAL); 835 836 /* For MMC modules 3, 4 & 5 you can't change the freq, it's always 48MHz */ 837 if ((clkdev->id == MMC3_CLK) || (clkdev->id == MMC4_CLK) || 838 (clkdev->id == MMC5_CLK)) { 839 if (clksrc != F48MHZ_CLK) 840 return (EINVAL); 841 return 0; 842 } 843 844 845 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 846 847 /* Bit 24 is set if 96MHz clock or cleared for 64MHz clock */ 848 if (clksrc == F64MHZ_CLK) 849 clksel &= ~(0x1UL << 24); 850 else if (clksrc == F96MHZ_CLK) 851 clksel |= (0x1UL << 24); 852 else 853 return (EINVAL); 854 855 bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); 856 857 return (0); 858 } 859 860 /** 861 * omap4_clk_hsmmc_get_source_freq - checks if a module is accessible 862 * @clkdev: pointer to the clockdev structure (id field will contain clock id) 863 * 864 * 865 * 866 * LOCKING: 867 * Inherits the locks from the omap_prcm driver, no internal locking. 868 * 869 * RETURNS: 870 * Returns 0 on success or a negative error code on failure. 871 */ 872 static int 873 omap4_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, 874 unsigned int *freq 875 ) 876 { 877 struct omap4_prcm_softc *sc; 878 struct omap4_clk_details* clk_details; 879 struct resource* clk_mem_res; 880 uint32_t clksel; 881 unsigned int src_freq; 882 883 clk_details = omap4_clk_details(clkdev->id); 884 885 if (clk_details == NULL) 886 return (ENXIO); 887 888 sc = omap4_prcm_get_instance_softc(clk_details->instance); 889 if (sc == NULL) 890 return ENXIO; 891 892 clk_mem_res = sc->sc_res; 893 894 if (clk_mem_res == NULL) 895 return (EINVAL); 896 897 switch (clkdev->id) { 898 case MMC1_CLK: 899 case MMC2_CLK: 900 /* Need to read the CLKSEL field to determine the clock source */ 901 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 902 if (clksel & (0x1UL << 24)) 903 src_freq = FREQ_96MHZ; 904 else 905 src_freq = FREQ_64MHZ; 906 break; 907 case MMC3_CLK: 908 case MMC4_CLK: 909 case MMC5_CLK: 910 src_freq = FREQ_48MHZ; 911 break; 912 default: 913 return (EINVAL); 914 } 915 916 /* Return the frequency */ 917 if (freq) 918 *freq = src_freq; 919 920 return (0); 921 } 922 923 /** 924 * omap4_clk_get_sysclk_freq - gets the sysclk frequency 925 * @sc: pointer to the clk module/device context 926 * 927 * Read the clocking information from the power-control/boot-strap registers, 928 * and stored in two global variables. 929 * 930 * RETURNS: 931 * nothing, values are saved in global variables 932 */ 933 static int 934 omap4_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, 935 unsigned int *freq) 936 { 937 uint32_t clksel; 938 uint32_t sysclk; 939 struct omap4_prcm_softc *sc; 940 941 sc = omap4_prcm_get_instance_softc(PRM_INSTANCE); 942 if (sc == NULL) 943 return ENXIO; 944 945 /* Read the input clock freq from the configuration register (CM_SYS_CLKSEL) */ 946 clksel = bus_read_4(sc->sc_res, CM_SYS_CLKSEL_OFFSET); 947 switch (clksel & 0x7) { 948 case 0x1: 949 /* 12Mhz */ 950 sysclk = 12000000; 951 break; 952 case 0x3: 953 /* 16.8Mhz */ 954 sysclk = 16800000; 955 break; 956 case 0x4: 957 /* 19.2Mhz */ 958 sysclk = 19200000; 959 break; 960 case 0x5: 961 /* 26Mhz */ 962 sysclk = 26000000; 963 break; 964 case 0x7: 965 /* 38.4Mhz */ 966 sysclk = 38400000; 967 break; 968 default: 969 panic("%s: Invalid clock freq", __func__); 970 } 971 972 /* Return the value */ 973 if (freq) 974 *freq = sysclk; 975 976 return (0); 977 } 978 979 /** 980 * omap4_clk_get_arm_fclk_freq - gets the MPU clock frequency 981 * @clkdev: ignored 982 * @freq: pointer which upon return will contain the freq in hz 983 * @mem_res: array of allocated memory resources 984 * 985 * Reads the frequency setting information registers and returns the value 986 * in the freq variable. 987 * 988 * RETURNS: 989 * returns 0 on success, a positive error code on failure. 990 */ 991 static int 992 omap4_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, 993 unsigned int *freq) 994 { 995 uint32_t clksel; 996 uint32_t pll_mult, pll_div; 997 uint32_t mpuclk, sysclk; 998 struct omap4_prcm_softc *sc; 999 1000 sc = omap4_prcm_get_instance_softc(CM1_INSTANCE); 1001 if (sc == NULL) 1002 return ENXIO; 1003 1004 /* Read the clksel register which contains the DPLL multiple and divide 1005 * values. These are applied to the sysclk. 1006 */ 1007 clksel = bus_read_4(sc->sc_res, CM_CLKSEL_DPLL_MPU); 1008 1009 pll_mult = ((clksel >> 8) & 0x7ff); 1010 pll_div = (clksel & 0x7f) + 1; 1011 1012 1013 /* Get the system clock freq */ 1014 omap4_clk_get_sysclk_freq(NULL, &sysclk); 1015 1016 1017 /* Calculate the MPU freq */ 1018 mpuclk = ((uint64_t)sysclk * pll_mult) / pll_div; 1019 1020 /* Return the value */ 1021 if (freq) 1022 *freq = mpuclk; 1023 1024 return (0); 1025 } 1026 1027 /** 1028 * omap4_clk_hsusbhost_activate - activates the USB clocks for the given module 1029 * @clkdev: pointer to the clock device structure. 1030 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1031 * 1032 * The USB clocking setup seems to be a bit more tricky than the other modules, 1033 * to start with the clocking diagram for the HS host module shows 13 different 1034 * clocks. So to try and make it easier to follow the clocking activation 1035 * and deactivation is handled in its own set of callbacks. 1036 * 1037 * LOCKING: 1038 * Inherits the locks from the omap_prcm driver, no internal locking. 1039 * 1040 * RETURNS: 1041 * Returns 0 on success or a positive error code on failure. 1042 */ 1043 1044 struct dpll_param { 1045 unsigned int m; 1046 unsigned int n; 1047 unsigned int m2; 1048 unsigned int m3; 1049 unsigned int m4; 1050 unsigned int m5; 1051 unsigned int m6; 1052 unsigned int m7; 1053 }; 1054 /* USB parameters */ 1055 struct dpll_param usb_dpll_param[7] = { 1056 /* 12M values */ 1057 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1058 /* 13M values */ 1059 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1060 /* 16.8M values */ 1061 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1062 /* 19.2M values */ 1063 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1064 /* 26M values */ 1065 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1066 /* 27M values */ 1067 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1068 /* 38.4M values */ 1069 #ifdef CONFIG_OMAP4_SDC 1070 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, 1071 #else 1072 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, 1073 #endif 1074 }; 1075 static int 1076 omap4_clk_hsusbhost_activate(struct ti_clock_dev *clkdev) 1077 { 1078 struct omap4_prcm_softc *sc; 1079 struct resource* clk_mem_res; 1080 uint32_t clksel_reg_off; 1081 uint32_t clksel; 1082 unsigned int i; 1083 1084 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1085 if (sc == NULL) 1086 return ENXIO; 1087 1088 switch (clkdev->id) { 1089 case USBTLL_CLK: 1090 /* For the USBTLL module we need to enable the following clocks: 1091 * - INIT_L4_ICLK (will be enabled by bootloader) 1092 * - TLL_CH0_FCLK 1093 * - TLL_CH1_FCLK 1094 */ 1095 1096 /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ 1097 clk_mem_res = sc->sc_res; 1098 clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; 1099 1100 /* Enable the module and also enable the optional func clocks for 1101 * channels 0 & 1 (is this needed ?) 1102 */ 1103 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1104 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1105 clksel |= CLKCTRL_MODULEMODE_ENABLE; 1106 1107 clksel |= (0x1 << 8); /* USB-HOST optional clock: USB_CH0_CLK */ 1108 clksel |= (0x1 << 9); /* USB-HOST optional clock: USB_CH1_CLK */ 1109 break; 1110 1111 case USBHSHOST_CLK: 1112 case USBP1_PHY_CLK: 1113 case USBP2_PHY_CLK: 1114 case USBP1_UTMI_CLK: 1115 case USBP2_UTMI_CLK: 1116 case USBP1_HSIC_CLK: 1117 case USBP2_HSIC_CLK: 1118 /* For the USB HS HOST module we need to enable the following clocks: 1119 * - INIT_L4_ICLK (will be enabled by bootloader) 1120 * - INIT_L3_ICLK (will be enabled by bootloader) 1121 * - INIT_48MC_FCLK 1122 * - UTMI_ROOT_GFCLK (UTMI only, create a new clock for that ?) 1123 * - UTMI_P1_FCLK (UTMI only, create a new clock for that ?) 1124 * - UTMI_P2_FCLK (UTMI only, create a new clock for that ?) 1125 * - HSIC_P1_60 (HSIC only, create a new clock for that ?) 1126 * - HSIC_P1_480 (HSIC only, create a new clock for that ?) 1127 * - HSIC_P2_60 (HSIC only, create a new clock for that ?) 1128 * - HSIC_P2_480 (HSIC only, create a new clock for that ?) 1129 */ 1130 1131 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1132 clk_mem_res = sc->sc_res; 1133 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1134 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1135 /* Enable the module and also enable the optional func clocks */ 1136 if (clkdev->id == USBHSHOST_CLK) { 1137 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1138 clksel |= /*CLKCTRL_MODULEMODE_ENABLE*/2; 1139 1140 clksel |= (0x1 << 15); /* USB-HOST clock control: FUNC48MCLK */ 1141 } 1142 1143 else if (clkdev->id == USBP1_UTMI_CLK) 1144 clksel |= (0x1 << 8); /* UTMI_P1_CLK */ 1145 else if (clkdev->id == USBP2_UTMI_CLK) 1146 clksel |= (0x1 << 9); /* UTMI_P2_CLK */ 1147 1148 else if (clkdev->id == USBP1_HSIC_CLK) 1149 clksel |= (0x5 << 11); /* HSIC60M_P1_CLK + HSIC480M_P1_CLK */ 1150 else if (clkdev->id == USBP2_HSIC_CLK) 1151 clksel |= (0x5 << 12); /* HSIC60M_P2_CLK + HSIC480M_P2_CLK */ 1152 1153 break; 1154 1155 default: 1156 return (EINVAL); 1157 } 1158 1159 bus_write_4(clk_mem_res, clksel_reg_off, clksel); 1160 1161 /* Try MAX_MODULE_ENABLE_WAIT number of times to check if enabled */ 1162 for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) { 1163 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1164 if ((clksel & CLKCTRL_IDLEST_MASK) == CLKCTRL_IDLEST_ENABLED) 1165 break; 1166 } 1167 1168 /* Check the enabled state */ 1169 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) { 1170 printf("Error: HERE failed to enable module with clock %d\n", clkdev->id); 1171 printf("Error: 0x%08x => 0x%08x\n", clksel_reg_off, clksel); 1172 return (ETIMEDOUT); 1173 } 1174 1175 return (0); 1176 } 1177 1178 /** 1179 * omap4_clk_generic_deactivate - checks if a module is accessible 1180 * @clkdev: pointer to the clock device structure. 1181 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1182 * 1183 * 1184 * 1185 * LOCKING: 1186 * Inherits the locks from the omap_prcm driver, no internal locking. 1187 * 1188 * RETURNS: 1189 * Returns 0 on success or a positive error code on failure. 1190 */ 1191 static int 1192 omap4_clk_hsusbhost_deactivate(struct ti_clock_dev *clkdev) 1193 { 1194 struct omap4_prcm_softc *sc; 1195 struct resource* clk_mem_res; 1196 uint32_t clksel_reg_off; 1197 uint32_t clksel; 1198 1199 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1200 if (sc == NULL) 1201 return ENXIO; 1202 1203 switch (clkdev->id) { 1204 case USBTLL_CLK: 1205 /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ 1206 clk_mem_res = sc->sc_res; 1207 clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; 1208 1209 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1210 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1211 clksel |= CLKCTRL_MODULEMODE_DISABLE; 1212 break; 1213 1214 case USBHSHOST_CLK: 1215 case USBP1_PHY_CLK: 1216 case USBP2_PHY_CLK: 1217 case USBP1_UTMI_CLK: 1218 case USBP2_UTMI_CLK: 1219 case USBP1_HSIC_CLK: 1220 case USBP2_HSIC_CLK: 1221 /* For the USB HS HOST module we need to enable the following clocks: 1222 * - INIT_L4_ICLK (will be enabled by bootloader) 1223 * - INIT_L3_ICLK (will be enabled by bootloader) 1224 * - INIT_48MC_FCLK 1225 * - UTMI_ROOT_GFCLK (UTMI only, create a new clock for that ?) 1226 * - UTMI_P1_FCLK (UTMI only, create a new clock for that ?) 1227 * - UTMI_P2_FCLK (UTMI only, create a new clock for that ?) 1228 * - HSIC_P1_60 (HSIC only, create a new clock for that ?) 1229 * - HSIC_P1_480 (HSIC only, create a new clock for that ?) 1230 * - HSIC_P2_60 (HSIC only, create a new clock for that ?) 1231 * - HSIC_P2_480 (HSIC only, create a new clock for that ?) 1232 */ 1233 1234 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1235 clk_mem_res = sc->sc_res; 1236 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1237 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1238 1239 /* Enable the module and also enable the optional func clocks */ 1240 if (clkdev->id == USBHSHOST_CLK) { 1241 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1242 clksel |= CLKCTRL_MODULEMODE_DISABLE; 1243 1244 clksel &= ~(0x1 << 15); /* USB-HOST clock control: FUNC48MCLK */ 1245 } 1246 1247 else if (clkdev->id == USBP1_UTMI_CLK) 1248 clksel &= ~(0x1 << 8); /* UTMI_P1_CLK */ 1249 else if (clkdev->id == USBP2_UTMI_CLK) 1250 clksel &= ~(0x1 << 9); /* UTMI_P2_CLK */ 1251 1252 else if (clkdev->id == USBP1_HSIC_CLK) 1253 clksel &= ~(0x5 << 11); /* HSIC60M_P1_CLK + HSIC480M_P1_CLK */ 1254 else if (clkdev->id == USBP2_HSIC_CLK) 1255 clksel &= ~(0x5 << 12); /* HSIC60M_P2_CLK + HSIC480M_P2_CLK */ 1256 1257 break; 1258 1259 default: 1260 return (EINVAL); 1261 } 1262 1263 bus_write_4(clk_mem_res, clksel_reg_off, clksel); 1264 1265 return (0); 1266 } 1267 1268 /** 1269 * omap4_clk_hsusbhost_accessible - checks if a module is accessible 1270 * @clkdev: pointer to the clock device structure. 1271 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1272 * 1273 * 1274 * 1275 * LOCKING: 1276 * Inherits the locks from the omap_prcm driver, no internal locking. 1277 * 1278 * RETURNS: 1279 * Returns 0 if module is not enable, 1 if module is enabled or a negative 1280 * error code on failure. 1281 */ 1282 static int 1283 omap4_clk_hsusbhost_accessible(struct ti_clock_dev *clkdev) 1284 { 1285 struct omap4_prcm_softc *sc; 1286 struct resource* clk_mem_res; 1287 uint32_t clksel_reg_off; 1288 uint32_t clksel; 1289 1290 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1291 if (sc == NULL) 1292 return ENXIO; 1293 1294 if (clkdev->id == USBTLL_CLK) { 1295 /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ 1296 clk_mem_res = sc->sc_res; 1297 clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; 1298 } 1299 else if (clkdev->id == USBHSHOST_CLK) { 1300 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1301 clk_mem_res = sc->sc_res; 1302 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1303 } 1304 else { 1305 return (EINVAL); 1306 } 1307 1308 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1309 1310 /* Check the enabled state */ 1311 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) 1312 return (0); 1313 1314 return (1); 1315 } 1316 1317 /** 1318 * omap4_clk_hsusbhost_set_source - sets the source clocks 1319 * @clkdev: pointer to the clock device structure. 1320 * @clksrc: the clock source ID for the given clock. 1321 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1322 * 1323 * 1324 * 1325 * LOCKING: 1326 * Inherits the locks from the omap_prcm driver, no internal locking. 1327 * 1328 * RETURNS: 1329 * Returns 0 if successful otherwise a negative error code on failure. 1330 */ 1331 static int 1332 omap4_clk_hsusbhost_set_source(struct ti_clock_dev *clkdev, 1333 clk_src_t clksrc) 1334 { 1335 struct omap4_prcm_softc *sc; 1336 struct resource* clk_mem_res; 1337 uint32_t clksel_reg_off; 1338 uint32_t clksel; 1339 unsigned int bit; 1340 1341 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1342 if (sc == NULL) 1343 return ENXIO; 1344 1345 if (clkdev->id == USBP1_PHY_CLK) 1346 bit = 24; 1347 else if (clkdev->id != USBP2_PHY_CLK) 1348 bit = 25; 1349 else 1350 return (EINVAL); 1351 1352 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1353 clk_mem_res = sc->sc_res; 1354 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1355 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1356 1357 /* Set the clock source to either external or internal */ 1358 if (clksrc == EXT_CLK) 1359 clksel |= (0x1 << bit); 1360 else 1361 clksel &= ~(0x1 << bit); 1362 1363 bus_write_4(clk_mem_res, clksel_reg_off, clksel); 1364 1365 return (0); 1366 } 1367 1368 #define PRM_RSTCTRL 0x1b00 1369 #define PRM_RSTCTRL_RESET 0x2 1370 1371 static void 1372 omap4_prcm_reset(void) 1373 { 1374 struct omap4_prcm_softc *sc; 1375 1376 sc = omap4_prcm_get_instance_softc(PRM_INSTANCE); 1377 if (sc == NULL) 1378 return; 1379 1380 bus_write_4(sc->sc_res, PRM_RSTCTRL, 1381 bus_read_4(sc->sc_res, PRM_RSTCTRL) | PRM_RSTCTRL_RESET); 1382 bus_read_4(sc->sc_res, PRM_RSTCTRL); 1383 } 1384 1385 /** 1386 * omap4_prcm_probe - probe function for the driver 1387 * @dev: prcm device handle 1388 * 1389 * Simply sets the name of the driver module. 1390 * 1391 * LOCKING: 1392 * None 1393 * 1394 * RETURNS: 1395 * Always returns 0 1396 */ 1397 static int 1398 omap4_prcm_probe(device_t dev) 1399 { 1400 const struct ofw_compat_data *ocd; 1401 1402 if (!ofw_bus_status_okay(dev)) 1403 return (ENXIO); 1404 1405 ocd = ofw_bus_search_compatible(dev, compat_data); 1406 if ((int)ocd->ocd_data == 0) 1407 return (ENXIO); 1408 1409 switch ((int)ocd->ocd_data) { 1410 case PRM_INSTANCE: 1411 device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (PRM)"); 1412 break; 1413 case CM1_INSTANCE: 1414 device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (C1)"); 1415 break; 1416 case CM2_INSTANCE: 1417 device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (C2)"); 1418 break; 1419 default: 1420 device_printf(dev, "unknown instance type: %d\n", (int)ocd->ocd_data); 1421 return (ENXIO); 1422 } 1423 1424 return (BUS_PROBE_DEFAULT); 1425 } 1426 1427 /** 1428 * omap_prcm_attach - attach function for the driver 1429 * @dev: prcm device handle 1430 * 1431 * Allocates and sets up the driver context, this simply entails creating a 1432 * bus mappings for the PRCM register set. 1433 * 1434 * LOCKING: 1435 * None 1436 * 1437 * RETURNS: 1438 * Always returns 0 1439 */ 1440 1441 extern uint32_t platform_arm_tmr_freq; 1442 1443 static int 1444 omap4_prcm_attach(device_t dev) 1445 { 1446 struct omap4_prcm_softc *sc; 1447 unsigned int freq; 1448 const struct ofw_compat_data *ocd; 1449 1450 1451 sc = device_get_softc(dev); 1452 ocd = ofw_bus_search_compatible(dev, compat_data); 1453 sc->sc_instance = (int)ocd->ocd_data; 1454 1455 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 1456 RF_ACTIVE); 1457 if (sc->sc_res == NULL) { 1458 device_printf(dev, "could not allocate resources\n"); 1459 return (ENXIO); 1460 } 1461 1462 ti_cpu_reset = omap4_prcm_reset; 1463 1464 /* 1465 * In order to determine ARM frequency we need both RPM and CM1 1466 * instances up and running. So wait until all CRM devices are 1467 * initialized. Should be replaced with proper clock framework 1468 */ 1469 if (device_get_unit(dev) == 2) { 1470 omap4_clk_get_arm_fclk_freq(NULL, &freq); 1471 arm_tmr_change_frequency(freq / 2); 1472 } 1473 1474 return (0); 1475 } 1476 1477 static device_method_t omap4_prcm_methods[] = { 1478 DEVMETHOD(device_probe, omap4_prcm_probe), 1479 DEVMETHOD(device_attach, omap4_prcm_attach), 1480 {0, 0}, 1481 }; 1482 1483 static driver_t omap4_prcm_driver = { 1484 "omap4_prcm", 1485 omap4_prcm_methods, 1486 sizeof(struct omap4_prcm_softc), 1487 }; 1488 1489 static devclass_t omap4_prcm_devclass; 1490 1491 EARLY_DRIVER_MODULE(omap4_prcm, simplebus, omap4_prcm_driver, 1492 omap4_prcm_devclass, 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_EARLY); 1493 MODULE_VERSION(omap4_prcm, 1); 1494