1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2011 5 * Ben Gray <ben.r.gray@gmail.com>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the company nor the name of the author may be used to 17 * endorse or promote products derived from this software without specific 18 * prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/bus.h> 38 #include <sys/resource.h> 39 #include <sys/rman.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/intr.h> 46 47 #include <arm/arm/mpcore_timervar.h> 48 #include <arm/ti/tivar.h> 49 #include <arm/ti/ti_prcm.h> 50 #include <arm/ti/omap4/omap4_reg.h> 51 52 #include <dev/ofw/openfirm.h> 53 #include <dev/ofw/ofw_bus.h> 54 #include <dev/ofw/ofw_bus_subr.h> 55 56 /* 57 * This file defines the clock configuration for the OMAP4xxx series of 58 * devices. 59 * 60 * How This is Suppose to Work 61 * =========================== 62 * - There is a top level omap_prcm module that defines all OMAP SoC drivers 63 * should use to enable/disable the system clocks regardless of the version 64 * of OMAP device they are running on. This top level PRCM module is just 65 * a thin shim to chip specific functions that perform the donkey work of 66 * configuring the clock - this file is the 'donkey' for OMAP44xx devices. 67 * 68 * - The key bit in this file is the omap_clk_devmap array, it's 69 * used by the omap_prcm driver to determine what clocks are valid and which 70 * functions to call to manipulate them. 71 * 72 * - In essence you just need to define some callbacks for each of the 73 * clocks and then you're done. 74 * 75 * - The other thing that is worth noting is that when the omap_prcm device 76 * is registered you typically pass in some memory ranges which are the 77 * SYS_MEMORY resources. These resources are in turn allocated using 78 * bus_allocate_resources(...) and the resource handles are passed to all 79 * individual clock callback handlers. 80 * 81 * 82 * 83 * OMAP4 devices are different from the previous OMAP3 devices in that there 84 * is no longer a separate functional and interface clock for each module, 85 * instead there is typically an interface clock that spans many modules. 86 */ 87 88 #define FREQ_96MHZ 96000000 89 #define FREQ_64MHZ 64000000 90 #define FREQ_48MHZ 48000000 91 #define FREQ_32KHZ 32000 92 93 #define PRM_INSTANCE 1 94 #define CM1_INSTANCE 2 95 #define CM2_INSTANCE 3 96 97 /** 98 * Address offsets from the PRM memory region to the top level clock control 99 * registers. 100 */ 101 #define CKGEN_PRM_OFFSET 0x00000100UL 102 #define MPU_PRM_OFFSET 0x00000300UL 103 #define DSP_PRM_OFFSET 0x00000400UL 104 #define ABE_PRM_OFFSET 0x00000500UL 105 #define ALWAYS_ON_PRM_OFFSET 0x00000600UL 106 #define CORE_PRM_OFFSET 0x00000700UL 107 #define IVAHD_PRM_OFFSET 0x00000F00UL 108 #define CAM_PRM_OFFSET 0x00001000UL 109 #define DSS_PRM_OFFSET 0x00001100UL 110 #define SGX_PRM_OFFSET 0x00001200UL 111 #define L3INIT_PRM_OFFSET 0x00001300UL 112 #define L4PER_PRM_OFFSET 0x00001400UL 113 #define WKUP_PRM_OFFSET 0x00001700UL 114 #define WKUP_CM_OFFSET 0x00001800UL 115 #define EMU_PRM_OFFSET 0x00001900UL 116 #define EMU_CM_OFFSET 0x00001A00UL 117 #define DEVICE_PRM_OFFSET 0x00001B00UL 118 #define INSTR_PRM_OFFSET 0x00001F00UL 119 120 #define CM_ABE_DSS_SYS_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x0000UL) 121 #define CM_L4_WKUP_CLKSELL_OFFSET (CKGEN_PRM_OFFSET + 0x0008UL) 122 #define CM_ABE_PLL_REF_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x000CUL) 123 #define CM_SYS_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x0010UL) 124 125 /** 126 * Address offsets from the CM1 memory region to the top level clock control 127 * registers. 128 */ 129 #define CKGEN_CM1_OFFSET 0x00000100UL 130 #define MPU_CM1_OFFSET 0x00000300UL 131 #define DSP_CM1_OFFSET 0x00000400UL 132 #define ABE_CM1_OFFSET 0x00000500UL 133 #define RESTORE_CM1_OFFSET 0x00000E00UL 134 #define INSTR_CM1_OFFSET 0x00000F00UL 135 136 #define CM_CLKSEL_DPLL_MPU (CKGEN_CM1_OFFSET + 0x006CUL) 137 138 /** 139 * Address offsets from the CM2 memory region to the top level clock control 140 * registers. 141 */ 142 #define INTRCONN_SOCKET_CM2_OFFSET 0x00000000UL 143 #define CKGEN_CM2_OFFSET 0x00000100UL 144 #define ALWAYS_ON_CM2_OFFSET 0x00000600UL 145 #define CORE_CM2_OFFSET 0x00000700UL 146 #define IVAHD_CM2_OFFSET 0x00000F00UL 147 #define CAM_CM2_OFFSET 0x00001000UL 148 #define DSS_CM2_OFFSET 0x00001100UL 149 #define SGX_CM2_OFFSET 0x00001200UL 150 #define L3INIT_CM2_OFFSET 0x00001300UL 151 #define L4PER_CM2_OFFSET 0x00001400UL 152 #define RESTORE_CM2_OFFSET 0x00001E00UL 153 #define INSTR_CM2_OFFSET 0x00001F00UL 154 155 #define CLKCTRL_MODULEMODE_MASK 0x00000003UL 156 #define CLKCTRL_MODULEMODE_DISABLE 0x00000000UL 157 #define CLKCTRL_MODULEMODE_AUTO 0x00000001UL 158 #define CLKCTRL_MODULEMODE_ENABLE 0x00000001UL 159 160 #define CLKCTRL_IDLEST_MASK 0x00030000UL 161 #define CLKCTRL_IDLEST_ENABLED 0x00000000UL 162 #define CLKCTRL_IDLEST_WAKING 0x00010000UL 163 #define CLKCTRL_IDLEST_IDLE 0x00020000UL 164 #define CLKCTRL_IDLEST_DISABLED 0x00030000UL 165 166 static struct ofw_compat_data compat_data[] = { 167 {"ti,omap4-cm1", (uintptr_t)CM1_INSTANCE}, 168 {"ti,omap4-cm2", (uintptr_t)CM2_INSTANCE}, 169 {"ti,omap4-prm", (uintptr_t)PRM_INSTANCE}, 170 {NULL, (uintptr_t)0}, 171 }; 172 173 struct omap4_prcm_softc { 174 struct resource *sc_res; 175 int sc_rid; 176 int sc_instance; 177 int attach_done; 178 }; 179 180 static int omap4_clk_generic_activate(struct ti_clock_dev *clkdev); 181 static int omap4_clk_generic_deactivate(struct ti_clock_dev *clkdev); 182 static int omap4_clk_generic_accessible(struct ti_clock_dev *clkdev); 183 static int omap4_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 184 static int omap4_clk_generic_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 185 186 static int omap4_clk_gptimer_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 187 static int omap4_clk_gptimer_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 188 189 static int omap4_clk_hsmmc_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 190 static int omap4_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 191 192 static int omap4_clk_hsusbhost_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 193 static int omap4_clk_hsusbhost_activate(struct ti_clock_dev *clkdev); 194 static int omap4_clk_hsusbhost_deactivate(struct ti_clock_dev *clkdev); 195 static int omap4_clk_hsusbhost_accessible(struct ti_clock_dev *clkdev); 196 197 static int omap4_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 198 static int omap4_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 199 200 /** 201 * omap_clk_devmap - Array of clock devices available on OMAP4xxx devices 202 * 203 * This map only defines which clocks are valid and the callback functions 204 * for clock activate, deactivate, etc. It is used by the top level omap_prcm 205 * driver. 206 * 207 * The actual details of the clocks (config registers, bit fields, sources, 208 * etc) are in the private g_omap3_clk_details array below. 209 * 210 */ 211 212 #define OMAP4_GENERIC_CLOCK_DEV(i) \ 213 { .id = (i), \ 214 .clk_activate = omap4_clk_generic_activate, \ 215 .clk_deactivate = omap4_clk_generic_deactivate, \ 216 .clk_set_source = omap4_clk_generic_set_source, \ 217 .clk_accessible = omap4_clk_generic_accessible, \ 218 .clk_get_source_freq = omap4_clk_generic_get_source_freq, \ 219 .clk_set_source_freq = NULL \ 220 } 221 222 #define OMAP4_GPTIMER_CLOCK_DEV(i) \ 223 { .id = (i), \ 224 .clk_activate = omap4_clk_generic_activate, \ 225 .clk_deactivate = omap4_clk_generic_deactivate, \ 226 .clk_set_source = omap4_clk_gptimer_set_source, \ 227 .clk_accessible = omap4_clk_generic_accessible, \ 228 .clk_get_source_freq = omap4_clk_gptimer_get_source_freq, \ 229 .clk_set_source_freq = NULL \ 230 } 231 232 #define OMAP4_HSMMC_CLOCK_DEV(i) \ 233 { .id = (i), \ 234 .clk_activate = omap4_clk_generic_activate, \ 235 .clk_deactivate = omap4_clk_generic_deactivate, \ 236 .clk_set_source = omap4_clk_hsmmc_set_source, \ 237 .clk_accessible = omap4_clk_generic_accessible, \ 238 .clk_get_source_freq = omap4_clk_hsmmc_get_source_freq, \ 239 .clk_set_source_freq = NULL \ 240 } 241 242 #define OMAP4_HSUSBHOST_CLOCK_DEV(i) \ 243 { .id = (i), \ 244 .clk_activate = omap4_clk_hsusbhost_activate, \ 245 .clk_deactivate = omap4_clk_hsusbhost_deactivate, \ 246 .clk_set_source = omap4_clk_hsusbhost_set_source, \ 247 .clk_accessible = omap4_clk_hsusbhost_accessible, \ 248 .clk_get_source_freq = NULL, \ 249 .clk_set_source_freq = NULL \ 250 } 251 252 struct ti_clock_dev ti_omap4_clk_devmap[] = { 253 /* System clocks */ 254 { .id = SYS_CLK, 255 .clk_activate = NULL, 256 .clk_deactivate = NULL, 257 .clk_set_source = NULL, 258 .clk_accessible = NULL, 259 .clk_get_source_freq = omap4_clk_get_sysclk_freq, 260 .clk_set_source_freq = NULL, 261 }, 262 /* MPU (ARM) core clocks */ 263 { .id = MPU_CLK, 264 .clk_activate = NULL, 265 .clk_deactivate = NULL, 266 .clk_set_source = NULL, 267 .clk_accessible = NULL, 268 .clk_get_source_freq = omap4_clk_get_arm_fclk_freq, 269 .clk_set_source_freq = NULL, 270 }, 271 272 /* UART device clocks */ 273 OMAP4_GENERIC_CLOCK_DEV(UART1_CLK), 274 OMAP4_GENERIC_CLOCK_DEV(UART2_CLK), 275 OMAP4_GENERIC_CLOCK_DEV(UART3_CLK), 276 OMAP4_GENERIC_CLOCK_DEV(UART4_CLK), 277 278 /* Timer device source clocks */ 279 OMAP4_GPTIMER_CLOCK_DEV(TIMER1_CLK), 280 OMAP4_GPTIMER_CLOCK_DEV(TIMER2_CLK), 281 OMAP4_GPTIMER_CLOCK_DEV(TIMER3_CLK), 282 OMAP4_GPTIMER_CLOCK_DEV(TIMER4_CLK), 283 OMAP4_GPTIMER_CLOCK_DEV(TIMER5_CLK), 284 OMAP4_GPTIMER_CLOCK_DEV(TIMER6_CLK), 285 OMAP4_GPTIMER_CLOCK_DEV(TIMER7_CLK), 286 OMAP4_GPTIMER_CLOCK_DEV(TIMER8_CLK), 287 OMAP4_GPTIMER_CLOCK_DEV(TIMER9_CLK), 288 OMAP4_GPTIMER_CLOCK_DEV(TIMER10_CLK), 289 OMAP4_GPTIMER_CLOCK_DEV(TIMER11_CLK), 290 291 /* MMC device clocks (MMC1 and MMC2 can have different input clocks) */ 292 OMAP4_HSMMC_CLOCK_DEV(MMC1_CLK), 293 OMAP4_HSMMC_CLOCK_DEV(MMC2_CLK), 294 OMAP4_GENERIC_CLOCK_DEV(MMC3_CLK), 295 OMAP4_GENERIC_CLOCK_DEV(MMC4_CLK), 296 OMAP4_GENERIC_CLOCK_DEV(MMC5_CLK), 297 298 /* USB HS (high speed TLL, EHCI and OHCI) */ 299 OMAP4_HSUSBHOST_CLOCK_DEV(USBTLL_CLK), 300 OMAP4_HSUSBHOST_CLOCK_DEV(USBHSHOST_CLK), 301 OMAP4_HSUSBHOST_CLOCK_DEV(USBFSHOST_CLK), 302 OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_PHY_CLK), 303 OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_PHY_CLK), 304 OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_UTMI_CLK), 305 OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_UTMI_CLK), 306 OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_HSIC_CLK), 307 OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_HSIC_CLK), 308 309 /* GPIO */ 310 OMAP4_GENERIC_CLOCK_DEV(GPIO1_CLK), 311 OMAP4_GENERIC_CLOCK_DEV(GPIO2_CLK), 312 OMAP4_GENERIC_CLOCK_DEV(GPIO3_CLK), 313 OMAP4_GENERIC_CLOCK_DEV(GPIO4_CLK), 314 OMAP4_GENERIC_CLOCK_DEV(GPIO5_CLK), 315 OMAP4_GENERIC_CLOCK_DEV(GPIO6_CLK), 316 317 /* sDMA */ 318 OMAP4_GENERIC_CLOCK_DEV(SDMA_CLK), 319 320 /* I2C */ 321 OMAP4_GENERIC_CLOCK_DEV(I2C1_CLK), 322 OMAP4_GENERIC_CLOCK_DEV(I2C2_CLK), 323 OMAP4_GENERIC_CLOCK_DEV(I2C3_CLK), 324 OMAP4_GENERIC_CLOCK_DEV(I2C4_CLK), 325 { INVALID_CLK_IDENT, NULL, NULL, NULL, NULL } 326 }; 327 328 /** 329 * omap4_clk_details - Stores details for all the different clocks supported 330 * 331 * Whenever an operation on a clock is being performed (activated, deactivated, 332 * etc) this array is looked up to find the correct register and bit(s) we 333 * should be modifying. 334 * 335 */ 336 struct omap4_clk_details { 337 clk_ident_t id; 338 339 uint32_t instance; 340 uint32_t clksel_reg; 341 342 int32_t src_freq; 343 344 uint32_t enable_mode; 345 }; 346 347 #define OMAP4_GENERIC_CLOCK_DETAILS(i, f, di, r, e) \ 348 { .id = (i), \ 349 .instance = (di), \ 350 .clksel_reg = (r), \ 351 .src_freq = (f), \ 352 .enable_mode = (e), \ 353 } 354 355 static struct omap4_clk_details g_omap4_clk_details[] = { 356 /* UART */ 357 OMAP4_GENERIC_CLOCK_DETAILS(UART1_CLK, FREQ_48MHZ, CM2_INSTANCE, 358 (L4PER_CM2_OFFSET + 0x0140), CLKCTRL_MODULEMODE_ENABLE), 359 OMAP4_GENERIC_CLOCK_DETAILS(UART2_CLK, FREQ_48MHZ, CM2_INSTANCE, 360 (L4PER_CM2_OFFSET + 0x0148), CLKCTRL_MODULEMODE_ENABLE), 361 OMAP4_GENERIC_CLOCK_DETAILS(UART3_CLK, FREQ_48MHZ, CM2_INSTANCE, 362 (L4PER_CM2_OFFSET + 0x0150), CLKCTRL_MODULEMODE_ENABLE), 363 OMAP4_GENERIC_CLOCK_DETAILS(UART4_CLK, FREQ_48MHZ, CM2_INSTANCE, 364 (L4PER_CM2_OFFSET + 0x0158), CLKCTRL_MODULEMODE_ENABLE), 365 366 /* General purpose timers */ 367 OMAP4_GENERIC_CLOCK_DETAILS(TIMER1_CLK, -1, PRM_INSTANCE, 368 (WKUP_CM_OFFSET + 0x040), CLKCTRL_MODULEMODE_ENABLE), 369 OMAP4_GENERIC_CLOCK_DETAILS(TIMER2_CLK, -1, CM2_INSTANCE, 370 (L4PER_CM2_OFFSET + 0x038), CLKCTRL_MODULEMODE_ENABLE), 371 OMAP4_GENERIC_CLOCK_DETAILS(TIMER3_CLK, -1, CM2_INSTANCE, 372 (L4PER_CM2_OFFSET + 0x040), CLKCTRL_MODULEMODE_ENABLE), 373 OMAP4_GENERIC_CLOCK_DETAILS(TIMER4_CLK, -1, CM2_INSTANCE, 374 (L4PER_CM2_OFFSET + 0x048), CLKCTRL_MODULEMODE_ENABLE), 375 OMAP4_GENERIC_CLOCK_DETAILS(TIMER5_CLK, -1, CM1_INSTANCE, 376 (ABE_CM1_OFFSET + 0x068), CLKCTRL_MODULEMODE_ENABLE), 377 OMAP4_GENERIC_CLOCK_DETAILS(TIMER6_CLK, -1, CM1_INSTANCE, 378 (ABE_CM1_OFFSET + 0x070), CLKCTRL_MODULEMODE_ENABLE), 379 OMAP4_GENERIC_CLOCK_DETAILS(TIMER7_CLK, -1, CM1_INSTANCE, 380 (ABE_CM1_OFFSET + 0x078), CLKCTRL_MODULEMODE_ENABLE), 381 OMAP4_GENERIC_CLOCK_DETAILS(TIMER8_CLK, -1, CM1_INSTANCE, 382 (ABE_CM1_OFFSET + 0x080), CLKCTRL_MODULEMODE_ENABLE), 383 OMAP4_GENERIC_CLOCK_DETAILS(TIMER9_CLK, -1, CM2_INSTANCE, 384 (L4PER_CM2_OFFSET + 0x050), CLKCTRL_MODULEMODE_ENABLE), 385 OMAP4_GENERIC_CLOCK_DETAILS(TIMER10_CLK, -1, CM2_INSTANCE, 386 (L4PER_CM2_OFFSET + 0x028), CLKCTRL_MODULEMODE_ENABLE), 387 OMAP4_GENERIC_CLOCK_DETAILS(TIMER11_CLK, -1, CM2_INSTANCE, 388 (L4PER_CM2_OFFSET + 0x030), CLKCTRL_MODULEMODE_ENABLE), 389 390 /* HSMMC (MMC1 and MMC2 can have different input clocks) */ 391 OMAP4_GENERIC_CLOCK_DETAILS(MMC1_CLK, -1, CM2_INSTANCE, 392 (L3INIT_CM2_OFFSET + 0x028), /*CLKCTRL_MODULEMODE_ENABLE*/2), 393 OMAP4_GENERIC_CLOCK_DETAILS(MMC2_CLK, -1, CM2_INSTANCE, 394 (L3INIT_CM2_OFFSET + 0x030), /*CLKCTRL_MODULEMODE_ENABLE*/2), 395 OMAP4_GENERIC_CLOCK_DETAILS(MMC3_CLK, FREQ_48MHZ, CM2_INSTANCE, 396 (L4PER_CM2_OFFSET + 0x120), /*CLKCTRL_MODULEMODE_ENABLE*/2), 397 OMAP4_GENERIC_CLOCK_DETAILS(MMC4_CLK, FREQ_48MHZ, CM2_INSTANCE, 398 (L4PER_CM2_OFFSET + 0x128), /*CLKCTRL_MODULEMODE_ENABLE*/2), 399 OMAP4_GENERIC_CLOCK_DETAILS(MMC5_CLK, FREQ_48MHZ, CM2_INSTANCE, 400 (L4PER_CM2_OFFSET + 0x160), /*CLKCTRL_MODULEMODE_ENABLE*/1), 401 402 /* GPIO modules */ 403 OMAP4_GENERIC_CLOCK_DETAILS(GPIO1_CLK, -1, PRM_INSTANCE, 404 (WKUP_CM_OFFSET + 0x038), CLKCTRL_MODULEMODE_AUTO), 405 OMAP4_GENERIC_CLOCK_DETAILS(GPIO2_CLK, -1, CM2_INSTANCE, 406 (L4PER_CM2_OFFSET + 0x060), CLKCTRL_MODULEMODE_AUTO), 407 OMAP4_GENERIC_CLOCK_DETAILS(GPIO3_CLK, -1, CM2_INSTANCE, 408 (L4PER_CM2_OFFSET + 0x068), CLKCTRL_MODULEMODE_AUTO), 409 OMAP4_GENERIC_CLOCK_DETAILS(GPIO4_CLK, -1, CM2_INSTANCE, 410 (L4PER_CM2_OFFSET + 0x070), CLKCTRL_MODULEMODE_AUTO), 411 OMAP4_GENERIC_CLOCK_DETAILS(GPIO5_CLK, -1, CM2_INSTANCE, 412 (L4PER_CM2_OFFSET + 0x078), CLKCTRL_MODULEMODE_AUTO), 413 OMAP4_GENERIC_CLOCK_DETAILS(GPIO6_CLK, -1, CM2_INSTANCE, 414 (L4PER_CM2_OFFSET + 0x080), CLKCTRL_MODULEMODE_AUTO), 415 416 /* sDMA block */ 417 OMAP4_GENERIC_CLOCK_DETAILS(SDMA_CLK, -1, CM2_INSTANCE, 418 (CORE_CM2_OFFSET + 0x300), CLKCTRL_MODULEMODE_AUTO), 419 420 /* I2C modules */ 421 OMAP4_GENERIC_CLOCK_DETAILS(I2C1_CLK, -1, CM2_INSTANCE, 422 (L4PER_CM2_OFFSET + 0x0A0), CLKCTRL_MODULEMODE_ENABLE), 423 OMAP4_GENERIC_CLOCK_DETAILS(I2C2_CLK, -1, CM2_INSTANCE, 424 (L4PER_CM2_OFFSET + 0x0A8), CLKCTRL_MODULEMODE_ENABLE), 425 OMAP4_GENERIC_CLOCK_DETAILS(I2C3_CLK, -1, CM2_INSTANCE, 426 (L4PER_CM2_OFFSET + 0x0B0), CLKCTRL_MODULEMODE_ENABLE), 427 OMAP4_GENERIC_CLOCK_DETAILS(I2C4_CLK, -1, CM2_INSTANCE, 428 (L4PER_CM2_OFFSET + 0x0B8), CLKCTRL_MODULEMODE_ENABLE), 429 430 { INVALID_CLK_IDENT, 0, 0, 0, 0 }, 431 }; 432 433 /** 434 * MAX_MODULE_ENABLE_WAIT - the number of loops to wait for the module to come 435 * alive. 436 * 437 */ 438 #define MAX_MODULE_ENABLE_WAIT 100 439 440 /** 441 * ARRAY_SIZE - Macro to return the number of elements in a static const array. 442 * 443 */ 444 #define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 445 446 /** 447 * omap4_clk_details - writes a 32-bit value to one of the timer registers 448 * @timer: Timer device context 449 * @off: The offset of a register from the timer register address range 450 * @val: The value to write into the register 451 * 452 * 453 * RETURNS: 454 * nothing 455 */ 456 static struct omap4_clk_details* 457 omap4_clk_details(clk_ident_t id) 458 { 459 struct omap4_clk_details *walker; 460 461 for (walker = g_omap4_clk_details; walker->id != INVALID_CLK_IDENT; walker++) { 462 if (id == walker->id) 463 return (walker); 464 } 465 466 return NULL; 467 } 468 469 static struct omap4_prcm_softc * 470 omap4_prcm_get_instance_softc(int module_instance) 471 { 472 int i, maxunit; 473 devclass_t prcm_devclass; 474 device_t dev; 475 struct omap4_prcm_softc *sc; 476 477 prcm_devclass = devclass_find("omap4_prcm"); 478 maxunit = devclass_get_maxunit(prcm_devclass); 479 480 for (i = 0; i < maxunit; i++) { 481 dev = devclass_get_device(prcm_devclass, i); 482 sc = device_get_softc(dev); 483 if (sc->sc_instance == module_instance) 484 return (sc); 485 } 486 487 return (NULL); 488 } 489 490 /** 491 * omap4_clk_generic_activate - checks if a module is accessible 492 * @module: identifier for the module to check, see omap3_prcm.h for a list 493 * of possible modules. 494 * Example: OMAP3_MODULE_MMC1 495 * 496 * 497 * 498 * LOCKING: 499 * Inherits the locks from the omap_prcm driver, no internal locking. 500 * 501 * RETURNS: 502 * Returns 0 on success or a positive error code on failure. 503 */ 504 static int 505 omap4_clk_generic_activate(struct ti_clock_dev *clkdev) 506 { 507 struct omap4_prcm_softc *sc; 508 struct omap4_clk_details* clk_details; 509 struct resource* clk_mem_res; 510 uint32_t clksel; 511 unsigned int i; 512 clk_details = omap4_clk_details(clkdev->id); 513 514 if (clk_details == NULL) 515 return (ENXIO); 516 517 sc = omap4_prcm_get_instance_softc(clk_details->instance); 518 if (sc == NULL) 519 return ENXIO; 520 521 clk_mem_res = sc->sc_res; 522 523 if (clk_mem_res == NULL) 524 return (EINVAL); 525 526 /* All the 'generic' clocks have a CLKCTRL register which is more or less 527 * generic - the have at least two fielda called MODULEMODE and IDLEST. 528 */ 529 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 530 clksel &= ~CLKCTRL_MODULEMODE_MASK; 531 clksel |= clk_details->enable_mode; 532 bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); 533 534 /* Now poll on the IDLEST register to tell us if the module has come up. 535 * TODO: We need to take into account the parent clocks. 536 */ 537 538 /* Try MAX_MODULE_ENABLE_WAIT number of times to check if enabled */ 539 for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) { 540 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 541 if ((clksel & CLKCTRL_IDLEST_MASK) == CLKCTRL_IDLEST_ENABLED) 542 break; 543 DELAY(10); 544 } 545 546 /* Check the enabled state */ 547 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) { 548 printf("Error: failed to enable module with clock %d\n", clkdev->id); 549 printf("Error: 0x%08x => 0x%08x\n", clk_details->clksel_reg, clksel); 550 return (ETIMEDOUT); 551 } 552 553 return (0); 554 } 555 556 /** 557 * omap4_clk_generic_deactivate - checks if a module is accessible 558 * @module: identifier for the module to check, see omap3_prcm.h for a list 559 * of possible modules. 560 * Example: OMAP3_MODULE_MMC1 561 * 562 * 563 * 564 * LOCKING: 565 * Inherits the locks from the omap_prcm driver, no internal locking. 566 * 567 * RETURNS: 568 * Returns 0 on success or a positive error code on failure. 569 */ 570 static int 571 omap4_clk_generic_deactivate(struct ti_clock_dev *clkdev) 572 { 573 struct omap4_prcm_softc *sc; 574 struct omap4_clk_details* clk_details; 575 struct resource* clk_mem_res; 576 uint32_t clksel; 577 578 clk_details = omap4_clk_details(clkdev->id); 579 580 if (clk_details == NULL) 581 return (ENXIO); 582 583 sc = omap4_prcm_get_instance_softc(clk_details->instance); 584 if (sc == NULL) 585 return ENXIO; 586 587 clk_mem_res = sc->sc_res; 588 589 if (clk_mem_res == NULL) 590 return (EINVAL); 591 592 /* All the 'generic' clocks have a CLKCTRL register which is more or less 593 * generic - the have at least two fielda called MODULEMODE and IDLEST. 594 */ 595 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 596 clksel &= ~CLKCTRL_MODULEMODE_MASK; 597 clksel |= CLKCTRL_MODULEMODE_DISABLE; 598 bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); 599 600 return (0); 601 } 602 603 /** 604 * omap4_clk_generic_set_source - checks if a module is accessible 605 * @module: identifier for the module to check, see omap3_prcm.h for a list 606 * of possible modules. 607 * Example: OMAP3_MODULE_MMC1 608 * 609 * 610 * 611 * LOCKING: 612 * Inherits the locks from the omap_prcm driver, no internal locking. 613 * 614 * RETURNS: 615 * Returns 0 on success or a positive error code on failure. 616 */ 617 static int 618 omap4_clk_generic_set_source(struct ti_clock_dev *clkdev, 619 clk_src_t clksrc) 620 { 621 622 return (0); 623 } 624 625 /** 626 * omap4_clk_generic_accessible - checks if a module is accessible 627 * @module: identifier for the module to check, see omap3_prcm.h for a list 628 * of possible modules. 629 * Example: OMAP3_MODULE_MMC1 630 * 631 * 632 * 633 * LOCKING: 634 * Inherits the locks from the omap_prcm driver, no internal locking. 635 * 636 * RETURNS: 637 * Returns 0 on success or a negative error code on failure. 638 */ 639 static int 640 omap4_clk_generic_accessible(struct ti_clock_dev *clkdev) 641 { 642 struct omap4_prcm_softc *sc; 643 struct omap4_clk_details* clk_details; 644 struct resource* clk_mem_res; 645 uint32_t clksel; 646 647 clk_details = omap4_clk_details(clkdev->id); 648 649 if (clk_details == NULL) 650 return (ENXIO); 651 652 sc = omap4_prcm_get_instance_softc(clk_details->instance); 653 if (sc == NULL) 654 return ENXIO; 655 656 clk_mem_res = sc->sc_res; 657 658 if (clk_mem_res == NULL) 659 return (EINVAL); 660 661 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 662 663 /* Check the enabled state */ 664 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) 665 return (0); 666 667 return (1); 668 } 669 670 /** 671 * omap4_clk_generic_get_source_freq - checks if a module is accessible 672 * @module: identifier for the module to check, see omap3_prcm.h for a list 673 * of possible modules. 674 * Example: OMAP3_MODULE_MMC1 675 * 676 * 677 * 678 * LOCKING: 679 * Inherits the locks from the omap_prcm driver, no internal locking. 680 * 681 * RETURNS: 682 * Returns 0 on success or a negative error code on failure. 683 */ 684 static int 685 omap4_clk_generic_get_source_freq(struct ti_clock_dev *clkdev, 686 unsigned int *freq 687 ) 688 { 689 struct omap4_clk_details* clk_details = omap4_clk_details(clkdev->id); 690 691 if (clk_details == NULL) 692 return (ENXIO); 693 694 /* Simply return the stored frequency */ 695 if (freq) 696 *freq = (unsigned int)clk_details->src_freq; 697 698 return (0); 699 } 700 701 /** 702 * omap4_clk_gptimer_set_source - checks if a module is accessible 703 * @module: identifier for the module to check, see omap3_prcm.h for a list 704 * of possible modules. 705 * Example: OMAP3_MODULE_MMC1 706 * 707 * 708 * 709 * LOCKING: 710 * Inherits the locks from the omap_prcm driver, no internal locking. 711 * 712 * RETURNS: 713 * Returns 0 on success or a negative error code on failure. 714 */ 715 static int 716 omap4_clk_gptimer_set_source(struct ti_clock_dev *clkdev, 717 clk_src_t clksrc) 718 { 719 struct omap4_prcm_softc *sc; 720 struct omap4_clk_details* clk_details; 721 struct resource* clk_mem_res; 722 723 clk_details = omap4_clk_details(clkdev->id); 724 725 if (clk_details == NULL) 726 return (ENXIO); 727 728 sc = omap4_prcm_get_instance_softc(clk_details->instance); 729 if (sc == NULL) 730 return ENXIO; 731 732 clk_mem_res = sc->sc_res; 733 734 if (clk_mem_res == NULL) 735 return (EINVAL); 736 737 /* TODO: Implement */ 738 739 return (0); 740 } 741 742 /** 743 * omap4_clk_gptimer_get_source_freq - checks if a module is accessible 744 * @module: identifier for the module to check, see omap3_prcm.h for a list 745 * of possible modules. 746 * Example: OMAP3_MODULE_MMC1 747 * 748 * 749 * 750 * LOCKING: 751 * Inherits the locks from the omap_prcm driver, no internal locking. 752 * 753 * RETURNS: 754 * Returns 0 on success or a negative error code on failure. 755 */ 756 static int 757 omap4_clk_gptimer_get_source_freq(struct ti_clock_dev *clkdev, 758 unsigned int *freq 759 ) 760 { 761 struct omap4_prcm_softc *sc; 762 struct omap4_clk_details* clk_details; 763 struct resource* clk_mem_res; 764 uint32_t clksel; 765 unsigned int src_freq; 766 767 clk_details = omap4_clk_details(clkdev->id); 768 769 if (clk_details == NULL) 770 return (ENXIO); 771 772 sc = omap4_prcm_get_instance_softc(clk_details->instance); 773 if (sc == NULL) 774 return ENXIO; 775 776 clk_mem_res = sc->sc_res; 777 778 if (clk_mem_res == NULL) 779 return (EINVAL); 780 781 /* Need to read the CLKSEL field to determine the clock source */ 782 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 783 if (clksel & (0x1UL << 24)) 784 src_freq = FREQ_32KHZ; 785 else 786 omap4_clk_get_sysclk_freq(NULL, &src_freq); 787 788 /* Return the frequency */ 789 if (freq) 790 *freq = src_freq; 791 792 return (0); 793 } 794 795 /** 796 * omap4_clk_hsmmc_set_source - sets the source clock (freq) 797 * @clkdev: pointer to the clockdev structure (id field will contain clock id) 798 * 799 * The MMC 1 and 2 clocks can be source from either a 64MHz or 96MHz clock. 800 * 801 * LOCKING: 802 * Inherits the locks from the omap_prcm driver, no internal locking. 803 * 804 * RETURNS: 805 * Returns 0 on success or a negative error code on failure. 806 */ 807 static int 808 omap4_clk_hsmmc_set_source(struct ti_clock_dev *clkdev, 809 clk_src_t clksrc) 810 { 811 struct omap4_prcm_softc *sc; 812 struct omap4_clk_details* clk_details; 813 struct resource* clk_mem_res; 814 uint32_t clksel; 815 816 clk_details = omap4_clk_details(clkdev->id); 817 818 if (clk_details == NULL) 819 return (ENXIO); 820 821 sc = omap4_prcm_get_instance_softc(clk_details->instance); 822 if (sc == NULL) 823 return ENXIO; 824 825 clk_mem_res = sc->sc_res; 826 827 if (clk_mem_res == NULL) 828 return (EINVAL); 829 830 /* For MMC modules 3, 4 & 5 you can't change the freq, it's always 48MHz */ 831 if ((clkdev->id == MMC3_CLK) || (clkdev->id == MMC4_CLK) || 832 (clkdev->id == MMC5_CLK)) { 833 if (clksrc != F48MHZ_CLK) 834 return (EINVAL); 835 return 0; 836 } 837 838 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 839 840 /* Bit 24 is set if 96MHz clock or cleared for 64MHz clock */ 841 if (clksrc == F64MHZ_CLK) 842 clksel &= ~(0x1UL << 24); 843 else if (clksrc == F96MHZ_CLK) 844 clksel |= (0x1UL << 24); 845 else 846 return (EINVAL); 847 848 bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); 849 850 return (0); 851 } 852 853 /** 854 * omap4_clk_hsmmc_get_source_freq - checks if a module is accessible 855 * @clkdev: pointer to the clockdev structure (id field will contain clock id) 856 * 857 * 858 * 859 * LOCKING: 860 * Inherits the locks from the omap_prcm driver, no internal locking. 861 * 862 * RETURNS: 863 * Returns 0 on success or a negative error code on failure. 864 */ 865 static int 866 omap4_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, 867 unsigned int *freq 868 ) 869 { 870 struct omap4_prcm_softc *sc; 871 struct omap4_clk_details* clk_details; 872 struct resource* clk_mem_res; 873 uint32_t clksel; 874 unsigned int src_freq; 875 876 clk_details = omap4_clk_details(clkdev->id); 877 878 if (clk_details == NULL) 879 return (ENXIO); 880 881 sc = omap4_prcm_get_instance_softc(clk_details->instance); 882 if (sc == NULL) 883 return ENXIO; 884 885 clk_mem_res = sc->sc_res; 886 887 if (clk_mem_res == NULL) 888 return (EINVAL); 889 890 switch (clkdev->id) { 891 case MMC1_CLK: 892 case MMC2_CLK: 893 /* Need to read the CLKSEL field to determine the clock source */ 894 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 895 if (clksel & (0x1UL << 24)) 896 src_freq = FREQ_96MHZ; 897 else 898 src_freq = FREQ_64MHZ; 899 break; 900 case MMC3_CLK: 901 case MMC4_CLK: 902 case MMC5_CLK: 903 src_freq = FREQ_48MHZ; 904 break; 905 default: 906 return (EINVAL); 907 } 908 909 /* Return the frequency */ 910 if (freq) 911 *freq = src_freq; 912 913 return (0); 914 } 915 916 /** 917 * omap4_clk_get_sysclk_freq - gets the sysclk frequency 918 * @sc: pointer to the clk module/device context 919 * 920 * Read the clocking information from the power-control/boot-strap registers, 921 * and stored in two global variables. 922 * 923 * RETURNS: 924 * nothing, values are saved in global variables 925 */ 926 static int 927 omap4_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, 928 unsigned int *freq) 929 { 930 uint32_t clksel; 931 uint32_t sysclk; 932 struct omap4_prcm_softc *sc; 933 934 sc = omap4_prcm_get_instance_softc(PRM_INSTANCE); 935 if (sc == NULL) 936 return ENXIO; 937 938 /* Read the input clock freq from the configuration register (CM_SYS_CLKSEL) */ 939 clksel = bus_read_4(sc->sc_res, CM_SYS_CLKSEL_OFFSET); 940 switch (clksel & 0x7) { 941 case 0x1: 942 /* 12Mhz */ 943 sysclk = 12000000; 944 break; 945 case 0x3: 946 /* 16.8Mhz */ 947 sysclk = 16800000; 948 break; 949 case 0x4: 950 /* 19.2Mhz */ 951 sysclk = 19200000; 952 break; 953 case 0x5: 954 /* 26Mhz */ 955 sysclk = 26000000; 956 break; 957 case 0x7: 958 /* 38.4Mhz */ 959 sysclk = 38400000; 960 break; 961 default: 962 panic("%s: Invalid clock freq", __func__); 963 } 964 965 /* Return the value */ 966 if (freq) 967 *freq = sysclk; 968 969 return (0); 970 } 971 972 /** 973 * omap4_clk_get_arm_fclk_freq - gets the MPU clock frequency 974 * @clkdev: ignored 975 * @freq: pointer which upon return will contain the freq in hz 976 * @mem_res: array of allocated memory resources 977 * 978 * Reads the frequency setting information registers and returns the value 979 * in the freq variable. 980 * 981 * RETURNS: 982 * returns 0 on success, a positive error code on failure. 983 */ 984 static int 985 omap4_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, 986 unsigned int *freq) 987 { 988 uint32_t clksel; 989 uint32_t pll_mult, pll_div; 990 uint32_t mpuclk, sysclk; 991 struct omap4_prcm_softc *sc; 992 993 sc = omap4_prcm_get_instance_softc(CM1_INSTANCE); 994 if (sc == NULL) 995 return ENXIO; 996 997 /* Read the clksel register which contains the DPLL multiple and divide 998 * values. These are applied to the sysclk. 999 */ 1000 clksel = bus_read_4(sc->sc_res, CM_CLKSEL_DPLL_MPU); 1001 1002 pll_mult = ((clksel >> 8) & 0x7ff); 1003 pll_div = (clksel & 0x7f) + 1; 1004 1005 /* Get the system clock freq */ 1006 omap4_clk_get_sysclk_freq(NULL, &sysclk); 1007 1008 /* Calculate the MPU freq */ 1009 mpuclk = ((uint64_t)sysclk * pll_mult) / pll_div; 1010 1011 /* Return the value */ 1012 if (freq) 1013 *freq = mpuclk; 1014 1015 return (0); 1016 } 1017 1018 /** 1019 * omap4_clk_hsusbhost_activate - activates the USB clocks for the given module 1020 * @clkdev: pointer to the clock device structure. 1021 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1022 * 1023 * The USB clocking setup seems to be a bit more tricky than the other modules, 1024 * to start with the clocking diagram for the HS host module shows 13 different 1025 * clocks. So to try and make it easier to follow the clocking activation 1026 * and deactivation is handled in its own set of callbacks. 1027 * 1028 * LOCKING: 1029 * Inherits the locks from the omap_prcm driver, no internal locking. 1030 * 1031 * RETURNS: 1032 * Returns 0 on success or a positive error code on failure. 1033 */ 1034 1035 struct dpll_param { 1036 unsigned int m; 1037 unsigned int n; 1038 unsigned int m2; 1039 unsigned int m3; 1040 unsigned int m4; 1041 unsigned int m5; 1042 unsigned int m6; 1043 unsigned int m7; 1044 }; 1045 /* USB parameters */ 1046 struct dpll_param usb_dpll_param[7] = { 1047 /* 12M values */ 1048 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1049 /* 13M values */ 1050 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1051 /* 16.8M values */ 1052 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1053 /* 19.2M values */ 1054 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1055 /* 26M values */ 1056 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1057 /* 27M values */ 1058 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1059 /* 38.4M values */ 1060 #ifdef CONFIG_OMAP4_SDC 1061 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, 1062 #else 1063 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, 1064 #endif 1065 }; 1066 static int 1067 omap4_clk_hsusbhost_activate(struct ti_clock_dev *clkdev) 1068 { 1069 struct omap4_prcm_softc *sc; 1070 struct resource* clk_mem_res; 1071 uint32_t clksel_reg_off; 1072 uint32_t clksel; 1073 unsigned int i; 1074 1075 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1076 if (sc == NULL) 1077 return ENXIO; 1078 1079 switch (clkdev->id) { 1080 case USBTLL_CLK: 1081 /* For the USBTLL module we need to enable the following clocks: 1082 * - INIT_L4_ICLK (will be enabled by bootloader) 1083 * - TLL_CH0_FCLK 1084 * - TLL_CH1_FCLK 1085 */ 1086 1087 /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ 1088 clk_mem_res = sc->sc_res; 1089 clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; 1090 1091 /* Enable the module and also enable the optional func clocks for 1092 * channels 0 & 1 (is this needed ?) 1093 */ 1094 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1095 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1096 clksel |= CLKCTRL_MODULEMODE_ENABLE; 1097 1098 clksel |= (0x1 << 8); /* USB-HOST optional clock: USB_CH0_CLK */ 1099 clksel |= (0x1 << 9); /* USB-HOST optional clock: USB_CH1_CLK */ 1100 break; 1101 1102 case USBHSHOST_CLK: 1103 case USBP1_PHY_CLK: 1104 case USBP2_PHY_CLK: 1105 case USBP1_UTMI_CLK: 1106 case USBP2_UTMI_CLK: 1107 case USBP1_HSIC_CLK: 1108 case USBP2_HSIC_CLK: 1109 /* For the USB HS HOST module we need to enable the following clocks: 1110 * - INIT_L4_ICLK (will be enabled by bootloader) 1111 * - INIT_L3_ICLK (will be enabled by bootloader) 1112 * - INIT_48MC_FCLK 1113 * - UTMI_ROOT_GFCLK (UTMI only, create a new clock for that ?) 1114 * - UTMI_P1_FCLK (UTMI only, create a new clock for that ?) 1115 * - UTMI_P2_FCLK (UTMI only, create a new clock for that ?) 1116 * - HSIC_P1_60 (HSIC only, create a new clock for that ?) 1117 * - HSIC_P1_480 (HSIC only, create a new clock for that ?) 1118 * - HSIC_P2_60 (HSIC only, create a new clock for that ?) 1119 * - HSIC_P2_480 (HSIC only, create a new clock for that ?) 1120 */ 1121 1122 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1123 clk_mem_res = sc->sc_res; 1124 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1125 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1126 /* Enable the module and also enable the optional func clocks */ 1127 if (clkdev->id == USBHSHOST_CLK) { 1128 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1129 clksel |= /*CLKCTRL_MODULEMODE_ENABLE*/2; 1130 1131 clksel |= (0x1 << 15); /* USB-HOST clock control: FUNC48MCLK */ 1132 } 1133 1134 else if (clkdev->id == USBP1_UTMI_CLK) 1135 clksel |= (0x1 << 8); /* UTMI_P1_CLK */ 1136 else if (clkdev->id == USBP2_UTMI_CLK) 1137 clksel |= (0x1 << 9); /* UTMI_P2_CLK */ 1138 1139 else if (clkdev->id == USBP1_HSIC_CLK) 1140 clksel |= (0x5 << 11); /* HSIC60M_P1_CLK + HSIC480M_P1_CLK */ 1141 else if (clkdev->id == USBP2_HSIC_CLK) 1142 clksel |= (0x5 << 12); /* HSIC60M_P2_CLK + HSIC480M_P2_CLK */ 1143 1144 break; 1145 1146 default: 1147 return (EINVAL); 1148 } 1149 1150 bus_write_4(clk_mem_res, clksel_reg_off, clksel); 1151 1152 /* Try MAX_MODULE_ENABLE_WAIT number of times to check if enabled */ 1153 for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) { 1154 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1155 if ((clksel & CLKCTRL_IDLEST_MASK) == CLKCTRL_IDLEST_ENABLED) 1156 break; 1157 } 1158 1159 /* Check the enabled state */ 1160 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) { 1161 printf("Error: HERE failed to enable module with clock %d\n", clkdev->id); 1162 printf("Error: 0x%08x => 0x%08x\n", clksel_reg_off, clksel); 1163 return (ETIMEDOUT); 1164 } 1165 1166 return (0); 1167 } 1168 1169 /** 1170 * omap4_clk_generic_deactivate - checks if a module is accessible 1171 * @clkdev: pointer to the clock device structure. 1172 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1173 * 1174 * 1175 * 1176 * LOCKING: 1177 * Inherits the locks from the omap_prcm driver, no internal locking. 1178 * 1179 * RETURNS: 1180 * Returns 0 on success or a positive error code on failure. 1181 */ 1182 static int 1183 omap4_clk_hsusbhost_deactivate(struct ti_clock_dev *clkdev) 1184 { 1185 struct omap4_prcm_softc *sc; 1186 struct resource* clk_mem_res; 1187 uint32_t clksel_reg_off; 1188 uint32_t clksel; 1189 1190 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1191 if (sc == NULL) 1192 return ENXIO; 1193 1194 switch (clkdev->id) { 1195 case USBTLL_CLK: 1196 /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ 1197 clk_mem_res = sc->sc_res; 1198 clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; 1199 1200 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1201 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1202 clksel |= CLKCTRL_MODULEMODE_DISABLE; 1203 break; 1204 1205 case USBHSHOST_CLK: 1206 case USBP1_PHY_CLK: 1207 case USBP2_PHY_CLK: 1208 case USBP1_UTMI_CLK: 1209 case USBP2_UTMI_CLK: 1210 case USBP1_HSIC_CLK: 1211 case USBP2_HSIC_CLK: 1212 /* For the USB HS HOST module we need to enable the following clocks: 1213 * - INIT_L4_ICLK (will be enabled by bootloader) 1214 * - INIT_L3_ICLK (will be enabled by bootloader) 1215 * - INIT_48MC_FCLK 1216 * - UTMI_ROOT_GFCLK (UTMI only, create a new clock for that ?) 1217 * - UTMI_P1_FCLK (UTMI only, create a new clock for that ?) 1218 * - UTMI_P2_FCLK (UTMI only, create a new clock for that ?) 1219 * - HSIC_P1_60 (HSIC only, create a new clock for that ?) 1220 * - HSIC_P1_480 (HSIC only, create a new clock for that ?) 1221 * - HSIC_P2_60 (HSIC only, create a new clock for that ?) 1222 * - HSIC_P2_480 (HSIC only, create a new clock for that ?) 1223 */ 1224 1225 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1226 clk_mem_res = sc->sc_res; 1227 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1228 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1229 1230 /* Enable the module and also enable the optional func clocks */ 1231 if (clkdev->id == USBHSHOST_CLK) { 1232 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1233 clksel |= CLKCTRL_MODULEMODE_DISABLE; 1234 1235 clksel &= ~(0x1 << 15); /* USB-HOST clock control: FUNC48MCLK */ 1236 } 1237 1238 else if (clkdev->id == USBP1_UTMI_CLK) 1239 clksel &= ~(0x1 << 8); /* UTMI_P1_CLK */ 1240 else if (clkdev->id == USBP2_UTMI_CLK) 1241 clksel &= ~(0x1 << 9); /* UTMI_P2_CLK */ 1242 1243 else if (clkdev->id == USBP1_HSIC_CLK) 1244 clksel &= ~(0x5 << 11); /* HSIC60M_P1_CLK + HSIC480M_P1_CLK */ 1245 else if (clkdev->id == USBP2_HSIC_CLK) 1246 clksel &= ~(0x5 << 12); /* HSIC60M_P2_CLK + HSIC480M_P2_CLK */ 1247 1248 break; 1249 1250 default: 1251 return (EINVAL); 1252 } 1253 1254 bus_write_4(clk_mem_res, clksel_reg_off, clksel); 1255 1256 return (0); 1257 } 1258 1259 /** 1260 * omap4_clk_hsusbhost_accessible - checks if a module is accessible 1261 * @clkdev: pointer to the clock device structure. 1262 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1263 * 1264 * 1265 * 1266 * LOCKING: 1267 * Inherits the locks from the omap_prcm driver, no internal locking. 1268 * 1269 * RETURNS: 1270 * Returns 0 if module is not enable, 1 if module is enabled or a negative 1271 * error code on failure. 1272 */ 1273 static int 1274 omap4_clk_hsusbhost_accessible(struct ti_clock_dev *clkdev) 1275 { 1276 struct omap4_prcm_softc *sc; 1277 struct resource* clk_mem_res; 1278 uint32_t clksel_reg_off; 1279 uint32_t clksel; 1280 1281 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1282 if (sc == NULL) 1283 return ENXIO; 1284 1285 if (clkdev->id == USBTLL_CLK) { 1286 /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ 1287 clk_mem_res = sc->sc_res; 1288 clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; 1289 } 1290 else if (clkdev->id == USBHSHOST_CLK) { 1291 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1292 clk_mem_res = sc->sc_res; 1293 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1294 } 1295 else { 1296 return (EINVAL); 1297 } 1298 1299 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1300 1301 /* Check the enabled state */ 1302 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) 1303 return (0); 1304 1305 return (1); 1306 } 1307 1308 /** 1309 * omap4_clk_hsusbhost_set_source - sets the source clocks 1310 * @clkdev: pointer to the clock device structure. 1311 * @clksrc: the clock source ID for the given clock. 1312 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1313 * 1314 * 1315 * 1316 * LOCKING: 1317 * Inherits the locks from the omap_prcm driver, no internal locking. 1318 * 1319 * RETURNS: 1320 * Returns 0 if successful otherwise a negative error code on failure. 1321 */ 1322 static int 1323 omap4_clk_hsusbhost_set_source(struct ti_clock_dev *clkdev, 1324 clk_src_t clksrc) 1325 { 1326 struct omap4_prcm_softc *sc; 1327 struct resource* clk_mem_res; 1328 uint32_t clksel_reg_off; 1329 uint32_t clksel; 1330 unsigned int bit; 1331 1332 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1333 if (sc == NULL) 1334 return ENXIO; 1335 1336 if (clkdev->id == USBP1_PHY_CLK) 1337 bit = 24; 1338 else if (clkdev->id != USBP2_PHY_CLK) 1339 bit = 25; 1340 else 1341 return (EINVAL); 1342 1343 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1344 clk_mem_res = sc->sc_res; 1345 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1346 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1347 1348 /* Set the clock source to either external or internal */ 1349 if (clksrc == EXT_CLK) 1350 clksel |= (0x1 << bit); 1351 else 1352 clksel &= ~(0x1 << bit); 1353 1354 bus_write_4(clk_mem_res, clksel_reg_off, clksel); 1355 1356 return (0); 1357 } 1358 1359 #define PRM_RSTCTRL 0x1b00 1360 #define PRM_RSTCTRL_RESET 0x2 1361 1362 static void 1363 omap4_prcm_reset(void) 1364 { 1365 struct omap4_prcm_softc *sc; 1366 1367 sc = omap4_prcm_get_instance_softc(PRM_INSTANCE); 1368 if (sc == NULL) 1369 return; 1370 1371 bus_write_4(sc->sc_res, PRM_RSTCTRL, 1372 bus_read_4(sc->sc_res, PRM_RSTCTRL) | PRM_RSTCTRL_RESET); 1373 bus_read_4(sc->sc_res, PRM_RSTCTRL); 1374 } 1375 1376 /** 1377 * omap4_prcm_probe - probe function for the driver 1378 * @dev: prcm device handle 1379 * 1380 * Simply sets the name of the driver module. 1381 * 1382 * LOCKING: 1383 * None 1384 * 1385 * RETURNS: 1386 * Always returns 0 1387 */ 1388 static int 1389 omap4_prcm_probe(device_t dev) 1390 { 1391 const struct ofw_compat_data *ocd; 1392 1393 if (!ofw_bus_status_okay(dev)) 1394 return (ENXIO); 1395 1396 ocd = ofw_bus_search_compatible(dev, compat_data); 1397 if ((int)ocd->ocd_data == 0) 1398 return (ENXIO); 1399 1400 switch ((int)ocd->ocd_data) { 1401 case PRM_INSTANCE: 1402 device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (PRM)"); 1403 break; 1404 case CM1_INSTANCE: 1405 device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (C1)"); 1406 break; 1407 case CM2_INSTANCE: 1408 device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (C2)"); 1409 break; 1410 default: 1411 device_printf(dev, "unknown instance type: %d\n", (int)ocd->ocd_data); 1412 return (ENXIO); 1413 } 1414 1415 return (BUS_PROBE_DEFAULT); 1416 } 1417 1418 /** 1419 * omap_prcm_attach - attach function for the driver 1420 * @dev: prcm device handle 1421 * 1422 * Allocates and sets up the driver context, this simply entails creating a 1423 * bus mappings for the PRCM register set. 1424 * 1425 * LOCKING: 1426 * None 1427 * 1428 * RETURNS: 1429 * Always returns 0 1430 */ 1431 1432 extern uint32_t platform_arm_tmr_freq; 1433 1434 static int 1435 omap4_prcm_attach(device_t dev) 1436 { 1437 struct omap4_prcm_softc *sc; 1438 const struct ofw_compat_data *ocd; 1439 1440 sc = device_get_softc(dev); 1441 ocd = ofw_bus_search_compatible(dev, compat_data); 1442 sc->sc_instance = (int)ocd->ocd_data; 1443 1444 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 1445 RF_ACTIVE); 1446 if (sc->sc_res == NULL) { 1447 device_printf(dev, "could not allocate resources\n"); 1448 return (ENXIO); 1449 } 1450 1451 ti_cpu_reset = omap4_prcm_reset; 1452 1453 return (0); 1454 } 1455 1456 static void 1457 omap4_prcm_new_pass(device_t dev) 1458 { 1459 struct omap4_prcm_softc *sc = device_get_softc(dev); 1460 unsigned int freq; 1461 1462 if (sc->attach_done || 1463 bus_current_pass < (BUS_PASS_TIMER + BUS_PASS_ORDER_EARLY)) { 1464 bus_generic_new_pass(dev); 1465 return; 1466 } 1467 sc->attach_done = 1; 1468 1469 /* 1470 * In order to determine ARM frequency we need both RPM and CM1 1471 * instances up and running. So wait until all CRM devices are 1472 * initialized. Should be replaced with proper clock framework 1473 */ 1474 if (device_get_unit(dev) == 2) { 1475 omap4_clk_get_arm_fclk_freq(NULL, &freq); 1476 arm_tmr_change_frequency(freq / 2); 1477 } 1478 1479 return; 1480 } 1481 1482 static device_method_t omap4_prcm_methods[] = { 1483 DEVMETHOD(device_probe, omap4_prcm_probe), 1484 DEVMETHOD(device_attach, omap4_prcm_attach), 1485 1486 /* Bus interface */ 1487 DEVMETHOD(bus_new_pass, omap4_prcm_new_pass), 1488 1489 {0, 0}, 1490 }; 1491 1492 static driver_t omap4_prcm_driver = { 1493 "omap4_prcm", 1494 omap4_prcm_methods, 1495 sizeof(struct omap4_prcm_softc), 1496 }; 1497 1498 EARLY_DRIVER_MODULE(omap4_prcm, simplebus, omap4_prcm_driver, 0, 0, 1499 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 1500 MODULE_VERSION(omap4_prcm, 1); 1501