1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2011 5 * Ben Gray <ben.r.gray@gmail.com>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the company nor the name of the author may be used to 17 * endorse or promote products derived from this software without specific 18 * prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/bus.h> 40 #include <sys/resource.h> 41 #include <sys/rman.h> 42 #include <sys/lock.h> 43 #include <sys/malloc.h> 44 45 #include <machine/bus.h> 46 #include <machine/resource.h> 47 #include <machine/intr.h> 48 49 #include <arm/arm/mpcore_timervar.h> 50 #include <arm/ti/tivar.h> 51 #include <arm/ti/ti_prcm.h> 52 #include <arm/ti/omap4/omap4_reg.h> 53 54 #include <dev/ofw/openfirm.h> 55 #include <dev/ofw/ofw_bus.h> 56 #include <dev/ofw/ofw_bus_subr.h> 57 58 /* 59 * This file defines the clock configuration for the OMAP4xxx series of 60 * devices. 61 * 62 * How This is Suppose to Work 63 * =========================== 64 * - There is a top level omap_prcm module that defines all OMAP SoC drivers 65 * should use to enable/disable the system clocks regardless of the version 66 * of OMAP device they are running on. This top level PRCM module is just 67 * a thin shim to chip specific functions that perform the donkey work of 68 * configuring the clock - this file is the 'donkey' for OMAP44xx devices. 69 * 70 * - The key bit in this file is the omap_clk_devmap array, it's 71 * used by the omap_prcm driver to determine what clocks are valid and which 72 * functions to call to manipulate them. 73 * 74 * - In essence you just need to define some callbacks for each of the 75 * clocks and then you're done. 76 * 77 * - The other thing that is worth noting is that when the omap_prcm device 78 * is registered you typically pass in some memory ranges which are the 79 * SYS_MEMORY resources. These resources are in turn allocated using 80 * bus_allocate_resources(...) and the resource handles are passed to all 81 * individual clock callback handlers. 82 * 83 * 84 * 85 * OMAP4 devices are different from the previous OMAP3 devices in that there 86 * is no longer a separate functional and interface clock for each module, 87 * instead there is typically an interface clock that spans many modules. 88 */ 89 90 #define FREQ_96MHZ 96000000 91 #define FREQ_64MHZ 64000000 92 #define FREQ_48MHZ 48000000 93 #define FREQ_32KHZ 32000 94 95 #define PRM_INSTANCE 1 96 #define CM1_INSTANCE 2 97 #define CM2_INSTANCE 3 98 99 /** 100 * Address offsets from the PRM memory region to the top level clock control 101 * registers. 102 */ 103 #define CKGEN_PRM_OFFSET 0x00000100UL 104 #define MPU_PRM_OFFSET 0x00000300UL 105 #define DSP_PRM_OFFSET 0x00000400UL 106 #define ABE_PRM_OFFSET 0x00000500UL 107 #define ALWAYS_ON_PRM_OFFSET 0x00000600UL 108 #define CORE_PRM_OFFSET 0x00000700UL 109 #define IVAHD_PRM_OFFSET 0x00000F00UL 110 #define CAM_PRM_OFFSET 0x00001000UL 111 #define DSS_PRM_OFFSET 0x00001100UL 112 #define SGX_PRM_OFFSET 0x00001200UL 113 #define L3INIT_PRM_OFFSET 0x00001300UL 114 #define L4PER_PRM_OFFSET 0x00001400UL 115 #define WKUP_PRM_OFFSET 0x00001700UL 116 #define WKUP_CM_OFFSET 0x00001800UL 117 #define EMU_PRM_OFFSET 0x00001900UL 118 #define EMU_CM_OFFSET 0x00001A00UL 119 #define DEVICE_PRM_OFFSET 0x00001B00UL 120 #define INSTR_PRM_OFFSET 0x00001F00UL 121 122 #define CM_ABE_DSS_SYS_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x0000UL) 123 #define CM_L4_WKUP_CLKSELL_OFFSET (CKGEN_PRM_OFFSET + 0x0008UL) 124 #define CM_ABE_PLL_REF_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x000CUL) 125 #define CM_SYS_CLKSEL_OFFSET (CKGEN_PRM_OFFSET + 0x0010UL) 126 127 /** 128 * Address offsets from the CM1 memory region to the top level clock control 129 * registers. 130 */ 131 #define CKGEN_CM1_OFFSET 0x00000100UL 132 #define MPU_CM1_OFFSET 0x00000300UL 133 #define DSP_CM1_OFFSET 0x00000400UL 134 #define ABE_CM1_OFFSET 0x00000500UL 135 #define RESTORE_CM1_OFFSET 0x00000E00UL 136 #define INSTR_CM1_OFFSET 0x00000F00UL 137 138 #define CM_CLKSEL_DPLL_MPU (CKGEN_CM1_OFFSET + 0x006CUL) 139 140 /** 141 * Address offsets from the CM2 memory region to the top level clock control 142 * registers. 143 */ 144 #define INTRCONN_SOCKET_CM2_OFFSET 0x00000000UL 145 #define CKGEN_CM2_OFFSET 0x00000100UL 146 #define ALWAYS_ON_CM2_OFFSET 0x00000600UL 147 #define CORE_CM2_OFFSET 0x00000700UL 148 #define IVAHD_CM2_OFFSET 0x00000F00UL 149 #define CAM_CM2_OFFSET 0x00001000UL 150 #define DSS_CM2_OFFSET 0x00001100UL 151 #define SGX_CM2_OFFSET 0x00001200UL 152 #define L3INIT_CM2_OFFSET 0x00001300UL 153 #define L4PER_CM2_OFFSET 0x00001400UL 154 #define RESTORE_CM2_OFFSET 0x00001E00UL 155 #define INSTR_CM2_OFFSET 0x00001F00UL 156 157 #define CLKCTRL_MODULEMODE_MASK 0x00000003UL 158 #define CLKCTRL_MODULEMODE_DISABLE 0x00000000UL 159 #define CLKCTRL_MODULEMODE_AUTO 0x00000001UL 160 #define CLKCTRL_MODULEMODE_ENABLE 0x00000001UL 161 162 #define CLKCTRL_IDLEST_MASK 0x00030000UL 163 #define CLKCTRL_IDLEST_ENABLED 0x00000000UL 164 #define CLKCTRL_IDLEST_WAKING 0x00010000UL 165 #define CLKCTRL_IDLEST_IDLE 0x00020000UL 166 #define CLKCTRL_IDLEST_DISABLED 0x00030000UL 167 168 static struct ofw_compat_data compat_data[] = { 169 {"ti,omap4-cm1", (uintptr_t)CM1_INSTANCE}, 170 {"ti,omap4-cm2", (uintptr_t)CM2_INSTANCE}, 171 {"ti,omap4-prm", (uintptr_t)PRM_INSTANCE}, 172 {NULL, (uintptr_t)0}, 173 }; 174 175 struct omap4_prcm_softc { 176 struct resource *sc_res; 177 int sc_rid; 178 int sc_instance; 179 }; 180 181 static int omap4_clk_generic_activate(struct ti_clock_dev *clkdev); 182 static int omap4_clk_generic_deactivate(struct ti_clock_dev *clkdev); 183 static int omap4_clk_generic_accessible(struct ti_clock_dev *clkdev); 184 static int omap4_clk_generic_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 185 static int omap4_clk_generic_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 186 187 static int omap4_clk_gptimer_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 188 static int omap4_clk_gptimer_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 189 190 static int omap4_clk_hsmmc_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 191 static int omap4_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 192 193 static int omap4_clk_hsusbhost_set_source(struct ti_clock_dev *clkdev, clk_src_t clksrc); 194 static int omap4_clk_hsusbhost_activate(struct ti_clock_dev *clkdev); 195 static int omap4_clk_hsusbhost_deactivate(struct ti_clock_dev *clkdev); 196 static int omap4_clk_hsusbhost_accessible(struct ti_clock_dev *clkdev); 197 198 static int omap4_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 199 static int omap4_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, unsigned int *freq); 200 201 /** 202 * omap_clk_devmap - Array of clock devices available on OMAP4xxx devices 203 * 204 * This map only defines which clocks are valid and the callback functions 205 * for clock activate, deactivate, etc. It is used by the top level omap_prcm 206 * driver. 207 * 208 * The actual details of the clocks (config registers, bit fields, sources, 209 * etc) are in the private g_omap3_clk_details array below. 210 * 211 */ 212 213 #define OMAP4_GENERIC_CLOCK_DEV(i) \ 214 { .id = (i), \ 215 .clk_activate = omap4_clk_generic_activate, \ 216 .clk_deactivate = omap4_clk_generic_deactivate, \ 217 .clk_set_source = omap4_clk_generic_set_source, \ 218 .clk_accessible = omap4_clk_generic_accessible, \ 219 .clk_get_source_freq = omap4_clk_generic_get_source_freq, \ 220 .clk_set_source_freq = NULL \ 221 } 222 223 #define OMAP4_GPTIMER_CLOCK_DEV(i) \ 224 { .id = (i), \ 225 .clk_activate = omap4_clk_generic_activate, \ 226 .clk_deactivate = omap4_clk_generic_deactivate, \ 227 .clk_set_source = omap4_clk_gptimer_set_source, \ 228 .clk_accessible = omap4_clk_generic_accessible, \ 229 .clk_get_source_freq = omap4_clk_gptimer_get_source_freq, \ 230 .clk_set_source_freq = NULL \ 231 } 232 233 #define OMAP4_HSMMC_CLOCK_DEV(i) \ 234 { .id = (i), \ 235 .clk_activate = omap4_clk_generic_activate, \ 236 .clk_deactivate = omap4_clk_generic_deactivate, \ 237 .clk_set_source = omap4_clk_hsmmc_set_source, \ 238 .clk_accessible = omap4_clk_generic_accessible, \ 239 .clk_get_source_freq = omap4_clk_hsmmc_get_source_freq, \ 240 .clk_set_source_freq = NULL \ 241 } 242 243 #define OMAP4_HSUSBHOST_CLOCK_DEV(i) \ 244 { .id = (i), \ 245 .clk_activate = omap4_clk_hsusbhost_activate, \ 246 .clk_deactivate = omap4_clk_hsusbhost_deactivate, \ 247 .clk_set_source = omap4_clk_hsusbhost_set_source, \ 248 .clk_accessible = omap4_clk_hsusbhost_accessible, \ 249 .clk_get_source_freq = NULL, \ 250 .clk_set_source_freq = NULL \ 251 } 252 253 254 struct ti_clock_dev ti_omap4_clk_devmap[] = { 255 256 /* System clocks */ 257 { .id = SYS_CLK, 258 .clk_activate = NULL, 259 .clk_deactivate = NULL, 260 .clk_set_source = NULL, 261 .clk_accessible = NULL, 262 .clk_get_source_freq = omap4_clk_get_sysclk_freq, 263 .clk_set_source_freq = NULL, 264 }, 265 /* MPU (ARM) core clocks */ 266 { .id = MPU_CLK, 267 .clk_activate = NULL, 268 .clk_deactivate = NULL, 269 .clk_set_source = NULL, 270 .clk_accessible = NULL, 271 .clk_get_source_freq = omap4_clk_get_arm_fclk_freq, 272 .clk_set_source_freq = NULL, 273 }, 274 275 276 /* UART device clocks */ 277 OMAP4_GENERIC_CLOCK_DEV(UART1_CLK), 278 OMAP4_GENERIC_CLOCK_DEV(UART2_CLK), 279 OMAP4_GENERIC_CLOCK_DEV(UART3_CLK), 280 OMAP4_GENERIC_CLOCK_DEV(UART4_CLK), 281 282 /* Timer device source clocks */ 283 OMAP4_GPTIMER_CLOCK_DEV(TIMER1_CLK), 284 OMAP4_GPTIMER_CLOCK_DEV(TIMER2_CLK), 285 OMAP4_GPTIMER_CLOCK_DEV(TIMER3_CLK), 286 OMAP4_GPTIMER_CLOCK_DEV(TIMER4_CLK), 287 OMAP4_GPTIMER_CLOCK_DEV(TIMER5_CLK), 288 OMAP4_GPTIMER_CLOCK_DEV(TIMER6_CLK), 289 OMAP4_GPTIMER_CLOCK_DEV(TIMER7_CLK), 290 OMAP4_GPTIMER_CLOCK_DEV(TIMER8_CLK), 291 OMAP4_GPTIMER_CLOCK_DEV(TIMER9_CLK), 292 OMAP4_GPTIMER_CLOCK_DEV(TIMER10_CLK), 293 OMAP4_GPTIMER_CLOCK_DEV(TIMER11_CLK), 294 295 /* MMC device clocks (MMC1 and MMC2 can have different input clocks) */ 296 OMAP4_HSMMC_CLOCK_DEV(MMC1_CLK), 297 OMAP4_HSMMC_CLOCK_DEV(MMC2_CLK), 298 OMAP4_GENERIC_CLOCK_DEV(MMC3_CLK), 299 OMAP4_GENERIC_CLOCK_DEV(MMC4_CLK), 300 OMAP4_GENERIC_CLOCK_DEV(MMC5_CLK), 301 302 /* USB HS (high speed TLL, EHCI and OHCI) */ 303 OMAP4_HSUSBHOST_CLOCK_DEV(USBTLL_CLK), 304 OMAP4_HSUSBHOST_CLOCK_DEV(USBHSHOST_CLK), 305 OMAP4_HSUSBHOST_CLOCK_DEV(USBFSHOST_CLK), 306 OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_PHY_CLK), 307 OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_PHY_CLK), 308 OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_UTMI_CLK), 309 OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_UTMI_CLK), 310 OMAP4_HSUSBHOST_CLOCK_DEV(USBP1_HSIC_CLK), 311 OMAP4_HSUSBHOST_CLOCK_DEV(USBP2_HSIC_CLK), 312 313 /* GPIO */ 314 OMAP4_GENERIC_CLOCK_DEV(GPIO1_CLK), 315 OMAP4_GENERIC_CLOCK_DEV(GPIO2_CLK), 316 OMAP4_GENERIC_CLOCK_DEV(GPIO3_CLK), 317 OMAP4_GENERIC_CLOCK_DEV(GPIO4_CLK), 318 OMAP4_GENERIC_CLOCK_DEV(GPIO5_CLK), 319 OMAP4_GENERIC_CLOCK_DEV(GPIO6_CLK), 320 321 /* sDMA */ 322 OMAP4_GENERIC_CLOCK_DEV(SDMA_CLK), 323 324 /* I2C */ 325 OMAP4_GENERIC_CLOCK_DEV(I2C1_CLK), 326 OMAP4_GENERIC_CLOCK_DEV(I2C2_CLK), 327 OMAP4_GENERIC_CLOCK_DEV(I2C3_CLK), 328 OMAP4_GENERIC_CLOCK_DEV(I2C4_CLK), 329 330 { INVALID_CLK_IDENT, NULL, NULL, NULL, NULL } 331 }; 332 333 /** 334 * omap4_clk_details - Stores details for all the different clocks supported 335 * 336 * Whenever an operation on a clock is being performed (activated, deactivated, 337 * etc) this array is looked up to find the correct register and bit(s) we 338 * should be modifying. 339 * 340 */ 341 struct omap4_clk_details { 342 clk_ident_t id; 343 344 uint32_t instance; 345 uint32_t clksel_reg; 346 347 int32_t src_freq; 348 349 uint32_t enable_mode; 350 }; 351 352 #define OMAP4_GENERIC_CLOCK_DETAILS(i, f, di, r, e) \ 353 { .id = (i), \ 354 .instance = (di), \ 355 .clksel_reg = (r), \ 356 .src_freq = (f), \ 357 .enable_mode = (e), \ 358 } 359 360 static struct omap4_clk_details g_omap4_clk_details[] = { 361 362 /* UART */ 363 OMAP4_GENERIC_CLOCK_DETAILS(UART1_CLK, FREQ_48MHZ, CM2_INSTANCE, 364 (L4PER_CM2_OFFSET + 0x0140), CLKCTRL_MODULEMODE_ENABLE), 365 OMAP4_GENERIC_CLOCK_DETAILS(UART2_CLK, FREQ_48MHZ, CM2_INSTANCE, 366 (L4PER_CM2_OFFSET + 0x0148), CLKCTRL_MODULEMODE_ENABLE), 367 OMAP4_GENERIC_CLOCK_DETAILS(UART3_CLK, FREQ_48MHZ, CM2_INSTANCE, 368 (L4PER_CM2_OFFSET + 0x0150), CLKCTRL_MODULEMODE_ENABLE), 369 OMAP4_GENERIC_CLOCK_DETAILS(UART4_CLK, FREQ_48MHZ, CM2_INSTANCE, 370 (L4PER_CM2_OFFSET + 0x0158), CLKCTRL_MODULEMODE_ENABLE), 371 372 /* General purpose timers */ 373 OMAP4_GENERIC_CLOCK_DETAILS(TIMER1_CLK, -1, PRM_INSTANCE, 374 (WKUP_CM_OFFSET + 0x040), CLKCTRL_MODULEMODE_ENABLE), 375 OMAP4_GENERIC_CLOCK_DETAILS(TIMER2_CLK, -1, CM2_INSTANCE, 376 (L4PER_CM2_OFFSET + 0x038), CLKCTRL_MODULEMODE_ENABLE), 377 OMAP4_GENERIC_CLOCK_DETAILS(TIMER3_CLK, -1, CM2_INSTANCE, 378 (L4PER_CM2_OFFSET + 0x040), CLKCTRL_MODULEMODE_ENABLE), 379 OMAP4_GENERIC_CLOCK_DETAILS(TIMER4_CLK, -1, CM2_INSTANCE, 380 (L4PER_CM2_OFFSET + 0x048), CLKCTRL_MODULEMODE_ENABLE), 381 OMAP4_GENERIC_CLOCK_DETAILS(TIMER5_CLK, -1, CM1_INSTANCE, 382 (ABE_CM1_OFFSET + 0x068), CLKCTRL_MODULEMODE_ENABLE), 383 OMAP4_GENERIC_CLOCK_DETAILS(TIMER6_CLK, -1, CM1_INSTANCE, 384 (ABE_CM1_OFFSET + 0x070), CLKCTRL_MODULEMODE_ENABLE), 385 OMAP4_GENERIC_CLOCK_DETAILS(TIMER7_CLK, -1, CM1_INSTANCE, 386 (ABE_CM1_OFFSET + 0x078), CLKCTRL_MODULEMODE_ENABLE), 387 OMAP4_GENERIC_CLOCK_DETAILS(TIMER8_CLK, -1, CM1_INSTANCE, 388 (ABE_CM1_OFFSET + 0x080), CLKCTRL_MODULEMODE_ENABLE), 389 OMAP4_GENERIC_CLOCK_DETAILS(TIMER9_CLK, -1, CM2_INSTANCE, 390 (L4PER_CM2_OFFSET + 0x050), CLKCTRL_MODULEMODE_ENABLE), 391 OMAP4_GENERIC_CLOCK_DETAILS(TIMER10_CLK, -1, CM2_INSTANCE, 392 (L4PER_CM2_OFFSET + 0x028), CLKCTRL_MODULEMODE_ENABLE), 393 OMAP4_GENERIC_CLOCK_DETAILS(TIMER11_CLK, -1, CM2_INSTANCE, 394 (L4PER_CM2_OFFSET + 0x030), CLKCTRL_MODULEMODE_ENABLE), 395 396 /* HSMMC (MMC1 and MMC2 can have different input clocks) */ 397 OMAP4_GENERIC_CLOCK_DETAILS(MMC1_CLK, -1, CM2_INSTANCE, 398 (L3INIT_CM2_OFFSET + 0x028), /*CLKCTRL_MODULEMODE_ENABLE*/2), 399 OMAP4_GENERIC_CLOCK_DETAILS(MMC2_CLK, -1, CM2_INSTANCE, 400 (L3INIT_CM2_OFFSET + 0x030), /*CLKCTRL_MODULEMODE_ENABLE*/2), 401 OMAP4_GENERIC_CLOCK_DETAILS(MMC3_CLK, FREQ_48MHZ, CM2_INSTANCE, 402 (L4PER_CM2_OFFSET + 0x120), /*CLKCTRL_MODULEMODE_ENABLE*/2), 403 OMAP4_GENERIC_CLOCK_DETAILS(MMC4_CLK, FREQ_48MHZ, CM2_INSTANCE, 404 (L4PER_CM2_OFFSET + 0x128), /*CLKCTRL_MODULEMODE_ENABLE*/2), 405 OMAP4_GENERIC_CLOCK_DETAILS(MMC5_CLK, FREQ_48MHZ, CM2_INSTANCE, 406 (L4PER_CM2_OFFSET + 0x160), /*CLKCTRL_MODULEMODE_ENABLE*/1), 407 408 /* GPIO modules */ 409 OMAP4_GENERIC_CLOCK_DETAILS(GPIO1_CLK, -1, PRM_INSTANCE, 410 (WKUP_CM_OFFSET + 0x038), CLKCTRL_MODULEMODE_AUTO), 411 OMAP4_GENERIC_CLOCK_DETAILS(GPIO2_CLK, -1, CM2_INSTANCE, 412 (L4PER_CM2_OFFSET + 0x060), CLKCTRL_MODULEMODE_AUTO), 413 OMAP4_GENERIC_CLOCK_DETAILS(GPIO3_CLK, -1, CM2_INSTANCE, 414 (L4PER_CM2_OFFSET + 0x068), CLKCTRL_MODULEMODE_AUTO), 415 OMAP4_GENERIC_CLOCK_DETAILS(GPIO4_CLK, -1, CM2_INSTANCE, 416 (L4PER_CM2_OFFSET + 0x070), CLKCTRL_MODULEMODE_AUTO), 417 OMAP4_GENERIC_CLOCK_DETAILS(GPIO5_CLK, -1, CM2_INSTANCE, 418 (L4PER_CM2_OFFSET + 0x078), CLKCTRL_MODULEMODE_AUTO), 419 OMAP4_GENERIC_CLOCK_DETAILS(GPIO6_CLK, -1, CM2_INSTANCE, 420 (L4PER_CM2_OFFSET + 0x080), CLKCTRL_MODULEMODE_AUTO), 421 422 /* sDMA block */ 423 OMAP4_GENERIC_CLOCK_DETAILS(SDMA_CLK, -1, CM2_INSTANCE, 424 (CORE_CM2_OFFSET + 0x300), CLKCTRL_MODULEMODE_AUTO), 425 426 /* I2C modules */ 427 OMAP4_GENERIC_CLOCK_DETAILS(I2C1_CLK, -1, CM2_INSTANCE, 428 (L4PER_CM2_OFFSET + 0x0A0), CLKCTRL_MODULEMODE_ENABLE), 429 OMAP4_GENERIC_CLOCK_DETAILS(I2C2_CLK, -1, CM2_INSTANCE, 430 (L4PER_CM2_OFFSET + 0x0A8), CLKCTRL_MODULEMODE_ENABLE), 431 OMAP4_GENERIC_CLOCK_DETAILS(I2C3_CLK, -1, CM2_INSTANCE, 432 (L4PER_CM2_OFFSET + 0x0B0), CLKCTRL_MODULEMODE_ENABLE), 433 OMAP4_GENERIC_CLOCK_DETAILS(I2C4_CLK, -1, CM2_INSTANCE, 434 (L4PER_CM2_OFFSET + 0x0B8), CLKCTRL_MODULEMODE_ENABLE), 435 436 { INVALID_CLK_IDENT, 0, 0, 0, 0 }, 437 }; 438 439 /** 440 * MAX_MODULE_ENABLE_WAIT - the number of loops to wait for the module to come 441 * alive. 442 * 443 */ 444 #define MAX_MODULE_ENABLE_WAIT 100 445 446 /** 447 * ARRAY_SIZE - Macro to return the number of elements in a static const array. 448 * 449 */ 450 #define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 451 452 /** 453 * omap4_clk_details - writes a 32-bit value to one of the timer registers 454 * @timer: Timer device context 455 * @off: The offset of a register from the timer register address range 456 * @val: The value to write into the register 457 * 458 * 459 * RETURNS: 460 * nothing 461 */ 462 static struct omap4_clk_details* 463 omap4_clk_details(clk_ident_t id) 464 { 465 struct omap4_clk_details *walker; 466 467 for (walker = g_omap4_clk_details; walker->id != INVALID_CLK_IDENT; walker++) { 468 if (id == walker->id) 469 return (walker); 470 } 471 472 return NULL; 473 } 474 475 static struct omap4_prcm_softc * 476 omap4_prcm_get_instance_softc(int module_instance) 477 { 478 int i, maxunit; 479 devclass_t prcm_devclass; 480 device_t dev; 481 struct omap4_prcm_softc *sc; 482 483 prcm_devclass = devclass_find("omap4_prcm"); 484 maxunit = devclass_get_maxunit(prcm_devclass); 485 486 for (i = 0; i < maxunit; i++) { 487 dev = devclass_get_device(prcm_devclass, i); 488 sc = device_get_softc(dev); 489 if (sc->sc_instance == module_instance) 490 return (sc); 491 } 492 493 return (NULL); 494 } 495 496 /** 497 * omap4_clk_generic_activate - checks if a module is accessible 498 * @module: identifier for the module to check, see omap3_prcm.h for a list 499 * of possible modules. 500 * Example: OMAP3_MODULE_MMC1 501 * 502 * 503 * 504 * LOCKING: 505 * Inherits the locks from the omap_prcm driver, no internal locking. 506 * 507 * RETURNS: 508 * Returns 0 on success or a positive error code on failure. 509 */ 510 static int 511 omap4_clk_generic_activate(struct ti_clock_dev *clkdev) 512 { 513 struct omap4_prcm_softc *sc; 514 struct omap4_clk_details* clk_details; 515 struct resource* clk_mem_res; 516 uint32_t clksel; 517 unsigned int i; 518 clk_details = omap4_clk_details(clkdev->id); 519 520 if (clk_details == NULL) 521 return (ENXIO); 522 523 sc = omap4_prcm_get_instance_softc(clk_details->instance); 524 if (sc == NULL) 525 return ENXIO; 526 527 clk_mem_res = sc->sc_res; 528 529 if (clk_mem_res == NULL) 530 return (EINVAL); 531 532 /* All the 'generic' clocks have a CLKCTRL register which is more or less 533 * generic - the have at least two fielda called MODULEMODE and IDLEST. 534 */ 535 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 536 clksel &= ~CLKCTRL_MODULEMODE_MASK; 537 clksel |= clk_details->enable_mode; 538 bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); 539 540 /* Now poll on the IDLEST register to tell us if the module has come up. 541 * TODO: We need to take into account the parent clocks. 542 */ 543 544 /* Try MAX_MODULE_ENABLE_WAIT number of times to check if enabled */ 545 for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) { 546 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 547 if ((clksel & CLKCTRL_IDLEST_MASK) == CLKCTRL_IDLEST_ENABLED) 548 break; 549 DELAY(10); 550 } 551 552 /* Check the enabled state */ 553 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) { 554 printf("Error: failed to enable module with clock %d\n", clkdev->id); 555 printf("Error: 0x%08x => 0x%08x\n", clk_details->clksel_reg, clksel); 556 return (ETIMEDOUT); 557 } 558 559 return (0); 560 } 561 562 /** 563 * omap4_clk_generic_deactivate - checks if a module is accessible 564 * @module: identifier for the module to check, see omap3_prcm.h for a list 565 * of possible modules. 566 * Example: OMAP3_MODULE_MMC1 567 * 568 * 569 * 570 * LOCKING: 571 * Inherits the locks from the omap_prcm driver, no internal locking. 572 * 573 * RETURNS: 574 * Returns 0 on success or a positive error code on failure. 575 */ 576 static int 577 omap4_clk_generic_deactivate(struct ti_clock_dev *clkdev) 578 { 579 struct omap4_prcm_softc *sc; 580 struct omap4_clk_details* clk_details; 581 struct resource* clk_mem_res; 582 uint32_t clksel; 583 584 clk_details = omap4_clk_details(clkdev->id); 585 586 if (clk_details == NULL) 587 return (ENXIO); 588 589 sc = omap4_prcm_get_instance_softc(clk_details->instance); 590 if (sc == NULL) 591 return ENXIO; 592 593 clk_mem_res = sc->sc_res; 594 595 if (clk_mem_res == NULL) 596 return (EINVAL); 597 598 /* All the 'generic' clocks have a CLKCTRL register which is more or less 599 * generic - the have at least two fielda called MODULEMODE and IDLEST. 600 */ 601 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 602 clksel &= ~CLKCTRL_MODULEMODE_MASK; 603 clksel |= CLKCTRL_MODULEMODE_DISABLE; 604 bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); 605 606 return (0); 607 } 608 609 /** 610 * omap4_clk_generic_set_source - checks if a module is accessible 611 * @module: identifier for the module to check, see omap3_prcm.h for a list 612 * of possible modules. 613 * Example: OMAP3_MODULE_MMC1 614 * 615 * 616 * 617 * LOCKING: 618 * Inherits the locks from the omap_prcm driver, no internal locking. 619 * 620 * RETURNS: 621 * Returns 0 on success or a positive error code on failure. 622 */ 623 static int 624 omap4_clk_generic_set_source(struct ti_clock_dev *clkdev, 625 clk_src_t clksrc) 626 { 627 628 return (0); 629 } 630 631 /** 632 * omap4_clk_generic_accessible - checks if a module is accessible 633 * @module: identifier for the module to check, see omap3_prcm.h for a list 634 * of possible modules. 635 * Example: OMAP3_MODULE_MMC1 636 * 637 * 638 * 639 * LOCKING: 640 * Inherits the locks from the omap_prcm driver, no internal locking. 641 * 642 * RETURNS: 643 * Returns 0 on success or a negative error code on failure. 644 */ 645 static int 646 omap4_clk_generic_accessible(struct ti_clock_dev *clkdev) 647 { 648 struct omap4_prcm_softc *sc; 649 struct omap4_clk_details* clk_details; 650 struct resource* clk_mem_res; 651 uint32_t clksel; 652 653 clk_details = omap4_clk_details(clkdev->id); 654 655 if (clk_details == NULL) 656 return (ENXIO); 657 658 sc = omap4_prcm_get_instance_softc(clk_details->instance); 659 if (sc == NULL) 660 return ENXIO; 661 662 clk_mem_res = sc->sc_res; 663 664 if (clk_mem_res == NULL) 665 return (EINVAL); 666 667 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 668 669 /* Check the enabled state */ 670 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) 671 return (0); 672 673 return (1); 674 } 675 676 /** 677 * omap4_clk_generic_get_source_freq - checks if a module is accessible 678 * @module: identifier for the module to check, see omap3_prcm.h for a list 679 * of possible modules. 680 * Example: OMAP3_MODULE_MMC1 681 * 682 * 683 * 684 * LOCKING: 685 * Inherits the locks from the omap_prcm driver, no internal locking. 686 * 687 * RETURNS: 688 * Returns 0 on success or a negative error code on failure. 689 */ 690 static int 691 omap4_clk_generic_get_source_freq(struct ti_clock_dev *clkdev, 692 unsigned int *freq 693 ) 694 { 695 struct omap4_clk_details* clk_details = omap4_clk_details(clkdev->id); 696 697 if (clk_details == NULL) 698 return (ENXIO); 699 700 /* Simply return the stored frequency */ 701 if (freq) 702 *freq = (unsigned int)clk_details->src_freq; 703 704 return (0); 705 } 706 707 708 /** 709 * omap4_clk_gptimer_set_source - checks if a module is accessible 710 * @module: identifier for the module to check, see omap3_prcm.h for a list 711 * of possible modules. 712 * Example: OMAP3_MODULE_MMC1 713 * 714 * 715 * 716 * LOCKING: 717 * Inherits the locks from the omap_prcm driver, no internal locking. 718 * 719 * RETURNS: 720 * Returns 0 on success or a negative error code on failure. 721 */ 722 static int 723 omap4_clk_gptimer_set_source(struct ti_clock_dev *clkdev, 724 clk_src_t clksrc) 725 { 726 struct omap4_prcm_softc *sc; 727 struct omap4_clk_details* clk_details; 728 struct resource* clk_mem_res; 729 730 clk_details = omap4_clk_details(clkdev->id); 731 732 if (clk_details == NULL) 733 return (ENXIO); 734 735 sc = omap4_prcm_get_instance_softc(clk_details->instance); 736 if (sc == NULL) 737 return ENXIO; 738 739 clk_mem_res = sc->sc_res; 740 741 if (clk_mem_res == NULL) 742 return (EINVAL); 743 744 /* TODO: Implement */ 745 746 return (0); 747 } 748 749 /** 750 * omap4_clk_gptimer_get_source_freq - checks if a module is accessible 751 * @module: identifier for the module to check, see omap3_prcm.h for a list 752 * of possible modules. 753 * Example: OMAP3_MODULE_MMC1 754 * 755 * 756 * 757 * LOCKING: 758 * Inherits the locks from the omap_prcm driver, no internal locking. 759 * 760 * RETURNS: 761 * Returns 0 on success or a negative error code on failure. 762 */ 763 static int 764 omap4_clk_gptimer_get_source_freq(struct ti_clock_dev *clkdev, 765 unsigned int *freq 766 ) 767 { 768 struct omap4_prcm_softc *sc; 769 struct omap4_clk_details* clk_details; 770 struct resource* clk_mem_res; 771 uint32_t clksel; 772 unsigned int src_freq; 773 774 clk_details = omap4_clk_details(clkdev->id); 775 776 if (clk_details == NULL) 777 return (ENXIO); 778 779 sc = omap4_prcm_get_instance_softc(clk_details->instance); 780 if (sc == NULL) 781 return ENXIO; 782 783 clk_mem_res = sc->sc_res; 784 785 if (clk_mem_res == NULL) 786 return (EINVAL); 787 788 /* Need to read the CLKSEL field to determine the clock source */ 789 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 790 if (clksel & (0x1UL << 24)) 791 src_freq = FREQ_32KHZ; 792 else 793 omap4_clk_get_sysclk_freq(NULL, &src_freq); 794 795 /* Return the frequency */ 796 if (freq) 797 *freq = src_freq; 798 799 return (0); 800 } 801 802 /** 803 * omap4_clk_hsmmc_set_source - sets the source clock (freq) 804 * @clkdev: pointer to the clockdev structure (id field will contain clock id) 805 * 806 * The MMC 1 and 2 clocks can be source from either a 64MHz or 96MHz clock. 807 * 808 * LOCKING: 809 * Inherits the locks from the omap_prcm driver, no internal locking. 810 * 811 * RETURNS: 812 * Returns 0 on success or a negative error code on failure. 813 */ 814 static int 815 omap4_clk_hsmmc_set_source(struct ti_clock_dev *clkdev, 816 clk_src_t clksrc) 817 { 818 struct omap4_prcm_softc *sc; 819 struct omap4_clk_details* clk_details; 820 struct resource* clk_mem_res; 821 uint32_t clksel; 822 823 clk_details = omap4_clk_details(clkdev->id); 824 825 if (clk_details == NULL) 826 return (ENXIO); 827 828 829 sc = omap4_prcm_get_instance_softc(clk_details->instance); 830 if (sc == NULL) 831 return ENXIO; 832 833 clk_mem_res = sc->sc_res; 834 835 if (clk_mem_res == NULL) 836 return (EINVAL); 837 838 /* For MMC modules 3, 4 & 5 you can't change the freq, it's always 48MHz */ 839 if ((clkdev->id == MMC3_CLK) || (clkdev->id == MMC4_CLK) || 840 (clkdev->id == MMC5_CLK)) { 841 if (clksrc != F48MHZ_CLK) 842 return (EINVAL); 843 return 0; 844 } 845 846 847 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 848 849 /* Bit 24 is set if 96MHz clock or cleared for 64MHz clock */ 850 if (clksrc == F64MHZ_CLK) 851 clksel &= ~(0x1UL << 24); 852 else if (clksrc == F96MHZ_CLK) 853 clksel |= (0x1UL << 24); 854 else 855 return (EINVAL); 856 857 bus_write_4(clk_mem_res, clk_details->clksel_reg, clksel); 858 859 return (0); 860 } 861 862 /** 863 * omap4_clk_hsmmc_get_source_freq - checks if a module is accessible 864 * @clkdev: pointer to the clockdev structure (id field will contain clock id) 865 * 866 * 867 * 868 * LOCKING: 869 * Inherits the locks from the omap_prcm driver, no internal locking. 870 * 871 * RETURNS: 872 * Returns 0 on success or a negative error code on failure. 873 */ 874 static int 875 omap4_clk_hsmmc_get_source_freq(struct ti_clock_dev *clkdev, 876 unsigned int *freq 877 ) 878 { 879 struct omap4_prcm_softc *sc; 880 struct omap4_clk_details* clk_details; 881 struct resource* clk_mem_res; 882 uint32_t clksel; 883 unsigned int src_freq; 884 885 clk_details = omap4_clk_details(clkdev->id); 886 887 if (clk_details == NULL) 888 return (ENXIO); 889 890 sc = omap4_prcm_get_instance_softc(clk_details->instance); 891 if (sc == NULL) 892 return ENXIO; 893 894 clk_mem_res = sc->sc_res; 895 896 if (clk_mem_res == NULL) 897 return (EINVAL); 898 899 switch (clkdev->id) { 900 case MMC1_CLK: 901 case MMC2_CLK: 902 /* Need to read the CLKSEL field to determine the clock source */ 903 clksel = bus_read_4(clk_mem_res, clk_details->clksel_reg); 904 if (clksel & (0x1UL << 24)) 905 src_freq = FREQ_96MHZ; 906 else 907 src_freq = FREQ_64MHZ; 908 break; 909 case MMC3_CLK: 910 case MMC4_CLK: 911 case MMC5_CLK: 912 src_freq = FREQ_48MHZ; 913 break; 914 default: 915 return (EINVAL); 916 } 917 918 /* Return the frequency */ 919 if (freq) 920 *freq = src_freq; 921 922 return (0); 923 } 924 925 /** 926 * omap4_clk_get_sysclk_freq - gets the sysclk frequency 927 * @sc: pointer to the clk module/device context 928 * 929 * Read the clocking information from the power-control/boot-strap registers, 930 * and stored in two global variables. 931 * 932 * RETURNS: 933 * nothing, values are saved in global variables 934 */ 935 static int 936 omap4_clk_get_sysclk_freq(struct ti_clock_dev *clkdev, 937 unsigned int *freq) 938 { 939 uint32_t clksel; 940 uint32_t sysclk; 941 struct omap4_prcm_softc *sc; 942 943 sc = omap4_prcm_get_instance_softc(PRM_INSTANCE); 944 if (sc == NULL) 945 return ENXIO; 946 947 /* Read the input clock freq from the configuration register (CM_SYS_CLKSEL) */ 948 clksel = bus_read_4(sc->sc_res, CM_SYS_CLKSEL_OFFSET); 949 switch (clksel & 0x7) { 950 case 0x1: 951 /* 12Mhz */ 952 sysclk = 12000000; 953 break; 954 case 0x3: 955 /* 16.8Mhz */ 956 sysclk = 16800000; 957 break; 958 case 0x4: 959 /* 19.2Mhz */ 960 sysclk = 19200000; 961 break; 962 case 0x5: 963 /* 26Mhz */ 964 sysclk = 26000000; 965 break; 966 case 0x7: 967 /* 38.4Mhz */ 968 sysclk = 38400000; 969 break; 970 default: 971 panic("%s: Invalid clock freq", __func__); 972 } 973 974 /* Return the value */ 975 if (freq) 976 *freq = sysclk; 977 978 return (0); 979 } 980 981 /** 982 * omap4_clk_get_arm_fclk_freq - gets the MPU clock frequency 983 * @clkdev: ignored 984 * @freq: pointer which upon return will contain the freq in hz 985 * @mem_res: array of allocated memory resources 986 * 987 * Reads the frequency setting information registers and returns the value 988 * in the freq variable. 989 * 990 * RETURNS: 991 * returns 0 on success, a positive error code on failure. 992 */ 993 static int 994 omap4_clk_get_arm_fclk_freq(struct ti_clock_dev *clkdev, 995 unsigned int *freq) 996 { 997 uint32_t clksel; 998 uint32_t pll_mult, pll_div; 999 uint32_t mpuclk, sysclk; 1000 struct omap4_prcm_softc *sc; 1001 1002 sc = omap4_prcm_get_instance_softc(CM1_INSTANCE); 1003 if (sc == NULL) 1004 return ENXIO; 1005 1006 /* Read the clksel register which contains the DPLL multiple and divide 1007 * values. These are applied to the sysclk. 1008 */ 1009 clksel = bus_read_4(sc->sc_res, CM_CLKSEL_DPLL_MPU); 1010 1011 pll_mult = ((clksel >> 8) & 0x7ff); 1012 pll_div = (clksel & 0x7f) + 1; 1013 1014 1015 /* Get the system clock freq */ 1016 omap4_clk_get_sysclk_freq(NULL, &sysclk); 1017 1018 1019 /* Calculate the MPU freq */ 1020 mpuclk = ((uint64_t)sysclk * pll_mult) / pll_div; 1021 1022 /* Return the value */ 1023 if (freq) 1024 *freq = mpuclk; 1025 1026 return (0); 1027 } 1028 1029 /** 1030 * omap4_clk_hsusbhost_activate - activates the USB clocks for the given module 1031 * @clkdev: pointer to the clock device structure. 1032 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1033 * 1034 * The USB clocking setup seems to be a bit more tricky than the other modules, 1035 * to start with the clocking diagram for the HS host module shows 13 different 1036 * clocks. So to try and make it easier to follow the clocking activation 1037 * and deactivation is handled in its own set of callbacks. 1038 * 1039 * LOCKING: 1040 * Inherits the locks from the omap_prcm driver, no internal locking. 1041 * 1042 * RETURNS: 1043 * Returns 0 on success or a positive error code on failure. 1044 */ 1045 1046 struct dpll_param { 1047 unsigned int m; 1048 unsigned int n; 1049 unsigned int m2; 1050 unsigned int m3; 1051 unsigned int m4; 1052 unsigned int m5; 1053 unsigned int m6; 1054 unsigned int m7; 1055 }; 1056 /* USB parameters */ 1057 struct dpll_param usb_dpll_param[7] = { 1058 /* 12M values */ 1059 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1060 /* 13M values */ 1061 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1062 /* 16.8M values */ 1063 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1064 /* 19.2M values */ 1065 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1066 /* 26M values */ 1067 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1068 /* 27M values */ 1069 {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, 1070 /* 38.4M values */ 1071 #ifdef CONFIG_OMAP4_SDC 1072 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, 1073 #else 1074 {0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0}, 1075 #endif 1076 }; 1077 static int 1078 omap4_clk_hsusbhost_activate(struct ti_clock_dev *clkdev) 1079 { 1080 struct omap4_prcm_softc *sc; 1081 struct resource* clk_mem_res; 1082 uint32_t clksel_reg_off; 1083 uint32_t clksel; 1084 unsigned int i; 1085 1086 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1087 if (sc == NULL) 1088 return ENXIO; 1089 1090 switch (clkdev->id) { 1091 case USBTLL_CLK: 1092 /* For the USBTLL module we need to enable the following clocks: 1093 * - INIT_L4_ICLK (will be enabled by bootloader) 1094 * - TLL_CH0_FCLK 1095 * - TLL_CH1_FCLK 1096 */ 1097 1098 /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ 1099 clk_mem_res = sc->sc_res; 1100 clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; 1101 1102 /* Enable the module and also enable the optional func clocks for 1103 * channels 0 & 1 (is this needed ?) 1104 */ 1105 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1106 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1107 clksel |= CLKCTRL_MODULEMODE_ENABLE; 1108 1109 clksel |= (0x1 << 8); /* USB-HOST optional clock: USB_CH0_CLK */ 1110 clksel |= (0x1 << 9); /* USB-HOST optional clock: USB_CH1_CLK */ 1111 break; 1112 1113 case USBHSHOST_CLK: 1114 case USBP1_PHY_CLK: 1115 case USBP2_PHY_CLK: 1116 case USBP1_UTMI_CLK: 1117 case USBP2_UTMI_CLK: 1118 case USBP1_HSIC_CLK: 1119 case USBP2_HSIC_CLK: 1120 /* For the USB HS HOST module we need to enable the following clocks: 1121 * - INIT_L4_ICLK (will be enabled by bootloader) 1122 * - INIT_L3_ICLK (will be enabled by bootloader) 1123 * - INIT_48MC_FCLK 1124 * - UTMI_ROOT_GFCLK (UTMI only, create a new clock for that ?) 1125 * - UTMI_P1_FCLK (UTMI only, create a new clock for that ?) 1126 * - UTMI_P2_FCLK (UTMI only, create a new clock for that ?) 1127 * - HSIC_P1_60 (HSIC only, create a new clock for that ?) 1128 * - HSIC_P1_480 (HSIC only, create a new clock for that ?) 1129 * - HSIC_P2_60 (HSIC only, create a new clock for that ?) 1130 * - HSIC_P2_480 (HSIC only, create a new clock for that ?) 1131 */ 1132 1133 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1134 clk_mem_res = sc->sc_res; 1135 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1136 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1137 /* Enable the module and also enable the optional func clocks */ 1138 if (clkdev->id == USBHSHOST_CLK) { 1139 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1140 clksel |= /*CLKCTRL_MODULEMODE_ENABLE*/2; 1141 1142 clksel |= (0x1 << 15); /* USB-HOST clock control: FUNC48MCLK */ 1143 } 1144 1145 else if (clkdev->id == USBP1_UTMI_CLK) 1146 clksel |= (0x1 << 8); /* UTMI_P1_CLK */ 1147 else if (clkdev->id == USBP2_UTMI_CLK) 1148 clksel |= (0x1 << 9); /* UTMI_P2_CLK */ 1149 1150 else if (clkdev->id == USBP1_HSIC_CLK) 1151 clksel |= (0x5 << 11); /* HSIC60M_P1_CLK + HSIC480M_P1_CLK */ 1152 else if (clkdev->id == USBP2_HSIC_CLK) 1153 clksel |= (0x5 << 12); /* HSIC60M_P2_CLK + HSIC480M_P2_CLK */ 1154 1155 break; 1156 1157 default: 1158 return (EINVAL); 1159 } 1160 1161 bus_write_4(clk_mem_res, clksel_reg_off, clksel); 1162 1163 /* Try MAX_MODULE_ENABLE_WAIT number of times to check if enabled */ 1164 for (i = 0; i < MAX_MODULE_ENABLE_WAIT; i++) { 1165 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1166 if ((clksel & CLKCTRL_IDLEST_MASK) == CLKCTRL_IDLEST_ENABLED) 1167 break; 1168 } 1169 1170 /* Check the enabled state */ 1171 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) { 1172 printf("Error: HERE failed to enable module with clock %d\n", clkdev->id); 1173 printf("Error: 0x%08x => 0x%08x\n", clksel_reg_off, clksel); 1174 return (ETIMEDOUT); 1175 } 1176 1177 return (0); 1178 } 1179 1180 /** 1181 * omap4_clk_generic_deactivate - checks if a module is accessible 1182 * @clkdev: pointer to the clock device structure. 1183 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1184 * 1185 * 1186 * 1187 * LOCKING: 1188 * Inherits the locks from the omap_prcm driver, no internal locking. 1189 * 1190 * RETURNS: 1191 * Returns 0 on success or a positive error code on failure. 1192 */ 1193 static int 1194 omap4_clk_hsusbhost_deactivate(struct ti_clock_dev *clkdev) 1195 { 1196 struct omap4_prcm_softc *sc; 1197 struct resource* clk_mem_res; 1198 uint32_t clksel_reg_off; 1199 uint32_t clksel; 1200 1201 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1202 if (sc == NULL) 1203 return ENXIO; 1204 1205 switch (clkdev->id) { 1206 case USBTLL_CLK: 1207 /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ 1208 clk_mem_res = sc->sc_res; 1209 clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; 1210 1211 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1212 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1213 clksel |= CLKCTRL_MODULEMODE_DISABLE; 1214 break; 1215 1216 case USBHSHOST_CLK: 1217 case USBP1_PHY_CLK: 1218 case USBP2_PHY_CLK: 1219 case USBP1_UTMI_CLK: 1220 case USBP2_UTMI_CLK: 1221 case USBP1_HSIC_CLK: 1222 case USBP2_HSIC_CLK: 1223 /* For the USB HS HOST module we need to enable the following clocks: 1224 * - INIT_L4_ICLK (will be enabled by bootloader) 1225 * - INIT_L3_ICLK (will be enabled by bootloader) 1226 * - INIT_48MC_FCLK 1227 * - UTMI_ROOT_GFCLK (UTMI only, create a new clock for that ?) 1228 * - UTMI_P1_FCLK (UTMI only, create a new clock for that ?) 1229 * - UTMI_P2_FCLK (UTMI only, create a new clock for that ?) 1230 * - HSIC_P1_60 (HSIC only, create a new clock for that ?) 1231 * - HSIC_P1_480 (HSIC only, create a new clock for that ?) 1232 * - HSIC_P2_60 (HSIC only, create a new clock for that ?) 1233 * - HSIC_P2_480 (HSIC only, create a new clock for that ?) 1234 */ 1235 1236 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1237 clk_mem_res = sc->sc_res; 1238 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1239 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1240 1241 /* Enable the module and also enable the optional func clocks */ 1242 if (clkdev->id == USBHSHOST_CLK) { 1243 clksel &= ~CLKCTRL_MODULEMODE_MASK; 1244 clksel |= CLKCTRL_MODULEMODE_DISABLE; 1245 1246 clksel &= ~(0x1 << 15); /* USB-HOST clock control: FUNC48MCLK */ 1247 } 1248 1249 else if (clkdev->id == USBP1_UTMI_CLK) 1250 clksel &= ~(0x1 << 8); /* UTMI_P1_CLK */ 1251 else if (clkdev->id == USBP2_UTMI_CLK) 1252 clksel &= ~(0x1 << 9); /* UTMI_P2_CLK */ 1253 1254 else if (clkdev->id == USBP1_HSIC_CLK) 1255 clksel &= ~(0x5 << 11); /* HSIC60M_P1_CLK + HSIC480M_P1_CLK */ 1256 else if (clkdev->id == USBP2_HSIC_CLK) 1257 clksel &= ~(0x5 << 12); /* HSIC60M_P2_CLK + HSIC480M_P2_CLK */ 1258 1259 break; 1260 1261 default: 1262 return (EINVAL); 1263 } 1264 1265 bus_write_4(clk_mem_res, clksel_reg_off, clksel); 1266 1267 return (0); 1268 } 1269 1270 /** 1271 * omap4_clk_hsusbhost_accessible - checks if a module is accessible 1272 * @clkdev: pointer to the clock device structure. 1273 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1274 * 1275 * 1276 * 1277 * LOCKING: 1278 * Inherits the locks from the omap_prcm driver, no internal locking. 1279 * 1280 * RETURNS: 1281 * Returns 0 if module is not enable, 1 if module is enabled or a negative 1282 * error code on failure. 1283 */ 1284 static int 1285 omap4_clk_hsusbhost_accessible(struct ti_clock_dev *clkdev) 1286 { 1287 struct omap4_prcm_softc *sc; 1288 struct resource* clk_mem_res; 1289 uint32_t clksel_reg_off; 1290 uint32_t clksel; 1291 1292 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1293 if (sc == NULL) 1294 return ENXIO; 1295 1296 if (clkdev->id == USBTLL_CLK) { 1297 /* We need the CM_L3INIT_HSUSBTLL_CLKCTRL register in CM2 register set */ 1298 clk_mem_res = sc->sc_res; 1299 clksel_reg_off = L3INIT_CM2_OFFSET + 0x68; 1300 } 1301 else if (clkdev->id == USBHSHOST_CLK) { 1302 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1303 clk_mem_res = sc->sc_res; 1304 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1305 } 1306 else { 1307 return (EINVAL); 1308 } 1309 1310 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1311 1312 /* Check the enabled state */ 1313 if ((clksel & CLKCTRL_IDLEST_MASK) != CLKCTRL_IDLEST_ENABLED) 1314 return (0); 1315 1316 return (1); 1317 } 1318 1319 /** 1320 * omap4_clk_hsusbhost_set_source - sets the source clocks 1321 * @clkdev: pointer to the clock device structure. 1322 * @clksrc: the clock source ID for the given clock. 1323 * @mem_res: array of memory resources allocated by the top level PRCM driver. 1324 * 1325 * 1326 * 1327 * LOCKING: 1328 * Inherits the locks from the omap_prcm driver, no internal locking. 1329 * 1330 * RETURNS: 1331 * Returns 0 if successful otherwise a negative error code on failure. 1332 */ 1333 static int 1334 omap4_clk_hsusbhost_set_source(struct ti_clock_dev *clkdev, 1335 clk_src_t clksrc) 1336 { 1337 struct omap4_prcm_softc *sc; 1338 struct resource* clk_mem_res; 1339 uint32_t clksel_reg_off; 1340 uint32_t clksel; 1341 unsigned int bit; 1342 1343 sc = omap4_prcm_get_instance_softc(CM2_INSTANCE); 1344 if (sc == NULL) 1345 return ENXIO; 1346 1347 if (clkdev->id == USBP1_PHY_CLK) 1348 bit = 24; 1349 else if (clkdev->id != USBP2_PHY_CLK) 1350 bit = 25; 1351 else 1352 return (EINVAL); 1353 1354 /* We need the CM_L3INIT_HSUSBHOST_CLKCTRL register in CM2 register set */ 1355 clk_mem_res = sc->sc_res; 1356 clksel_reg_off = L3INIT_CM2_OFFSET + 0x58; 1357 clksel = bus_read_4(clk_mem_res, clksel_reg_off); 1358 1359 /* Set the clock source to either external or internal */ 1360 if (clksrc == EXT_CLK) 1361 clksel |= (0x1 << bit); 1362 else 1363 clksel &= ~(0x1 << bit); 1364 1365 bus_write_4(clk_mem_res, clksel_reg_off, clksel); 1366 1367 return (0); 1368 } 1369 1370 #define PRM_RSTCTRL 0x1b00 1371 #define PRM_RSTCTRL_RESET 0x2 1372 1373 static void 1374 omap4_prcm_reset(void) 1375 { 1376 struct omap4_prcm_softc *sc; 1377 1378 sc = omap4_prcm_get_instance_softc(PRM_INSTANCE); 1379 if (sc == NULL) 1380 return; 1381 1382 bus_write_4(sc->sc_res, PRM_RSTCTRL, 1383 bus_read_4(sc->sc_res, PRM_RSTCTRL) | PRM_RSTCTRL_RESET); 1384 bus_read_4(sc->sc_res, PRM_RSTCTRL); 1385 } 1386 1387 /** 1388 * omap4_prcm_probe - probe function for the driver 1389 * @dev: prcm device handle 1390 * 1391 * Simply sets the name of the driver module. 1392 * 1393 * LOCKING: 1394 * None 1395 * 1396 * RETURNS: 1397 * Always returns 0 1398 */ 1399 static int 1400 omap4_prcm_probe(device_t dev) 1401 { 1402 const struct ofw_compat_data *ocd; 1403 1404 if (!ofw_bus_status_okay(dev)) 1405 return (ENXIO); 1406 1407 ocd = ofw_bus_search_compatible(dev, compat_data); 1408 if ((int)ocd->ocd_data == 0) 1409 return (ENXIO); 1410 1411 switch ((int)ocd->ocd_data) { 1412 case PRM_INSTANCE: 1413 device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (PRM)"); 1414 break; 1415 case CM1_INSTANCE: 1416 device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (C1)"); 1417 break; 1418 case CM2_INSTANCE: 1419 device_set_desc(dev, "TI OMAP Power, Reset and Clock Management (C2)"); 1420 break; 1421 default: 1422 device_printf(dev, "unknown instance type: %d\n", (int)ocd->ocd_data); 1423 return (ENXIO); 1424 } 1425 1426 return (BUS_PROBE_DEFAULT); 1427 } 1428 1429 /** 1430 * omap_prcm_attach - attach function for the driver 1431 * @dev: prcm device handle 1432 * 1433 * Allocates and sets up the driver context, this simply entails creating a 1434 * bus mappings for the PRCM register set. 1435 * 1436 * LOCKING: 1437 * None 1438 * 1439 * RETURNS: 1440 * Always returns 0 1441 */ 1442 1443 extern uint32_t platform_arm_tmr_freq; 1444 1445 static int 1446 omap4_prcm_attach(device_t dev) 1447 { 1448 struct omap4_prcm_softc *sc; 1449 unsigned int freq; 1450 const struct ofw_compat_data *ocd; 1451 1452 1453 sc = device_get_softc(dev); 1454 ocd = ofw_bus_search_compatible(dev, compat_data); 1455 sc->sc_instance = (int)ocd->ocd_data; 1456 1457 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 1458 RF_ACTIVE); 1459 if (sc->sc_res == NULL) { 1460 device_printf(dev, "could not allocate resources\n"); 1461 return (ENXIO); 1462 } 1463 1464 ti_cpu_reset = omap4_prcm_reset; 1465 1466 /* 1467 * In order to determine ARM frequency we need both RPM and CM1 1468 * instances up and running. So wait until all CRM devices are 1469 * initialized. Should be replaced with proper clock framework 1470 */ 1471 if (device_get_unit(dev) == 2) { 1472 omap4_clk_get_arm_fclk_freq(NULL, &freq); 1473 arm_tmr_change_frequency(freq / 2); 1474 } 1475 1476 return (0); 1477 } 1478 1479 static device_method_t omap4_prcm_methods[] = { 1480 DEVMETHOD(device_probe, omap4_prcm_probe), 1481 DEVMETHOD(device_attach, omap4_prcm_attach), 1482 {0, 0}, 1483 }; 1484 1485 static driver_t omap4_prcm_driver = { 1486 "omap4_prcm", 1487 omap4_prcm_methods, 1488 sizeof(struct omap4_prcm_softc), 1489 }; 1490 1491 static devclass_t omap4_prcm_devclass; 1492 1493 EARLY_DRIVER_MODULE(omap4_prcm, simplebus, omap4_prcm_driver, 1494 omap4_prcm_devclass, 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_EARLY); 1495 MODULE_VERSION(omap4_prcm, 1); 1496