1 /*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _IF_CPSWVAR_H 30 #define _IF_CPSWVAR_H 31 32 #define CPSW_INTR_COUNT 4 33 34 /* MII BUS */ 35 #define CPSW_MIIBUS_RETRIES 5 36 #define CPSW_MIIBUS_DELAY 1000 37 38 #define CPSW_MAX_TX_BUFFERS 128 39 #define CPSW_MAX_RX_BUFFERS 128 40 #define CPSW_MAX_ALE_ENTRIES 1024 41 42 struct cpsw_softc { 43 struct ifnet *ifp; 44 phandle_t node; 45 device_t dev; 46 uint8_t mac_addr[ETHER_ADDR_LEN]; 47 device_t miibus; 48 struct mii_data *mii; 49 struct mtx tx_lock; /* transmitter lock */ 50 struct mtx rx_lock; /* receiver lock */ 51 struct resource *res[1 + CPSW_INTR_COUNT]; /* resources */ 52 void *ih_cookie[CPSW_INTR_COUNT]; /* interrupt handlers cookies */ 53 54 uint32_t cpsw_if_flags; 55 int cpsw_media_status; 56 57 struct callout wd_callout; 58 int wd_timer; 59 60 /* buffers */ 61 bus_dma_tag_t mbuf_dtag; 62 bus_dmamap_t tx_dmamap[CPSW_MAX_TX_BUFFERS]; 63 bus_dmamap_t rx_dmamap[CPSW_MAX_RX_BUFFERS]; 64 struct mbuf *tx_mbuf[CPSW_MAX_TX_BUFFERS]; 65 struct mbuf *rx_mbuf[CPSW_MAX_RX_BUFFERS]; 66 int txbd_head; 67 int txbd_queue_size; 68 int rxbd_head; 69 int rxbd_tail; 70 71 int tmp; 72 int eoq; 73 int tc[CPSW_MAX_TX_BUFFERS]; 74 int tc_unload[CPSW_MAX_TX_BUFFERS]; 75 76 struct cpsw_softc *phy_sc; 77 }; 78 79 #define CPDMA_BD_SOP (1<<15) 80 #define CPDMA_BD_EOP (1<<14) 81 #define CPDMA_BD_OWNER (1<<13) 82 #define CPDMA_BD_EOQ (1<<12) 83 #define CPDMA_BD_PKT_ERR_MASK (3<< 4) 84 85 struct cpsw_cpdma_bd { 86 volatile uint32_t next; 87 volatile uint32_t bufptr; 88 volatile uint16_t buflen; 89 volatile uint16_t bufoff; 90 volatile uint16_t pktlen; 91 volatile uint16_t flags; 92 }; 93 94 /* Read/Write macros */ 95 #define cpsw_read_4(reg) bus_read_4(sc->res[0], reg) 96 #define cpsw_write_4(reg, val) bus_write_4(sc->res[0], reg, val) 97 98 #define cpsw_cpdma_txbd_offset(i) \ 99 (CPSW_CPPI_RAM_OFFSET + ((i)*16)) 100 #define cpsw_cpdma_txbd_paddr(i) (cpsw_cpdma_txbd_offset(i) + \ 101 vtophys(rman_get_start(sc->res[0]))) 102 #define cpsw_cpdma_read_txbd(i, val) \ 103 bus_read_region_4(sc->res[0], cpsw_cpdma_txbd_offset(i), (uint32_t *) val, 4) 104 #define cpsw_cpdma_write_txbd(i, val) \ 105 bus_write_region_4(sc->res[0], cpsw_cpdma_txbd_offset(i), (uint32_t *) val, 4) 106 #define cpsw_cpdma_write_txbd_next(i, val) \ 107 bus_write_4(sc->res[0], cpsw_cpdma_txbd_offset(i), val) 108 #define cpsw_cpdma_read_txbd_flags(i) \ 109 bus_read_2(sc->res[0], cpsw_cpdma_txbd_offset(i)+14) 110 111 #define cpsw_cpdma_rxbd_offset(i) \ 112 (CPSW_CPPI_RAM_OFFSET + ((CPSW_MAX_TX_BUFFERS + (i))*16)) 113 #define cpsw_cpdma_rxbd_paddr(i) (cpsw_cpdma_rxbd_offset(i) + \ 114 vtophys(rman_get_start(sc->res[0]))) 115 #define cpsw_cpdma_read_rxbd(i, val) \ 116 bus_read_region_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), (uint32_t *) val, 4) 117 #define cpsw_cpdma_write_rxbd(i, val) \ 118 bus_write_region_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), (uint32_t *) val, 4) 119 #define cpsw_cpdma_write_rxbd_next(i, val) \ 120 bus_write_4(sc->res[0], cpsw_cpdma_rxbd_offset(i), val) 121 #define cpsw_cpdma_read_rxbd_flags(i) \ 122 bus_read_2(sc->res[0], cpsw_cpdma_rxbd_offset(i)+14) 123 124 #endif /*_IF_CPSWVAR_H */ 125