1 /*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _IF_CPSWVAR_H 30 #define _IF_CPSWVAR_H 31 32 #define CPSW_PORTS 2 33 #define CPSW_INTR_COUNT 4 34 35 /* MII BUS */ 36 #define CPSW_MIIBUS_RETRIES 5 37 #define CPSW_MIIBUS_DELAY 1000 38 39 #define CPSW_MAX_ALE_ENTRIES 1024 40 41 #define CPSW_SYSCTL_COUNT 34 42 43 #ifdef CPSW_ETHERSWITCH 44 #define CPSW_CPU_PORT 0 45 #define CPSW_PORTS_MASK 0x7 46 #define CPSW_VLANS 128 /* Arbitrary number. */ 47 48 struct cpsw_vlangroups { 49 int vid; 50 }; 51 #endif 52 53 struct cpsw_slot { 54 uint32_t bd_offset; /* Offset of corresponding BD within CPPI RAM. */ 55 bus_dmamap_t dmamap; 56 struct ifnet *ifp; 57 struct mbuf *mbuf; 58 STAILQ_ENTRY(cpsw_slot) next; 59 }; 60 STAILQ_HEAD(cpsw_slots, cpsw_slot); 61 62 struct cpsw_queue { 63 struct mtx lock; 64 int running; 65 int teardown; 66 struct cpsw_slots active; 67 struct cpsw_slots avail; 68 uint32_t queue_adds; /* total bufs added */ 69 uint32_t queue_removes; /* total bufs removed */ 70 uint32_t queue_removes_at_last_tick; /* Used by watchdog */ 71 uint32_t queue_restart; 72 int queue_slots; 73 int active_queue_len; 74 int max_active_queue_len; 75 int avail_queue_len; 76 int max_avail_queue_len; 77 int longest_chain; /* Largest # segments in a single packet. */ 78 int hdp_offset; 79 }; 80 81 struct cpsw_port { 82 device_t dev; 83 int phy; 84 int vlan; 85 }; 86 87 struct cpsw_softc { 88 device_t dev; 89 int active_slave; 90 int debug; 91 int dualemac; 92 int rx_batch; 93 phandle_t node; 94 struct bintime attach_uptime; /* system uptime when attach happened. */ 95 struct cpsw_port port[2]; 96 unsigned coal_us; 97 98 /* RX and TX buffer tracking */ 99 struct cpsw_queue rx, tx; 100 101 /* We expect 1 memory resource and 4 interrupts from the device tree. */ 102 int mem_rid; 103 struct resource *mem_res; 104 struct resource *irq_res[CPSW_INTR_COUNT]; 105 void *ih_cookie[CPSW_INTR_COUNT]; 106 107 /* An mbuf full of nulls for TX padding. */ 108 bus_dmamap_t null_mbuf_dmamap; 109 struct mbuf *null_mbuf; 110 bus_addr_t null_mbuf_paddr; 111 112 bus_dma_tag_t mbuf_dtag; 113 114 struct { 115 int resets; 116 int timer; 117 struct callout callout; 118 } watchdog; 119 120 /* 64-bit versions of 32-bit hardware statistics counters */ 121 uint64_t shadow_stats[CPSW_SYSCTL_COUNT]; 122 123 /* CPPI STATERAM has 512 slots for building TX/RX queues. */ 124 /* TODO: Size here supposedly varies with different versions 125 of the controller. Check DaVinci specs and find a good 126 way to adjust this. One option is to have a separate 127 Device Tree parameter for number slots; another option 128 is to calculate it from the memory size in the device tree. */ 129 struct cpsw_slot _slots[CPSW_CPPI_RAM_SIZE / sizeof(struct cpsw_cpdma_bd)]; 130 struct cpsw_slots avail; 131 }; 132 133 struct cpswp_softc { 134 device_t dev; 135 device_t miibus; 136 device_t pdev; 137 int media_status; 138 int unit; 139 int vlan; 140 struct bintime init_uptime; /* system uptime when init happened. */ 141 struct callout mii_callout; 142 struct cpsw_softc *swsc; 143 struct ifnet *ifp; 144 struct mii_data *mii; 145 struct mtx lock; 146 uint32_t if_flags; 147 uint32_t phy; 148 uint32_t phyaccess; 149 uint32_t physel; 150 }; 151 152 #endif /*_IF_CPSWVAR_H */ 153