1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 #ifndef _IF_CPSWREG_H 32 #define _IF_CPSWREG_H 33 34 #define CPSW_SS_OFFSET 0x0000 35 #define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00) 36 #define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08) 37 #define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C) 38 #define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10) 39 #define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24) 40 41 #define CPSW_PORT_OFFSET 0x0100 42 #define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100)) 43 #define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100)) 44 #define CPSW_PORT_P_VLAN(p) (CPSW_PORT_OFFSET + 0x14 + ((p) * 0x100)) 45 #define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100)) 46 #define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C) 47 #define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020) 48 #define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100)) 49 #define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100)) 50 51 #define CPSW_CPDMA_OFFSET 0x0800 52 #define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04) 53 #define CPSW_CPDMA_TX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x08) 54 #define CPSW_CPDMA_RX_CONTROL (CPSW_CPDMA_OFFSET + 0x14) 55 #define CPSW_CPDMA_RX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x18) 56 #define CPSW_CPDMA_SOFT_RESET (CPSW_CPDMA_OFFSET + 0x1c) 57 #define CPSW_CPDMA_DMACONTROL (CPSW_CPDMA_OFFSET + 0x20) 58 #define CPSW_CPDMA_DMASTATUS (CPSW_CPDMA_OFFSET + 0x24) 59 #define CPSW_CPDMA_RX_BUFFER_OFFSET (CPSW_CPDMA_OFFSET + 0x28) 60 #define CPSW_CPDMA_TX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0x80) 61 #define CPSW_CPDMA_TX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0x84) 62 #define CPSW_CPDMA_TX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0x88) 63 #define CPSW_CPDMA_TX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0x8C) 64 #define CPSW_CPDMA_CPDMA_EOI_VECTOR (CPSW_CPDMA_OFFSET + 0x94) 65 #define CPSW_CPDMA_RX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xA0) 66 #define CPSW_CPDMA_RX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xA4) 67 #define CPSW_CPDMA_RX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xA8) 68 #define CPSW_CPDMA_RX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xAc) 69 #define CPSW_CPDMA_RX_INT_THRESH(_ch) (1 << (8 + ((_ch) & 7))) 70 #define CPSW_CPDMA_RX_INT(_ch) (1 << (0 + ((_ch) & 7))) 71 #define CPSW_CPDMA_DMA_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xB0) 72 #define CPSW_CPDMA_DMA_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xB4) 73 #define CPSW_CPDMA_DMA_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xB8) 74 #define CPSW_CPDMA_DMA_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xBC) 75 #define CPSW_CPDMA_RX_PENDTHRESH(p) (CPSW_CPDMA_OFFSET + 0x0c0 + ((p) * 0x04)) 76 #define CPSW_CPDMA_RX_FREEBUFFER(p) (CPSW_CPDMA_OFFSET + 0x0e0 + ((p) * 0x04)) 77 78 #define CPSW_STATS_OFFSET 0x0900 79 80 #define CPSW_STATERAM_OFFSET 0x0A00 81 #define CPSW_CPDMA_TX_HDP(p) (CPSW_STATERAM_OFFSET + 0x00 + ((p) * 0x04)) 82 #define CPSW_CPDMA_RX_HDP(p) (CPSW_STATERAM_OFFSET + 0x20 + ((p) * 0x04)) 83 #define CPSW_CPDMA_TX_CP(p) (CPSW_STATERAM_OFFSET + 0x40 + ((p) * 0x04)) 84 #define CPSW_CPDMA_RX_CP(p) (CPSW_STATERAM_OFFSET + 0x60 + ((p) * 0x04)) 85 86 #define CPSW_CPTS_OFFSET 0x0C00 87 88 #define CPSW_ALE_OFFSET 0x0D00 89 #define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08) 90 #define CPSW_ALE_CTL_ENABLE (1U << 31) 91 #define CPSW_ALE_CTL_CLEAR_TBL (1 << 30) 92 #define CPSW_ALE_CTL_BYPASS (1 << 4) 93 #define CPSW_ALE_CTL_VLAN_AWARE (1 << 2) 94 #define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20) 95 #define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34) 96 #define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38) 97 #define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C) 98 #define ALE_MCAST(_a) ((_a[1] >> 8) & 1) 99 #define ALE_MCAST_FWD (3 << 30) 100 #define ALE_PORTS(_a) ((_a[2] >> 2) & 7) 101 #define ALE_TYPE(_a) ((_a[1] >> 28) & 3) 102 #define ALE_TYPE_ADDR 1 103 #define ALE_TYPE_VLAN 2 104 #define ALE_TYPE_VLAN_ADDR 3 105 #define ALE_VLAN(_a) ((_a[1] >> 16) & 0xfff) 106 #define ALE_VLAN_UNREGFLOOD(_a) ((_a[0] >> 8) & 7) 107 #define ALE_VLAN_REGFLOOD(_a) ((_a[0] >> 16) & 7) 108 #define ALE_VLAN_UNTAG(_a) ((_a[0] >> 24) & 7) 109 #define ALE_VLAN_MEMBERS(_a) (_a[0] & 7) 110 #define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04)) 111 #define ALE_PORTCTL_NO_SA_UPDATE (1 << 5) 112 #define ALE_PORTCTL_NO_LEARN (1 << 4) 113 #define ALE_PORTCTL_INGRESS (1 << 3) 114 #define ALE_PORTCTL_DROP_UNTAGGED (1 << 2) 115 #define ALE_PORTCTL_FORWARD 3 116 #define ALE_PORTCTL_LEARN 2 117 #define ALE_PORTCTL_BLOCKED 1 118 #define ALE_PORTCTL_DISABLED 0 119 120 /* SL1 is at 0x0D80, SL2 is at 0x0DC0 */ 121 #define CPSW_SL_OFFSET 0x0D80 122 #define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04) 123 #define CPSW_SL_MACTL_IFCTL_B (1 << 16) 124 #define CPSW_SL_MACTL_IFCTL_A (1 << 15) 125 #define CPSW_SL_MACTL_GIG (1 << 7) 126 #define CPSW_SL_MACTL_GMII_ENABLE (1 << 5) 127 #define CPSW_SL_MACTL_FULLDUPLEX (1 << 0) 128 #define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08) 129 #define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C) 130 #define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10) 131 #define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18) 132 #define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C) 133 #define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24) 134 135 #define MDIO_OFFSET 0x1000 136 #define MDIOCONTROL (MDIO_OFFSET + 0x04) 137 #define MDIOCTL_ENABLE (1 << 30) 138 #define MDIOCTL_FAULTENB (1 << 18) 139 #define MDIOLINKINTRAW (MDIO_OFFSET + 0x10) 140 #define MDIOLINKINTMASKED (MDIO_OFFSET + 0x14) 141 #define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80) 142 #define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84) 143 #define MDIOUSERACCESS1 (MDIO_OFFSET + 0x88) 144 #define MDIOUSERPHYSEL1 (MDIO_OFFSET + 0x8C) 145 #define MDIO_PHYSEL_LINKINTENB (1 << 6) 146 #define MDIO_PHYACCESS_GO (1U << 31) 147 #define MDIO_PHYACCESS_WRITE (1 << 30) 148 #define MDIO_PHYACCESS_ACK (1 << 29) 149 150 #define CPSW_WR_OFFSET 0x1200 151 #define CPSW_WR_SOFT_RESET (CPSW_WR_OFFSET + 0x04) 152 #define CPSW_WR_CONTROL (CPSW_WR_OFFSET + 0x08) 153 #define CPSW_WR_INT_CONTROL (CPSW_WR_OFFSET + 0x0c) 154 #define CPSW_WR_INT_C0_RX_PULSE (1 << 16) 155 #define CPSW_WR_INT_C0_TX_PULSE (1 << 17) 156 #define CPSW_WR_INT_C1_RX_PULSE (1 << 18) 157 #define CPSW_WR_INT_C1_TX_PULSE (1 << 19) 158 #define CPSW_WR_INT_C2_RX_PULSE (1 << 20) 159 #define CPSW_WR_INT_C2_TX_PULSE (1 << 21) 160 #define CPSW_WR_INT_PACE_EN \ 161 (CPSW_WR_INT_C0_RX_PULSE | CPSW_WR_INT_C0_TX_PULSE | \ 162 CPSW_WR_INT_C1_RX_PULSE | CPSW_WR_INT_C1_TX_PULSE | \ 163 CPSW_WR_INT_C2_RX_PULSE | CPSW_WR_INT_C2_TX_PULSE) 164 #define CPSW_WR_INT_PRESCALE_MASK 0xfff 165 #define CPSW_WR_C_RX_THRESH_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x10) 166 #define CPSW_WR_C_RX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x14) 167 #define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18) 168 #define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C) 169 #define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40) 170 #define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44) 171 #define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48) 172 #define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C) 173 #define CPSW_WR_C_MISC_EVNT_PEND (1 << 4) 174 #define CPSW_WR_C_MISC_STAT_PEND (1 << 3) 175 #define CPSW_WR_C_MISC_HOST_PEND (1 << 2) 176 #define CPSW_WR_C_MISC_MDIOLINK (1 << 1) 177 #define CPSW_WR_C_MISC_MDIOUSER (1 << 0) 178 #define CPSW_WR_C_RX_IMAX(p) (CPSW_WR_OFFSET + (0x08 * (p)) + 0x70) 179 #define CPSW_WR_C_TX_IMAX(p) (CPSW_WR_OFFSET + (0x08 * (p)) + 0x74) 180 #define CPSW_WR_C_IMAX_MASK 0x3f 181 #define CPSW_WR_C_IMAX_MAX 63 182 #define CPSW_WR_C_IMAX_MIN 2 183 #define CPSW_WR_C_IMAX_US_MAX 500 184 #define CPSW_WR_C_IMAX_US_MIN 16 185 186 #define CPSW_CPPI_RAM_OFFSET 0x2000 187 #define CPSW_CPPI_RAM_SIZE 0x2000 188 189 #define CPSW_MEMWINDOW_SIZE 0x4000 190 191 #define CPDMA_BD_SOP (1 << 15) 192 #define CPDMA_BD_EOP (1 << 14) 193 #define CPDMA_BD_OWNER (1 << 13) 194 #define CPDMA_BD_EOQ (1 << 12) 195 #define CPDMA_BD_TDOWNCMPLT (1 << 11) 196 #define CPDMA_BD_PASS_CRC (1 << 10) 197 #define CPDMA_BD_PKT_ERR_MASK (3 << 4) 198 #define CPDMA_BD_TO_PORT (1 << 4) 199 #define CPDMA_BD_PORT_MASK 3 200 201 struct cpsw_cpdma_bd { 202 volatile uint32_t next; 203 volatile uint32_t bufptr; 204 volatile uint16_t buflen; 205 volatile uint16_t bufoff; 206 volatile uint16_t pktlen; 207 volatile uint16_t flags; 208 }; 209 210 #endif /*_IF_CPSWREG_H */ 211