1 /*- 2 * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _IF_CPSWREG_H 30 #define _IF_CPSWREG_H 31 32 #define CPSW_SS_OFFSET 0x0000 33 #define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00) 34 #define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08) 35 #define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C) 36 #define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10) 37 #define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24) 38 39 #define CPSW_PORT_OFFSET 0x0100 40 #define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100)) 41 #define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100)) 42 #define CPSW_PORT_P_VLAN(p) (CPSW_PORT_OFFSET + 0x14 + ((p) * 0x100)) 43 #define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100)) 44 #define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C) 45 #define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020) 46 #define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100)) 47 #define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100)) 48 49 #define CPSW_CPDMA_OFFSET 0x0800 50 #define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04) 51 #define CPSW_CPDMA_TX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x08) 52 #define CPSW_CPDMA_RX_CONTROL (CPSW_CPDMA_OFFSET + 0x14) 53 #define CPSW_CPDMA_RX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x18) 54 #define CPSW_CPDMA_SOFT_RESET (CPSW_CPDMA_OFFSET + 0x1c) 55 #define CPSW_CPDMA_DMACONTROL (CPSW_CPDMA_OFFSET + 0x20) 56 #define CPSW_CPDMA_DMASTATUS (CPSW_CPDMA_OFFSET + 0x24) 57 #define CPSW_CPDMA_RX_BUFFER_OFFSET (CPSW_CPDMA_OFFSET + 0x28) 58 #define CPSW_CPDMA_TX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0x80) 59 #define CPSW_CPDMA_TX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0x84) 60 #define CPSW_CPDMA_TX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0x88) 61 #define CPSW_CPDMA_TX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0x8C) 62 #define CPSW_CPDMA_CPDMA_EOI_VECTOR (CPSW_CPDMA_OFFSET + 0x94) 63 #define CPSW_CPDMA_RX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xA0) 64 #define CPSW_CPDMA_RX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xA4) 65 #define CPSW_CPDMA_RX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xA8) 66 #define CPSW_CPDMA_RX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xAc) 67 #define CPSW_CPDMA_RX_INT_THRESH(_ch) (1 << (8 + ((_ch) & 7))) 68 #define CPSW_CPDMA_RX_INT(_ch) (1 << (0 + ((_ch) & 7))) 69 #define CPSW_CPDMA_DMA_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xB0) 70 #define CPSW_CPDMA_DMA_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xB4) 71 #define CPSW_CPDMA_DMA_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xB8) 72 #define CPSW_CPDMA_DMA_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xBC) 73 #define CPSW_CPDMA_RX_PENDTHRESH(p) (CPSW_CPDMA_OFFSET + 0x0c0 + ((p) * 0x04)) 74 #define CPSW_CPDMA_RX_FREEBUFFER(p) (CPSW_CPDMA_OFFSET + 0x0e0 + ((p) * 0x04)) 75 76 #define CPSW_STATS_OFFSET 0x0900 77 78 #define CPSW_STATERAM_OFFSET 0x0A00 79 #define CPSW_CPDMA_TX_HDP(p) (CPSW_STATERAM_OFFSET + 0x00 + ((p) * 0x04)) 80 #define CPSW_CPDMA_RX_HDP(p) (CPSW_STATERAM_OFFSET + 0x20 + ((p) * 0x04)) 81 #define CPSW_CPDMA_TX_CP(p) (CPSW_STATERAM_OFFSET + 0x40 + ((p) * 0x04)) 82 #define CPSW_CPDMA_RX_CP(p) (CPSW_STATERAM_OFFSET + 0x60 + ((p) * 0x04)) 83 84 #define CPSW_CPTS_OFFSET 0x0C00 85 86 #define CPSW_ALE_OFFSET 0x0D00 87 #define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08) 88 #define CPSW_ALE_CTL_ENABLE (1U << 31) 89 #define CPSW_ALE_CTL_CLEAR_TBL (1 << 30) 90 #define CPSW_ALE_CTL_BYPASS (1 << 4) 91 #define CPSW_ALE_CTL_VLAN_AWARE (1 << 2) 92 #define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20) 93 #define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34) 94 #define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38) 95 #define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C) 96 #define ALE_MCAST(_a) ((_a[1] >> 8) & 1) 97 #define ALE_MCAST_FWD (3 << 30) 98 #define ALE_PORTS(_a) ((_a[2] >> 2) & 7) 99 #define ALE_TYPE(_a) ((_a[1] >> 28) & 3) 100 #define ALE_TYPE_ADDR 1 101 #define ALE_TYPE_VLAN 2 102 #define ALE_TYPE_VLAN_ADDR 3 103 #define ALE_VLAN(_a) ((_a[1] >> 16) & 0xfff) 104 #define ALE_VLAN_UNREGFLOOD(_a) ((_a[0] >> 8) & 7) 105 #define ALE_VLAN_REGFLOOD(_a) ((_a[0] >> 16) & 7) 106 #define ALE_VLAN_UNTAG(_a) ((_a[0] >> 24) & 7) 107 #define ALE_VLAN_MEMBERS(_a) (_a[0] & 7) 108 #define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04)) 109 #define ALE_PORTCTL_NO_SA_UPDATE (1 << 5) 110 #define ALE_PORTCTL_NO_LEARN (1 << 4) 111 #define ALE_PORTCTL_INGRESS (1 << 3) 112 #define ALE_PORTCTL_DROP_UNTAGGED (1 << 2) 113 #define ALE_PORTCTL_FORWARD 3 114 #define ALE_PORTCTL_LEARN 2 115 #define ALE_PORTCTL_BLOCKED 1 116 #define ALE_PORTCTL_DISABLED 0 117 118 /* SL1 is at 0x0D80, SL2 is at 0x0DC0 */ 119 #define CPSW_SL_OFFSET 0x0D80 120 #define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04) 121 #define CPSW_SL_MACTL_IFCTL_B (1 << 16) 122 #define CPSW_SL_MACTL_IFCTL_A (1 << 15) 123 #define CPSW_SL_MACTL_GIG (1 << 7) 124 #define CPSW_SL_MACTL_GMII_ENABLE (1 << 5) 125 #define CPSW_SL_MACTL_FULLDUPLEX (1 << 0) 126 #define CPSW_SL_MACSTATUS(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x08) 127 #define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C) 128 #define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10) 129 #define CPSW_SL_RX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x18) 130 #define CPSW_SL_TX_PAUSE(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x1C) 131 #define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24) 132 133 #define MDIO_OFFSET 0x1000 134 #define MDIOCONTROL (MDIO_OFFSET + 0x04) 135 #define MDIOCTL_ENABLE (1 << 30) 136 #define MDIOCTL_FAULTENB (1 << 18) 137 #define MDIOLINKINTRAW (MDIO_OFFSET + 0x10) 138 #define MDIOLINKINTMASKED (MDIO_OFFSET + 0x14) 139 #define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80) 140 #define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84) 141 #define MDIOUSERACCESS1 (MDIO_OFFSET + 0x88) 142 #define MDIOUSERPHYSEL1 (MDIO_OFFSET + 0x8C) 143 #define MDIO_PHYSEL_LINKINTENB (1 << 6) 144 #define MDIO_PHYACCESS_GO (1U << 31) 145 #define MDIO_PHYACCESS_WRITE (1 << 30) 146 #define MDIO_PHYACCESS_ACK (1 << 29) 147 148 #define CPSW_WR_OFFSET 0x1200 149 #define CPSW_WR_SOFT_RESET (CPSW_WR_OFFSET + 0x04) 150 #define CPSW_WR_CONTROL (CPSW_WR_OFFSET + 0x08) 151 #define CPSW_WR_INT_CONTROL (CPSW_WR_OFFSET + 0x0c) 152 #define CPSW_WR_INT_C0_RX_PULSE (1 << 16) 153 #define CPSW_WR_INT_C0_TX_PULSE (1 << 17) 154 #define CPSW_WR_INT_C1_RX_PULSE (1 << 18) 155 #define CPSW_WR_INT_C1_TX_PULSE (1 << 19) 156 #define CPSW_WR_INT_C2_RX_PULSE (1 << 20) 157 #define CPSW_WR_INT_C2_TX_PULSE (1 << 21) 158 #define CPSW_WR_INT_PACE_EN \ 159 (CPSW_WR_INT_C0_RX_PULSE | CPSW_WR_INT_C0_TX_PULSE | \ 160 CPSW_WR_INT_C1_RX_PULSE | CPSW_WR_INT_C1_TX_PULSE | \ 161 CPSW_WR_INT_C2_RX_PULSE | CPSW_WR_INT_C2_TX_PULSE) 162 #define CPSW_WR_INT_PRESCALE_MASK 0xfff 163 #define CPSW_WR_C_RX_THRESH_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x10) 164 #define CPSW_WR_C_RX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x14) 165 #define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18) 166 #define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C) 167 #define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40) 168 #define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44) 169 #define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48) 170 #define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C) 171 #define CPSW_WR_C_MISC_EVNT_PEND (1 << 4) 172 #define CPSW_WR_C_MISC_STAT_PEND (1 << 3) 173 #define CPSW_WR_C_MISC_HOST_PEND (1 << 2) 174 #define CPSW_WR_C_MISC_MDIOLINK (1 << 1) 175 #define CPSW_WR_C_MISC_MDIOUSER (1 << 0) 176 #define CPSW_WR_C_RX_IMAX(p) (CPSW_WR_OFFSET + (0x08 * (p)) + 0x70) 177 #define CPSW_WR_C_TX_IMAX(p) (CPSW_WR_OFFSET + (0x08 * (p)) + 0x74) 178 #define CPSW_WR_C_IMAX_MASK 0x3f 179 #define CPSW_WR_C_IMAX_MAX 63 180 #define CPSW_WR_C_IMAX_MIN 2 181 #define CPSW_WR_C_IMAX_US_MAX 500 182 #define CPSW_WR_C_IMAX_US_MIN 16 183 184 #define CPSW_CPPI_RAM_OFFSET 0x2000 185 #define CPSW_CPPI_RAM_SIZE 0x2000 186 187 #define CPSW_MEMWINDOW_SIZE 0x4000 188 189 #define CPDMA_BD_SOP (1 << 15) 190 #define CPDMA_BD_EOP (1 << 14) 191 #define CPDMA_BD_OWNER (1 << 13) 192 #define CPDMA_BD_EOQ (1 << 12) 193 #define CPDMA_BD_TDOWNCMPLT (1 << 11) 194 #define CPDMA_BD_PASS_CRC (1 << 10) 195 #define CPDMA_BD_PKT_ERR_MASK (3 << 4) 196 #define CPDMA_BD_TO_PORT (1 << 4) 197 #define CPDMA_BD_PORT_MASK 3 198 199 struct cpsw_cpdma_bd { 200 volatile uint32_t next; 201 volatile uint32_t bufptr; 202 volatile uint16_t buflen; 203 volatile uint16_t bufoff; 204 volatile uint16_t pktlen; 205 volatile uint16_t flags; 206 }; 207 208 #endif /*_IF_CPSWREG_H */ 209