xref: /freebsd/sys/arm/ti/cpsw/if_cpsw.c (revision b78d94bd05582cc23438a9a55dbc6203786261aa)
1 /*-
2  * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
3  * Copyright (c) 2016 Rubicon Communications, LLC (Netgate)
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 /*
29  * TI Common Platform Ethernet Switch (CPSW) Driver
30  * Found in TI8148 "DaVinci" and AM335x "Sitara" SoCs.
31  *
32  * This controller is documented in the AM335x Technical Reference
33  * Manual, in the TMS320DM814x DaVinci Digital Video Processors TRM
34  * and in the TMS320C6452 3 Port Switch Ethernet Subsystem TRM.
35  *
36  * It is basically a single Ethernet port (port 0) wired internally to
37  * a 3-port store-and-forward switch connected to two independent
38  * "sliver" controllers (port 1 and port 2).  You can operate the
39  * controller in a variety of different ways by suitably configuring
40  * the slivers and the Address Lookup Engine (ALE) that routes packets
41  * between the ports.
42  *
43  * This code was developed and tested on a BeagleBone with
44  * an AM335x SoC.
45  */
46 
47 #include <sys/cdefs.h>
48 __FBSDID("$FreeBSD$");
49 
50 #include "opt_cpsw.h"
51 
52 #include <sys/param.h>
53 #include <sys/bus.h>
54 #include <sys/kernel.h>
55 #include <sys/lock.h>
56 #include <sys/mbuf.h>
57 #include <sys/module.h>
58 #include <sys/mutex.h>
59 #include <sys/rman.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/sysctl.h>
63 
64 #include <machine/bus.h>
65 #include <machine/resource.h>
66 #include <machine/stdarg.h>
67 
68 #include <net/ethernet.h>
69 #include <net/bpf.h>
70 #include <net/if.h>
71 #include <net/if_dl.h>
72 #include <net/if_media.h>
73 #include <net/if_types.h>
74 
75 #include <arm/ti/ti_scm.h>
76 #include <arm/ti/am335x/am335x_scm.h>
77 
78 #include <dev/mii/mii.h>
79 #include <dev/mii/miivar.h>
80 
81 #include <dev/ofw/ofw_bus.h>
82 #include <dev/ofw/ofw_bus_subr.h>
83 
84 #ifdef CPSW_ETHERSWITCH
85 #include <dev/etherswitch/etherswitch.h>
86 #include "etherswitch_if.h"
87 #endif
88 
89 #include "if_cpswreg.h"
90 #include "if_cpswvar.h"
91 
92 #include "miibus_if.h"
93 
94 /* Device probe/attach/detach. */
95 static int cpsw_probe(device_t);
96 static int cpsw_attach(device_t);
97 static int cpsw_detach(device_t);
98 static int cpswp_probe(device_t);
99 static int cpswp_attach(device_t);
100 static int cpswp_detach(device_t);
101 
102 static phandle_t cpsw_get_node(device_t, device_t);
103 
104 /* Device Init/shutdown. */
105 static int cpsw_shutdown(device_t);
106 static void cpswp_init(void *);
107 static void cpswp_init_locked(void *);
108 static void cpswp_stop_locked(struct cpswp_softc *);
109 
110 /* Device Suspend/Resume. */
111 static int cpsw_suspend(device_t);
112 static int cpsw_resume(device_t);
113 
114 /* Ioctl. */
115 static int cpswp_ioctl(struct ifnet *, u_long command, caddr_t data);
116 
117 static int cpswp_miibus_readreg(device_t, int phy, int reg);
118 static int cpswp_miibus_writereg(device_t, int phy, int reg, int value);
119 static void cpswp_miibus_statchg(device_t);
120 
121 /* Send/Receive packets. */
122 static void cpsw_intr_rx(void *arg);
123 static struct mbuf *cpsw_rx_dequeue(struct cpsw_softc *);
124 static void cpsw_rx_enqueue(struct cpsw_softc *);
125 static void cpswp_start(struct ifnet *);
126 static void cpsw_intr_tx(void *);
127 static void cpswp_tx_enqueue(struct cpswp_softc *);
128 static int cpsw_tx_dequeue(struct cpsw_softc *);
129 
130 /* Misc interrupts and watchdog. */
131 static void cpsw_intr_rx_thresh(void *);
132 static void cpsw_intr_misc(void *);
133 static void cpswp_tick(void *);
134 static void cpswp_ifmedia_sts(struct ifnet *, struct ifmediareq *);
135 static int cpswp_ifmedia_upd(struct ifnet *);
136 static void cpsw_tx_watchdog(void *);
137 
138 /* ALE support */
139 static void cpsw_ale_read_entry(struct cpsw_softc *, uint16_t, uint32_t *);
140 static void cpsw_ale_write_entry(struct cpsw_softc *, uint16_t, uint32_t *);
141 static int cpsw_ale_mc_entry_set(struct cpsw_softc *, uint8_t, int, uint8_t *);
142 static void cpsw_ale_dump_table(struct cpsw_softc *);
143 static int cpsw_ale_update_vlan_table(struct cpsw_softc *, int, int, int, int,
144 	int);
145 static int cpswp_ale_update_addresses(struct cpswp_softc *, int);
146 
147 /* Statistics and sysctls. */
148 static void cpsw_add_sysctls(struct cpsw_softc *);
149 static void cpsw_stats_collect(struct cpsw_softc *);
150 static int cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS);
151 
152 #ifdef CPSW_ETHERSWITCH
153 static etherswitch_info_t *cpsw_getinfo(device_t);
154 static int cpsw_getport(device_t, etherswitch_port_t *);
155 static int cpsw_setport(device_t, etherswitch_port_t *);
156 static int cpsw_getconf(device_t, etherswitch_conf_t *);
157 static int cpsw_getvgroup(device_t, etherswitch_vlangroup_t *);
158 static int cpsw_setvgroup(device_t, etherswitch_vlangroup_t *);
159 static int cpsw_readreg(device_t, int);
160 static int cpsw_writereg(device_t, int, int);
161 static int cpsw_readphy(device_t, int, int);
162 static int cpsw_writephy(device_t, int, int, int);
163 #endif
164 
165 /*
166  * Arbitrary limit on number of segments in an mbuf to be transmitted.
167  * Packets with more segments than this will be defragmented before
168  * they are queued.
169  */
170 #define	CPSW_TXFRAGS		16
171 
172 /* Shared resources. */
173 static device_method_t cpsw_methods[] = {
174 	/* Device interface */
175 	DEVMETHOD(device_probe,		cpsw_probe),
176 	DEVMETHOD(device_attach,	cpsw_attach),
177 	DEVMETHOD(device_detach,	cpsw_detach),
178 	DEVMETHOD(device_shutdown,	cpsw_shutdown),
179 	DEVMETHOD(device_suspend,	cpsw_suspend),
180 	DEVMETHOD(device_resume,	cpsw_resume),
181 	/* Bus interface */
182 	DEVMETHOD(bus_add_child,	device_add_child_ordered),
183 	/* OFW methods */
184 	DEVMETHOD(ofw_bus_get_node,	cpsw_get_node),
185 #ifdef CPSW_ETHERSWITCH
186 	/* etherswitch interface */
187 	DEVMETHOD(etherswitch_getinfo,	cpsw_getinfo),
188 	DEVMETHOD(etherswitch_readreg,	cpsw_readreg),
189 	DEVMETHOD(etherswitch_writereg,	cpsw_writereg),
190 	DEVMETHOD(etherswitch_readphyreg,	cpsw_readphy),
191 	DEVMETHOD(etherswitch_writephyreg,	cpsw_writephy),
192 	DEVMETHOD(etherswitch_getport,	cpsw_getport),
193 	DEVMETHOD(etherswitch_setport,	cpsw_setport),
194 	DEVMETHOD(etherswitch_getvgroup,	cpsw_getvgroup),
195 	DEVMETHOD(etherswitch_setvgroup,	cpsw_setvgroup),
196 	DEVMETHOD(etherswitch_getconf,	cpsw_getconf),
197 #endif
198 	DEVMETHOD_END
199 };
200 
201 static driver_t cpsw_driver = {
202 	"cpswss",
203 	cpsw_methods,
204 	sizeof(struct cpsw_softc),
205 };
206 
207 static devclass_t cpsw_devclass;
208 
209 DRIVER_MODULE(cpswss, simplebus, cpsw_driver, cpsw_devclass, 0, 0);
210 
211 /* Port/Slave resources. */
212 static device_method_t cpswp_methods[] = {
213 	/* Device interface */
214 	DEVMETHOD(device_probe,		cpswp_probe),
215 	DEVMETHOD(device_attach,	cpswp_attach),
216 	DEVMETHOD(device_detach,	cpswp_detach),
217 	/* MII interface */
218 	DEVMETHOD(miibus_readreg,	cpswp_miibus_readreg),
219 	DEVMETHOD(miibus_writereg,	cpswp_miibus_writereg),
220 	DEVMETHOD(miibus_statchg,	cpswp_miibus_statchg),
221 	DEVMETHOD_END
222 };
223 
224 static driver_t cpswp_driver = {
225 	"cpsw",
226 	cpswp_methods,
227 	sizeof(struct cpswp_softc),
228 };
229 
230 static devclass_t cpswp_devclass;
231 
232 #ifdef CPSW_ETHERSWITCH
233 DRIVER_MODULE(etherswitch, cpswss, etherswitch_driver, etherswitch_devclass, 0, 0);
234 MODULE_DEPEND(cpswss, etherswitch, 1, 1, 1);
235 #endif
236 
237 DRIVER_MODULE(cpsw, cpswss, cpswp_driver, cpswp_devclass, 0, 0);
238 DRIVER_MODULE(miibus, cpsw, miibus_driver, miibus_devclass, 0, 0);
239 MODULE_DEPEND(cpsw, ether, 1, 1, 1);
240 MODULE_DEPEND(cpsw, miibus, 1, 1, 1);
241 
242 #ifdef CPSW_ETHERSWITCH
243 static struct cpsw_vlangroups cpsw_vgroups[CPSW_VLANS];
244 #endif
245 
246 static uint32_t slave_mdio_addr[] = { 0x4a100200, 0x4a100300 };
247 
248 static struct resource_spec irq_res_spec[] = {
249 	{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
250 	{ SYS_RES_IRQ, 1, RF_ACTIVE | RF_SHAREABLE },
251 	{ SYS_RES_IRQ, 2, RF_ACTIVE | RF_SHAREABLE },
252 	{ SYS_RES_IRQ, 3, RF_ACTIVE | RF_SHAREABLE },
253 	{ -1, 0 }
254 };
255 
256 static struct {
257 	void (*cb)(void *);
258 } cpsw_intr_cb[] = {
259 	{ cpsw_intr_rx_thresh },
260 	{ cpsw_intr_rx },
261 	{ cpsw_intr_tx },
262 	{ cpsw_intr_misc },
263 };
264 
265 /* Number of entries here must match size of stats
266  * array in struct cpswp_softc. */
267 static struct cpsw_stat {
268 	int	reg;
269 	char *oid;
270 } cpsw_stat_sysctls[CPSW_SYSCTL_COUNT] = {
271 	{0x00, "GoodRxFrames"},
272 	{0x04, "BroadcastRxFrames"},
273 	{0x08, "MulticastRxFrames"},
274 	{0x0C, "PauseRxFrames"},
275 	{0x10, "RxCrcErrors"},
276 	{0x14, "RxAlignErrors"},
277 	{0x18, "OversizeRxFrames"},
278 	{0x1c, "RxJabbers"},
279 	{0x20, "ShortRxFrames"},
280 	{0x24, "RxFragments"},
281 	{0x30, "RxOctets"},
282 	{0x34, "GoodTxFrames"},
283 	{0x38, "BroadcastTxFrames"},
284 	{0x3c, "MulticastTxFrames"},
285 	{0x40, "PauseTxFrames"},
286 	{0x44, "DeferredTxFrames"},
287 	{0x48, "CollisionsTxFrames"},
288 	{0x4c, "SingleCollisionTxFrames"},
289 	{0x50, "MultipleCollisionTxFrames"},
290 	{0x54, "ExcessiveCollisions"},
291 	{0x58, "LateCollisions"},
292 	{0x5c, "TxUnderrun"},
293 	{0x60, "CarrierSenseErrors"},
294 	{0x64, "TxOctets"},
295 	{0x68, "RxTx64OctetFrames"},
296 	{0x6c, "RxTx65to127OctetFrames"},
297 	{0x70, "RxTx128to255OctetFrames"},
298 	{0x74, "RxTx256to511OctetFrames"},
299 	{0x78, "RxTx512to1024OctetFrames"},
300 	{0x7c, "RxTx1024upOctetFrames"},
301 	{0x80, "NetOctets"},
302 	{0x84, "RxStartOfFrameOverruns"},
303 	{0x88, "RxMiddleOfFrameOverruns"},
304 	{0x8c, "RxDmaOverruns"}
305 };
306 
307 /*
308  * Basic debug support.
309  */
310 
311 static void
312 cpsw_debugf_head(const char *funcname)
313 {
314 	int t = (int)(time_second % (24 * 60 * 60));
315 
316 	printf("%02d:%02d:%02d %s ", t / (60 * 60), (t / 60) % 60, t % 60, funcname);
317 }
318 
319 static void
320 cpsw_debugf(const char *fmt, ...)
321 {
322 	va_list ap;
323 
324 	va_start(ap, fmt);
325 	vprintf(fmt, ap);
326 	va_end(ap);
327 	printf("\n");
328 
329 }
330 
331 #define	CPSW_DEBUGF(_sc, a) do {					\
332 	if ((_sc)->debug) {						\
333 		cpsw_debugf_head(__func__);				\
334 		cpsw_debugf a;						\
335 	}								\
336 } while (0)
337 
338 /*
339  * Locking macros
340  */
341 #define	CPSW_TX_LOCK(sc) do {						\
342 		mtx_assert(&(sc)->rx.lock, MA_NOTOWNED);		\
343 		mtx_lock(&(sc)->tx.lock);				\
344 } while (0)
345 
346 #define	CPSW_TX_UNLOCK(sc)	mtx_unlock(&(sc)->tx.lock)
347 #define	CPSW_TX_LOCK_ASSERT(sc)	mtx_assert(&(sc)->tx.lock, MA_OWNED)
348 
349 #define	CPSW_RX_LOCK(sc) do {						\
350 		mtx_assert(&(sc)->tx.lock, MA_NOTOWNED);		\
351 		mtx_lock(&(sc)->rx.lock);				\
352 } while (0)
353 
354 #define	CPSW_RX_UNLOCK(sc)		mtx_unlock(&(sc)->rx.lock)
355 #define	CPSW_RX_LOCK_ASSERT(sc)	mtx_assert(&(sc)->rx.lock, MA_OWNED)
356 
357 #define CPSW_PORT_LOCK(_sc) do {					\
358 		mtx_assert(&(_sc)->lock, MA_NOTOWNED);			\
359 		mtx_lock(&(_sc)->lock);					\
360 } while (0)
361 
362 #define	CPSW_PORT_UNLOCK(_sc)	mtx_unlock(&(_sc)->lock)
363 #define	CPSW_PORT_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->lock, MA_OWNED)
364 
365 /*
366  * Read/Write macros
367  */
368 #define	cpsw_read_4(_sc, _reg)		bus_read_4((_sc)->mem_res, (_reg))
369 #define	cpsw_write_4(_sc, _reg, _val)					\
370 	bus_write_4((_sc)->mem_res, (_reg), (_val))
371 
372 #define	cpsw_cpdma_bd_offset(i)	(CPSW_CPPI_RAM_OFFSET + ((i)*16))
373 
374 #define	cpsw_cpdma_bd_paddr(sc, slot)					\
375 	BUS_SPACE_PHYSADDR(sc->mem_res, slot->bd_offset)
376 #define	cpsw_cpdma_read_bd(sc, slot, val)				\
377 	bus_read_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4)
378 #define	cpsw_cpdma_write_bd(sc, slot, val)				\
379 	bus_write_region_4(sc->mem_res, slot->bd_offset, (uint32_t *) val, 4)
380 #define	cpsw_cpdma_write_bd_next(sc, slot, next_slot)			\
381 	cpsw_write_4(sc, slot->bd_offset, cpsw_cpdma_bd_paddr(sc, next_slot))
382 #define	cpsw_cpdma_write_bd_flags(sc, slot, val)			\
383 	bus_write_2(sc->mem_res, slot->bd_offset + 14, val)
384 #define	cpsw_cpdma_read_bd_flags(sc, slot)				\
385 	bus_read_2(sc->mem_res, slot->bd_offset + 14)
386 #define	cpsw_write_hdp_slot(sc, queue, slot)				\
387 	cpsw_write_4(sc, (queue)->hdp_offset, cpsw_cpdma_bd_paddr(sc, slot))
388 #define	CP_OFFSET (CPSW_CPDMA_TX_CP(0) - CPSW_CPDMA_TX_HDP(0))
389 #define	cpsw_read_cp(sc, queue)						\
390 	cpsw_read_4(sc, (queue)->hdp_offset + CP_OFFSET)
391 #define	cpsw_write_cp(sc, queue, val)					\
392 	cpsw_write_4(sc, (queue)->hdp_offset + CP_OFFSET, (val))
393 #define	cpsw_write_cp_slot(sc, queue, slot)				\
394 	cpsw_write_cp(sc, queue, cpsw_cpdma_bd_paddr(sc, slot))
395 
396 #if 0
397 /* XXX temporary function versions for debugging. */
398 static void
399 cpsw_write_hdp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot)
400 {
401 	uint32_t reg = queue->hdp_offset;
402 	uint32_t v = cpsw_cpdma_bd_paddr(sc, slot);
403 	CPSW_DEBUGF(("HDP <=== 0x%08x (was 0x%08x)", v, cpsw_read_4(sc, reg)));
404 	cpsw_write_4(sc, reg, v);
405 }
406 
407 static void
408 cpsw_write_cp_slotX(struct cpsw_softc *sc, struct cpsw_queue *queue, struct cpsw_slot *slot)
409 {
410 	uint32_t v = cpsw_cpdma_bd_paddr(sc, slot);
411 	CPSW_DEBUGF(("CP <=== 0x%08x (expecting 0x%08x)", v, cpsw_read_cp(sc, queue)));
412 	cpsw_write_cp(sc, queue, v);
413 }
414 #endif
415 
416 /*
417  * Expanded dump routines for verbose debugging.
418  */
419 static void
420 cpsw_dump_slot(struct cpsw_softc *sc, struct cpsw_slot *slot)
421 {
422 	static const char *flags[] = {"SOP", "EOP", "Owner", "EOQ",
423 	    "TDownCmplt", "PassCRC", "Long", "Short", "MacCtl", "Overrun",
424 	    "PktErr1", "PortEn/PktErr0", "RxVlanEncap", "Port2", "Port1",
425 	    "Port0"};
426 	struct cpsw_cpdma_bd bd;
427 	const char *sep;
428 	int i;
429 
430 	cpsw_cpdma_read_bd(sc, slot, &bd);
431 	printf("BD Addr : 0x%08x   Next  : 0x%08x\n",
432 	    cpsw_cpdma_bd_paddr(sc, slot), bd.next);
433 	printf("  BufPtr: 0x%08x   BufLen: 0x%08x\n", bd.bufptr, bd.buflen);
434 	printf("  BufOff: 0x%08x   PktLen: 0x%08x\n", bd.bufoff, bd.pktlen);
435 	printf("  Flags: ");
436 	sep = "";
437 	for (i = 0; i < 16; ++i) {
438 		if (bd.flags & (1 << (15 - i))) {
439 			printf("%s%s", sep, flags[i]);
440 			sep = ",";
441 		}
442 	}
443 	printf("\n");
444 	if (slot->mbuf) {
445 		printf("  Ether:  %14D\n",
446 		    (char *)(slot->mbuf->m_data), " ");
447 		printf("  Packet: %16D\n",
448 		    (char *)(slot->mbuf->m_data) + 14, " ");
449 	}
450 }
451 
452 #define	CPSW_DUMP_SLOT(cs, slot) do {				\
453 	IF_DEBUG(sc) {						\
454 		cpsw_dump_slot(sc, slot);			\
455 	}							\
456 } while (0)
457 
458 static void
459 cpsw_dump_queue(struct cpsw_softc *sc, struct cpsw_slots *q)
460 {
461 	struct cpsw_slot *slot;
462 	int i = 0;
463 	int others = 0;
464 
465 	STAILQ_FOREACH(slot, q, next) {
466 		if (i > CPSW_TXFRAGS)
467 			++others;
468 		else
469 			cpsw_dump_slot(sc, slot);
470 		++i;
471 	}
472 	if (others)
473 		printf(" ... and %d more.\n", others);
474 	printf("\n");
475 }
476 
477 #define CPSW_DUMP_QUEUE(sc, q) do {				\
478 	IF_DEBUG(sc) {						\
479 		cpsw_dump_queue(sc, q);				\
480 	}							\
481 } while (0)
482 
483 static void
484 cpsw_init_slots(struct cpsw_softc *sc)
485 {
486 	struct cpsw_slot *slot;
487 	int i;
488 
489 	STAILQ_INIT(&sc->avail);
490 
491 	/* Put the slot descriptors onto the global avail list. */
492 	for (i = 0; i < nitems(sc->_slots); i++) {
493 		slot = &sc->_slots[i];
494 		slot->bd_offset = cpsw_cpdma_bd_offset(i);
495 		STAILQ_INSERT_TAIL(&sc->avail, slot, next);
496 	}
497 }
498 
499 static int
500 cpsw_add_slots(struct cpsw_softc *sc, struct cpsw_queue *queue, int requested)
501 {
502 	const int max_slots = nitems(sc->_slots);
503 	struct cpsw_slot *slot;
504 	int i;
505 
506 	if (requested < 0)
507 		requested = max_slots;
508 
509 	for (i = 0; i < requested; ++i) {
510 		slot = STAILQ_FIRST(&sc->avail);
511 		if (slot == NULL)
512 			return (0);
513 		if (bus_dmamap_create(sc->mbuf_dtag, 0, &slot->dmamap)) {
514 			device_printf(sc->dev, "failed to create dmamap\n");
515 			return (ENOMEM);
516 		}
517 		STAILQ_REMOVE_HEAD(&sc->avail, next);
518 		STAILQ_INSERT_TAIL(&queue->avail, slot, next);
519 		++queue->avail_queue_len;
520 		++queue->queue_slots;
521 	}
522 	return (0);
523 }
524 
525 static void
526 cpsw_free_slot(struct cpsw_softc *sc, struct cpsw_slot *slot)
527 {
528 	int error;
529 
530 	if (slot->dmamap) {
531 		if (slot->mbuf)
532 			bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap);
533 		error = bus_dmamap_destroy(sc->mbuf_dtag, slot->dmamap);
534 		KASSERT(error == 0, ("Mapping still active"));
535 		slot->dmamap = NULL;
536 	}
537 	if (slot->mbuf) {
538 		m_freem(slot->mbuf);
539 		slot->mbuf = NULL;
540 	}
541 }
542 
543 static void
544 cpsw_reset(struct cpsw_softc *sc)
545 {
546 	int i;
547 
548 	callout_stop(&sc->watchdog.callout);
549 
550 	/* Reset RMII/RGMII wrapper. */
551 	cpsw_write_4(sc, CPSW_WR_SOFT_RESET, 1);
552 	while (cpsw_read_4(sc, CPSW_WR_SOFT_RESET) & 1)
553 		;
554 
555 	/* Disable TX and RX interrupts for all cores. */
556 	for (i = 0; i < 3; ++i) {
557 		cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(i), 0x00);
558 		cpsw_write_4(sc, CPSW_WR_C_TX_EN(i), 0x00);
559 		cpsw_write_4(sc, CPSW_WR_C_RX_EN(i), 0x00);
560 		cpsw_write_4(sc, CPSW_WR_C_MISC_EN(i), 0x00);
561 	}
562 
563 	/* Reset CPSW subsystem. */
564 	cpsw_write_4(sc, CPSW_SS_SOFT_RESET, 1);
565 	while (cpsw_read_4(sc, CPSW_SS_SOFT_RESET) & 1)
566 		;
567 
568 	/* Reset Sliver port 1 and 2 */
569 	for (i = 0; i < 2; i++) {
570 		/* Reset */
571 		cpsw_write_4(sc, CPSW_SL_SOFT_RESET(i), 1);
572 		while (cpsw_read_4(sc, CPSW_SL_SOFT_RESET(i)) & 1)
573 			;
574 	}
575 
576 	/* Reset DMA controller. */
577 	cpsw_write_4(sc, CPSW_CPDMA_SOFT_RESET, 1);
578 	while (cpsw_read_4(sc, CPSW_CPDMA_SOFT_RESET) & 1)
579 		;
580 
581 	/* Disable TX & RX DMA */
582 	cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 0);
583 	cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 0);
584 
585 	/* Clear all queues. */
586 	for (i = 0; i < 8; i++) {
587 		cpsw_write_4(sc, CPSW_CPDMA_TX_HDP(i), 0);
588 		cpsw_write_4(sc, CPSW_CPDMA_RX_HDP(i), 0);
589 		cpsw_write_4(sc, CPSW_CPDMA_TX_CP(i), 0);
590 		cpsw_write_4(sc, CPSW_CPDMA_RX_CP(i), 0);
591 	}
592 
593 	/* Clear all interrupt Masks */
594 	cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_CLEAR, 0xFFFFFFFF);
595 	cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_CLEAR, 0xFFFFFFFF);
596 }
597 
598 static void
599 cpsw_init(struct cpsw_softc *sc)
600 {
601 	struct cpsw_slot *slot;
602 	uint32_t reg;
603 
604 	/* Disable the interrupt pacing. */
605 	reg = cpsw_read_4(sc, CPSW_WR_INT_CONTROL);
606 	reg &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK);
607 	cpsw_write_4(sc, CPSW_WR_INT_CONTROL, reg);
608 
609 	/* Clear ALE */
610 	cpsw_write_4(sc, CPSW_ALE_CONTROL, CPSW_ALE_CTL_CLEAR_TBL);
611 
612 	/* Enable ALE */
613 	reg = CPSW_ALE_CTL_ENABLE;
614 	if (sc->dualemac)
615 		reg |= CPSW_ALE_CTL_VLAN_AWARE;
616 	cpsw_write_4(sc, CPSW_ALE_CONTROL, reg);
617 
618 	/* Set Host Port Mapping. */
619 	cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_TX_PRI_MAP, 0x76543210);
620 	cpsw_write_4(sc, CPSW_PORT_P0_CPDMA_RX_CH_MAP, 0);
621 
622 	/* Initialize ALE: set host port to forwarding(3). */
623 	cpsw_write_4(sc, CPSW_ALE_PORTCTL(0),
624 	    ALE_PORTCTL_INGRESS | ALE_PORTCTL_FORWARD);
625 
626 	cpsw_write_4(sc, CPSW_SS_PTYPE, 0);
627 
628 	/* Enable statistics for ports 0, 1 and 2 */
629 	cpsw_write_4(sc, CPSW_SS_STAT_PORT_EN, 7);
630 
631 	/* Turn off flow control. */
632 	cpsw_write_4(sc, CPSW_SS_FLOW_CONTROL, 0);
633 
634 	/* Make IP hdr aligned with 4 */
635 	cpsw_write_4(sc, CPSW_CPDMA_RX_BUFFER_OFFSET, 2);
636 
637 	/* Initialize RX Buffer Descriptors */
638 	cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), 0);
639 	cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), 0);
640 
641 	/* Enable TX & RX DMA */
642 	cpsw_write_4(sc, CPSW_CPDMA_TX_CONTROL, 1);
643 	cpsw_write_4(sc, CPSW_CPDMA_RX_CONTROL, 1);
644 
645 	/* Enable Interrupts for core 0 */
646 	cpsw_write_4(sc, CPSW_WR_C_RX_THRESH_EN(0), 0xFF);
647 	cpsw_write_4(sc, CPSW_WR_C_RX_EN(0), 0xFF);
648 	cpsw_write_4(sc, CPSW_WR_C_TX_EN(0), 0xFF);
649 	cpsw_write_4(sc, CPSW_WR_C_MISC_EN(0), 0x1F);
650 
651 	/* Enable host Error Interrupt */
652 	cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_SET, 3);
653 
654 	/* Enable interrupts for RX and TX on Channel 0 */
655 	cpsw_write_4(sc, CPSW_CPDMA_RX_INTMASK_SET,
656 	    CPSW_CPDMA_RX_INT(0) | CPSW_CPDMA_RX_INT_THRESH(0));
657 	cpsw_write_4(sc, CPSW_CPDMA_TX_INTMASK_SET, 1);
658 
659 	/* Initialze MDIO - ENABLE, PREAMBLE=0, FAULTENB, CLKDIV=0xFF */
660 	/* TODO Calculate MDCLK=CLK/(CLKDIV+1) */
661 	cpsw_write_4(sc, MDIOCONTROL, MDIOCTL_ENABLE | MDIOCTL_FAULTENB | 0xff);
662 
663 	/* Select MII in GMII_SEL, Internal Delay mode */
664 	//ti_scm_reg_write_4(0x650, 0);
665 
666 	/* Initialize active queues. */
667 	slot = STAILQ_FIRST(&sc->tx.active);
668 	if (slot != NULL)
669 		cpsw_write_hdp_slot(sc, &sc->tx, slot);
670 	slot = STAILQ_FIRST(&sc->rx.active);
671 	if (slot != NULL)
672 		cpsw_write_hdp_slot(sc, &sc->rx, slot);
673 	cpsw_rx_enqueue(sc);
674 	cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), sc->rx.active_queue_len);
675 	cpsw_write_4(sc, CPSW_CPDMA_RX_PENDTHRESH(0), CPSW_TXFRAGS);
676 
677 	/* Activate network interface. */
678 	sc->rx.running = 1;
679 	sc->tx.running = 1;
680 	sc->watchdog.timer = 0;
681 	callout_init(&sc->watchdog.callout, 0);
682 	callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc);
683 }
684 
685 /*
686  *
687  * Device Probe, Attach, Detach.
688  *
689  */
690 
691 static int
692 cpsw_probe(device_t dev)
693 {
694 
695 	if (!ofw_bus_status_okay(dev))
696 		return (ENXIO);
697 
698 	if (!ofw_bus_is_compatible(dev, "ti,cpsw"))
699 		return (ENXIO);
700 
701 	device_set_desc(dev, "3-port Switch Ethernet Subsystem");
702 	return (BUS_PROBE_DEFAULT);
703 }
704 
705 static int
706 cpsw_intr_attach(struct cpsw_softc *sc)
707 {
708 	int i;
709 
710 	for (i = 0; i < CPSW_INTR_COUNT; i++) {
711 		if (bus_setup_intr(sc->dev, sc->irq_res[i],
712 		    INTR_TYPE_NET | INTR_MPSAFE, NULL,
713 		    cpsw_intr_cb[i].cb, sc, &sc->ih_cookie[i]) != 0) {
714 			return (-1);
715 		}
716 	}
717 
718 	return (0);
719 }
720 
721 static void
722 cpsw_intr_detach(struct cpsw_softc *sc)
723 {
724 	int i;
725 
726 	for (i = 0; i < CPSW_INTR_COUNT; i++) {
727 		if (sc->ih_cookie[i]) {
728 			bus_teardown_intr(sc->dev, sc->irq_res[i],
729 			    sc->ih_cookie[i]);
730 		}
731 	}
732 }
733 
734 static int
735 cpsw_get_fdt_data(struct cpsw_softc *sc, int port)
736 {
737 	char *name;
738 	int len, phy, vlan;
739 	pcell_t phy_id[3], vlan_id;
740 	phandle_t child;
741 	unsigned long mdio_child_addr;
742 
743 	/* Find any slave with phy_id */
744 	phy = -1;
745 	vlan = -1;
746 	for (child = OF_child(sc->node); child != 0; child = OF_peer(child)) {
747 		if (OF_getprop_alloc(child, "name", 1, (void **)&name) < 0)
748 			continue;
749 		if (sscanf(name, "slave@%lx", &mdio_child_addr) != 1) {
750 			OF_prop_free(name);
751 			continue;
752 		}
753 		OF_prop_free(name);
754 		if (mdio_child_addr != slave_mdio_addr[port])
755 			continue;
756 
757 		len = OF_getproplen(child, "phy_id");
758 		if (len / sizeof(pcell_t) == 2) {
759 			/* Get phy address from fdt */
760 			if (OF_getencprop(child, "phy_id", phy_id, len) > 0)
761 				phy = phy_id[1];
762 		}
763 
764 		len = OF_getproplen(child, "dual_emac_res_vlan");
765 		if (len / sizeof(pcell_t) == 1) {
766 			/* Get phy address from fdt */
767 			if (OF_getencprop(child, "dual_emac_res_vlan",
768 			    &vlan_id, len) > 0) {
769 				vlan = vlan_id;
770 			}
771 		}
772 
773 		break;
774 	}
775 	if (phy == -1)
776 		return (ENXIO);
777 	sc->port[port].phy = phy;
778 	sc->port[port].vlan = vlan;
779 
780 	return (0);
781 }
782 
783 static int
784 cpsw_attach(device_t dev)
785 {
786 	bus_dma_segment_t segs[1];
787 	int error, i, nsegs;
788 	struct cpsw_softc *sc;
789 	uint32_t reg;
790 
791 	sc = device_get_softc(dev);
792 	sc->dev = dev;
793 	sc->node = ofw_bus_get_node(dev);
794 	getbinuptime(&sc->attach_uptime);
795 
796 	if (OF_getencprop(sc->node, "active_slave", &sc->active_slave,
797 	    sizeof(sc->active_slave)) <= 0) {
798 		sc->active_slave = 0;
799 	}
800 	if (sc->active_slave > 1)
801 		sc->active_slave = 1;
802 
803 	if (OF_hasprop(sc->node, "dual_emac"))
804 		sc->dualemac = 1;
805 
806 	for (i = 0; i < CPSW_PORTS; i++) {
807 		if (!sc->dualemac && i != sc->active_slave)
808 			continue;
809 		if (cpsw_get_fdt_data(sc, i) != 0) {
810 			device_printf(dev,
811 			    "failed to get PHY address from FDT\n");
812 			return (ENXIO);
813 		}
814 	}
815 
816 	/* Initialize mutexes */
817 	mtx_init(&sc->tx.lock, device_get_nameunit(dev),
818 	    "cpsw TX lock", MTX_DEF);
819 	mtx_init(&sc->rx.lock, device_get_nameunit(dev),
820 	    "cpsw RX lock", MTX_DEF);
821 
822 	/* Allocate IRQ resources */
823 	error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res);
824 	if (error) {
825 		device_printf(dev, "could not allocate IRQ resources\n");
826 		cpsw_detach(dev);
827 		return (ENXIO);
828 	}
829 
830 	sc->mem_rid = 0;
831 	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
832 	    &sc->mem_rid, RF_ACTIVE);
833 	if (sc->mem_res == NULL) {
834 		device_printf(sc->dev, "failed to allocate memory resource\n");
835 		cpsw_detach(dev);
836 		return (ENXIO);
837 	}
838 
839 	reg = cpsw_read_4(sc, CPSW_SS_IDVER);
840 	device_printf(dev, "CPSW SS Version %d.%d (%d)\n", (reg >> 8 & 0x7),
841 		reg & 0xFF, (reg >> 11) & 0x1F);
842 
843 	cpsw_add_sysctls(sc);
844 
845 	/* Allocate a busdma tag and DMA safe memory for mbufs. */
846 	error = bus_dma_tag_create(
847 		bus_get_dma_tag(sc->dev),	/* parent */
848 		1, 0,				/* alignment, boundary */
849 		BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
850 		BUS_SPACE_MAXADDR,		/* highaddr */
851 		NULL, NULL,			/* filtfunc, filtfuncarg */
852 		MCLBYTES, CPSW_TXFRAGS,		/* maxsize, nsegments */
853 		MCLBYTES, 0,			/* maxsegsz, flags */
854 		NULL, NULL,			/* lockfunc, lockfuncarg */
855 		&sc->mbuf_dtag);		/* dmatag */
856 	if (error) {
857 		device_printf(dev, "bus_dma_tag_create failed\n");
858 		cpsw_detach(dev);
859 		return (error);
860 	}
861 
862 	/* Allocate the null mbuf and pre-sync it. */
863 	sc->null_mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
864 	memset(sc->null_mbuf->m_data, 0, sc->null_mbuf->m_ext.ext_size);
865 	bus_dmamap_create(sc->mbuf_dtag, 0, &sc->null_mbuf_dmamap);
866 	bus_dmamap_load_mbuf_sg(sc->mbuf_dtag, sc->null_mbuf_dmamap,
867 	    sc->null_mbuf, segs, &nsegs, BUS_DMA_NOWAIT);
868 	bus_dmamap_sync(sc->mbuf_dtag, sc->null_mbuf_dmamap,
869 	    BUS_DMASYNC_PREWRITE);
870 	sc->null_mbuf_paddr = segs[0].ds_addr;
871 
872 	cpsw_init_slots(sc);
873 
874 	/* Allocate slots to TX and RX queues. */
875 	STAILQ_INIT(&sc->rx.avail);
876 	STAILQ_INIT(&sc->rx.active);
877 	STAILQ_INIT(&sc->tx.avail);
878 	STAILQ_INIT(&sc->tx.active);
879 	// For now:  128 slots to TX, rest to RX.
880 	// XXX TODO: start with 32/64 and grow dynamically based on demand.
881 	if (cpsw_add_slots(sc, &sc->tx, 128) ||
882 	    cpsw_add_slots(sc, &sc->rx, -1)) {
883 		device_printf(dev, "failed to allocate dmamaps\n");
884 		cpsw_detach(dev);
885 		return (ENOMEM);
886 	}
887 	device_printf(dev, "Initial queue size TX=%d RX=%d\n",
888 	    sc->tx.queue_slots, sc->rx.queue_slots);
889 
890 	sc->tx.hdp_offset = CPSW_CPDMA_TX_HDP(0);
891 	sc->rx.hdp_offset = CPSW_CPDMA_RX_HDP(0);
892 
893 	if (cpsw_intr_attach(sc) == -1) {
894 		device_printf(dev, "failed to setup interrupts\n");
895 		cpsw_detach(dev);
896 		return (ENXIO);
897 	}
898 
899 #ifdef CPSW_ETHERSWITCH
900 	for (i = 0; i < CPSW_VLANS; i++)
901 		cpsw_vgroups[i].vid = -1;
902 #endif
903 
904 	/* Reset the controller. */
905 	cpsw_reset(sc);
906 	cpsw_init(sc);
907 
908 	for (i = 0; i < CPSW_PORTS; i++) {
909 		if (!sc->dualemac && i != sc->active_slave)
910 			continue;
911 		sc->port[i].dev = device_add_child(dev, "cpsw", i);
912 		if (sc->port[i].dev == NULL) {
913 			cpsw_detach(dev);
914 			return (ENXIO);
915 		}
916 	}
917 	bus_generic_probe(dev);
918 	bus_generic_attach(dev);
919 
920 	return (0);
921 }
922 
923 static int
924 cpsw_detach(device_t dev)
925 {
926 	struct cpsw_softc *sc;
927 	int error, i;
928 
929 	bus_generic_detach(dev);
930  	sc = device_get_softc(dev);
931 
932 	for (i = 0; i < CPSW_PORTS; i++) {
933 		if (sc->port[i].dev)
934 			device_delete_child(dev, sc->port[i].dev);
935 	}
936 
937 	if (device_is_attached(dev)) {
938 		callout_stop(&sc->watchdog.callout);
939 		callout_drain(&sc->watchdog.callout);
940 	}
941 
942 	/* Stop and release all interrupts */
943 	cpsw_intr_detach(sc);
944 
945 	/* Free dmamaps and mbufs */
946 	for (i = 0; i < nitems(sc->_slots); ++i)
947 		cpsw_free_slot(sc, &sc->_slots[i]);
948 
949 	/* Free null mbuf. */
950 	if (sc->null_mbuf_dmamap) {
951 		bus_dmamap_unload(sc->mbuf_dtag, sc->null_mbuf_dmamap);
952 		error = bus_dmamap_destroy(sc->mbuf_dtag, sc->null_mbuf_dmamap);
953 		KASSERT(error == 0, ("Mapping still active"));
954 		m_freem(sc->null_mbuf);
955 	}
956 
957 	/* Free DMA tag */
958 	if (sc->mbuf_dtag) {
959 		error = bus_dma_tag_destroy(sc->mbuf_dtag);
960 		KASSERT(error == 0, ("Unable to destroy DMA tag"));
961 	}
962 
963 	/* Free IO memory handler */
964 	if (sc->mem_res != NULL)
965 		bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
966 	bus_release_resources(dev, irq_res_spec, sc->irq_res);
967 
968 	/* Destroy mutexes */
969 	mtx_destroy(&sc->rx.lock);
970 	mtx_destroy(&sc->tx.lock);
971 
972 	/* Detach the switch device, if present. */
973 	error = bus_generic_detach(dev);
974 	if (error != 0)
975 		return (error);
976 
977 	return (device_delete_children(dev));
978 }
979 
980 static phandle_t
981 cpsw_get_node(device_t bus, device_t dev)
982 {
983 
984 	/* Share controller node with port device. */
985 	return (ofw_bus_get_node(bus));
986 }
987 
988 static int
989 cpswp_probe(device_t dev)
990 {
991 
992 	if (device_get_unit(dev) > 1) {
993 		device_printf(dev, "Only two ports are supported.\n");
994 		return (ENXIO);
995 	}
996 	device_set_desc(dev, "Ethernet Switch Port");
997 
998 	return (BUS_PROBE_DEFAULT);
999 }
1000 
1001 static int
1002 cpswp_attach(device_t dev)
1003 {
1004 	int error;
1005 	struct ifnet *ifp;
1006 	struct cpswp_softc *sc;
1007 	uint32_t reg;
1008 	uint8_t mac_addr[ETHER_ADDR_LEN];
1009 
1010 	sc = device_get_softc(dev);
1011 	sc->dev = dev;
1012 	sc->pdev = device_get_parent(dev);
1013 	sc->swsc = device_get_softc(sc->pdev);
1014 	sc->unit = device_get_unit(dev);
1015 	sc->phy = sc->swsc->port[sc->unit].phy;
1016 	sc->vlan = sc->swsc->port[sc->unit].vlan;
1017 	if (sc->swsc->dualemac && sc->vlan == -1)
1018 		sc->vlan = sc->unit + 1;
1019 
1020 	if (sc->unit == 0) {
1021 		sc->physel = MDIOUSERPHYSEL0;
1022 		sc->phyaccess = MDIOUSERACCESS0;
1023 	} else {
1024 		sc->physel = MDIOUSERPHYSEL1;
1025 		sc->phyaccess = MDIOUSERACCESS1;
1026 	}
1027 
1028 	mtx_init(&sc->lock, device_get_nameunit(dev), "cpsw port lock",
1029 	    MTX_DEF);
1030 
1031 	/* Allocate network interface */
1032 	ifp = sc->ifp = if_alloc(IFT_ETHER);
1033 	if (ifp == NULL) {
1034 		cpswp_detach(dev);
1035 		return (ENXIO);
1036 	}
1037 
1038 	if_initname(ifp, device_get_name(sc->dev), sc->unit);
1039 	ifp->if_softc = sc;
1040 	ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST;
1041 	ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_HWCSUM; //FIXME VLAN?
1042 	ifp->if_capenable = ifp->if_capabilities;
1043 
1044 	ifp->if_init = cpswp_init;
1045 	ifp->if_start = cpswp_start;
1046 	ifp->if_ioctl = cpswp_ioctl;
1047 
1048 	ifp->if_snd.ifq_drv_maxlen = sc->swsc->tx.queue_slots;
1049 	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1050 	IFQ_SET_READY(&ifp->if_snd);
1051 
1052 	/* Get high part of MAC address from control module (mac_id[0|1]_hi) */
1053 	ti_scm_reg_read_4(SCM_MAC_ID0_HI + sc->unit * 8, &reg);
1054 	mac_addr[0] = reg & 0xFF;
1055 	mac_addr[1] = (reg >>  8) & 0xFF;
1056 	mac_addr[2] = (reg >> 16) & 0xFF;
1057 	mac_addr[3] = (reg >> 24) & 0xFF;
1058 
1059 	/* Get low part of MAC address from control module (mac_id[0|1]_lo) */
1060 	ti_scm_reg_read_4(SCM_MAC_ID0_LO + sc->unit * 8, &reg);
1061 	mac_addr[4] = reg & 0xFF;
1062 	mac_addr[5] = (reg >>  8) & 0xFF;
1063 
1064 	error = mii_attach(dev, &sc->miibus, ifp, cpswp_ifmedia_upd,
1065 	    cpswp_ifmedia_sts, BMSR_DEFCAPMASK, sc->phy, MII_OFFSET_ANY, 0);
1066 	if (error) {
1067 		device_printf(dev, "attaching PHYs failed\n");
1068 		cpswp_detach(dev);
1069 		return (error);
1070 	}
1071 	sc->mii = device_get_softc(sc->miibus);
1072 
1073 	/* Select PHY and enable interrupts */
1074 	cpsw_write_4(sc->swsc, sc->physel,
1075 	    MDIO_PHYSEL_LINKINTENB | (sc->phy & 0x1F));
1076 
1077 	ether_ifattach(sc->ifp, mac_addr);
1078 	callout_init(&sc->mii_callout, 0);
1079 
1080 	return (0);
1081 }
1082 
1083 static int
1084 cpswp_detach(device_t dev)
1085 {
1086 	struct cpswp_softc *sc;
1087 
1088 	sc = device_get_softc(dev);
1089 	CPSW_DEBUGF(sc->swsc, (""));
1090 	if (device_is_attached(dev)) {
1091 		ether_ifdetach(sc->ifp);
1092 		CPSW_PORT_LOCK(sc);
1093 		cpswp_stop_locked(sc);
1094 		CPSW_PORT_UNLOCK(sc);
1095 		callout_drain(&sc->mii_callout);
1096 	}
1097 
1098 	bus_generic_detach(dev);
1099 
1100 	if_free(sc->ifp);
1101 	mtx_destroy(&sc->lock);
1102 
1103 	return (0);
1104 }
1105 
1106 /*
1107  *
1108  * Init/Shutdown.
1109  *
1110  */
1111 
1112 static int
1113 cpsw_ports_down(struct cpsw_softc *sc)
1114 {
1115 	struct cpswp_softc *psc;
1116 	struct ifnet *ifp1, *ifp2;
1117 
1118 	if (!sc->dualemac)
1119 		return (1);
1120 	psc = device_get_softc(sc->port[0].dev);
1121 	ifp1 = psc->ifp;
1122 	psc = device_get_softc(sc->port[1].dev);
1123 	ifp2 = psc->ifp;
1124 	if ((ifp1->if_flags & IFF_UP) == 0 && (ifp2->if_flags & IFF_UP) == 0)
1125 		return (1);
1126 
1127 	return (0);
1128 }
1129 
1130 static void
1131 cpswp_init(void *arg)
1132 {
1133 	struct cpswp_softc *sc = arg;
1134 
1135 	CPSW_DEBUGF(sc->swsc, (""));
1136 	CPSW_PORT_LOCK(sc);
1137 	cpswp_init_locked(arg);
1138 	CPSW_PORT_UNLOCK(sc);
1139 }
1140 
1141 static void
1142 cpswp_init_locked(void *arg)
1143 {
1144 #ifdef CPSW_ETHERSWITCH
1145 	int i;
1146 #endif
1147 	struct cpswp_softc *sc = arg;
1148 	struct ifnet *ifp;
1149 	uint32_t reg;
1150 
1151 	CPSW_DEBUGF(sc->swsc, (""));
1152 	CPSW_PORT_LOCK_ASSERT(sc);
1153 	ifp = sc->ifp;
1154 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1155 		return;
1156 
1157 	getbinuptime(&sc->init_uptime);
1158 
1159 	if (!sc->swsc->rx.running && !sc->swsc->tx.running) {
1160 		/* Reset the controller. */
1161 		cpsw_reset(sc->swsc);
1162 		cpsw_init(sc->swsc);
1163 	}
1164 
1165 	/* Set Slave Mapping. */
1166 	cpsw_write_4(sc->swsc, CPSW_SL_RX_PRI_MAP(sc->unit), 0x76543210);
1167 	cpsw_write_4(sc->swsc, CPSW_PORT_P_TX_PRI_MAP(sc->unit + 1),
1168 	    0x33221100);
1169 	cpsw_write_4(sc->swsc, CPSW_SL_RX_MAXLEN(sc->unit), 0x5f2);
1170 	/* Enable MAC RX/TX modules. */
1171 	/* TODO: Docs claim that IFCTL_B and IFCTL_A do the same thing? */
1172 	/* Huh?  Docs call bit 0 "Loopback" some places, "FullDuplex" others. */
1173 	reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit));
1174 	reg |= CPSW_SL_MACTL_GMII_ENABLE;
1175 	cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg);
1176 
1177 	/* Initialize ALE: set port to forwarding, initialize addrs */
1178 	cpsw_write_4(sc->swsc, CPSW_ALE_PORTCTL(sc->unit + 1),
1179 	    ALE_PORTCTL_INGRESS | ALE_PORTCTL_FORWARD);
1180 	cpswp_ale_update_addresses(sc, 1);
1181 
1182 	if (sc->swsc->dualemac) {
1183 		/* Set Port VID. */
1184 		cpsw_write_4(sc->swsc, CPSW_PORT_P_VLAN(sc->unit + 1),
1185 		    sc->vlan & 0xfff);
1186 		cpsw_ale_update_vlan_table(sc->swsc, sc->vlan,
1187 		    (1 << (sc->unit + 1)) | (1 << 0), /* Member list */
1188 		    (1 << (sc->unit + 1)) | (1 << 0), /* Untagged egress */
1189 		    (1 << (sc->unit + 1)) | (1 << 0), 0); /* mcast reg flood */
1190 #ifdef CPSW_ETHERSWITCH
1191 		for (i = 0; i < CPSW_VLANS; i++) {
1192 			if (cpsw_vgroups[i].vid != -1)
1193 				continue;
1194 			cpsw_vgroups[i].vid = sc->vlan;
1195 			break;
1196 		}
1197 #endif
1198 	}
1199 
1200 	mii_mediachg(sc->mii);
1201 	callout_reset(&sc->mii_callout, hz, cpswp_tick, sc);
1202 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1203 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1204 }
1205 
1206 static int
1207 cpsw_shutdown(device_t dev)
1208 {
1209 	struct cpsw_softc *sc;
1210 	struct cpswp_softc *psc;
1211 	int i;
1212 
1213  	sc = device_get_softc(dev);
1214 	CPSW_DEBUGF(sc, (""));
1215 	for (i = 0; i < CPSW_PORTS; i++) {
1216 		if (!sc->dualemac && i != sc->active_slave)
1217 			continue;
1218 		psc = device_get_softc(sc->port[i].dev);
1219 		CPSW_PORT_LOCK(psc);
1220 		cpswp_stop_locked(psc);
1221 		CPSW_PORT_UNLOCK(psc);
1222 	}
1223 
1224 	return (0);
1225 }
1226 
1227 static void
1228 cpsw_rx_teardown(struct cpsw_softc *sc)
1229 {
1230 	int i = 0;
1231 
1232 	CPSW_RX_LOCK(sc);
1233 	CPSW_DEBUGF(sc, ("starting RX teardown"));
1234 	sc->rx.teardown = 1;
1235 	cpsw_write_4(sc, CPSW_CPDMA_RX_TEARDOWN, 0);
1236 	CPSW_RX_UNLOCK(sc);
1237 	while (sc->rx.running) {
1238 		if (++i > 10) {
1239 			device_printf(sc->dev,
1240 			    "Unable to cleanly shutdown receiver\n");
1241 			return;
1242 		}
1243 		DELAY(200);
1244 	}
1245 	if (!sc->rx.running)
1246 		CPSW_DEBUGF(sc, ("finished RX teardown (%d retries)", i));
1247 }
1248 
1249 static void
1250 cpsw_tx_teardown(struct cpsw_softc *sc)
1251 {
1252 	int i = 0;
1253 
1254 	CPSW_TX_LOCK(sc);
1255 	CPSW_DEBUGF(sc, ("starting TX teardown"));
1256 	/* Start the TX queue teardown if queue is not empty. */
1257 	if (STAILQ_FIRST(&sc->tx.active) != NULL)
1258 		cpsw_write_4(sc, CPSW_CPDMA_TX_TEARDOWN, 0);
1259 	else
1260 		sc->tx.teardown = 1;
1261 	cpsw_tx_dequeue(sc);
1262 	while (sc->tx.running && ++i < 10) {
1263 		DELAY(200);
1264 		cpsw_tx_dequeue(sc);
1265 	}
1266 	if (sc->tx.running) {
1267 		device_printf(sc->dev,
1268 		    "Unable to cleanly shutdown transmitter\n");
1269 	}
1270 	CPSW_DEBUGF(sc,
1271 	    ("finished TX teardown (%d retries, %d idle buffers)", i,
1272 	     sc->tx.active_queue_len));
1273 	CPSW_TX_UNLOCK(sc);
1274 }
1275 
1276 static void
1277 cpswp_stop_locked(struct cpswp_softc *sc)
1278 {
1279 	struct ifnet *ifp;
1280 	uint32_t reg;
1281 
1282 	ifp = sc->ifp;
1283 	CPSW_DEBUGF(sc->swsc, (""));
1284 	CPSW_PORT_LOCK_ASSERT(sc);
1285 
1286 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1287 		return;
1288 
1289 	/* Disable interface */
1290 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1291 	ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1292 
1293 	/* Stop ticker */
1294 	callout_stop(&sc->mii_callout);
1295 
1296 	/* Tear down the RX/TX queues. */
1297 	if (cpsw_ports_down(sc->swsc)) {
1298 		cpsw_rx_teardown(sc->swsc);
1299 		cpsw_tx_teardown(sc->swsc);
1300 	}
1301 
1302 	/* Stop MAC RX/TX modules. */
1303 	reg = cpsw_read_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit));
1304 	reg &= ~CPSW_SL_MACTL_GMII_ENABLE;
1305 	cpsw_write_4(sc->swsc, CPSW_SL_MACCONTROL(sc->unit), reg);
1306 
1307 	if (cpsw_ports_down(sc->swsc)) {
1308 		/* Capture stats before we reset controller. */
1309 		cpsw_stats_collect(sc->swsc);
1310 
1311 		cpsw_reset(sc->swsc);
1312 		cpsw_init(sc->swsc);
1313 	}
1314 }
1315 
1316 /*
1317  *  Suspend/Resume.
1318  */
1319 
1320 static int
1321 cpsw_suspend(device_t dev)
1322 {
1323 	struct cpsw_softc *sc;
1324 	struct cpswp_softc *psc;
1325 	int i;
1326 
1327 	sc = device_get_softc(dev);
1328 	CPSW_DEBUGF(sc, (""));
1329 	for (i = 0; i < CPSW_PORTS; i++) {
1330 		if (!sc->dualemac && i != sc->active_slave)
1331 			continue;
1332 		psc = device_get_softc(sc->port[i].dev);
1333 		CPSW_PORT_LOCK(psc);
1334 		cpswp_stop_locked(psc);
1335 		CPSW_PORT_UNLOCK(psc);
1336 	}
1337 
1338 	return (0);
1339 }
1340 
1341 static int
1342 cpsw_resume(device_t dev)
1343 {
1344 	struct cpsw_softc *sc;
1345 
1346 	sc  = device_get_softc(dev);
1347 	CPSW_DEBUGF(sc, ("UNIMPLEMENTED"));
1348 
1349 	return (0);
1350 }
1351 
1352 /*
1353  *
1354  *  IOCTL
1355  *
1356  */
1357 
1358 static void
1359 cpsw_set_promisc(struct cpswp_softc *sc, int set)
1360 {
1361 	uint32_t reg;
1362 
1363 	/*
1364 	 * Enabling promiscuous mode requires ALE_BYPASS to be enabled.
1365 	 * That disables the ALE forwarding logic and causes every
1366 	 * packet to be sent only to the host port.  In bypass mode,
1367 	 * the ALE processes host port transmit packets the same as in
1368 	 * normal mode.
1369 	 */
1370 	reg = cpsw_read_4(sc->swsc, CPSW_ALE_CONTROL);
1371 	reg &= ~CPSW_ALE_CTL_BYPASS;
1372 	if (set)
1373 		reg |= CPSW_ALE_CTL_BYPASS;
1374 	cpsw_write_4(sc->swsc, CPSW_ALE_CONTROL, reg);
1375 }
1376 
1377 static void
1378 cpsw_set_allmulti(struct cpswp_softc *sc, int set)
1379 {
1380 	if (set) {
1381 		printf("All-multicast mode unimplemented\n");
1382 	}
1383 }
1384 
1385 static int
1386 cpswp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1387 {
1388 	struct cpswp_softc *sc;
1389 	struct ifreq *ifr;
1390 	int error;
1391 	uint32_t changed;
1392 
1393 	error = 0;
1394 	sc = ifp->if_softc;
1395 	ifr = (struct ifreq *)data;
1396 
1397 	switch (command) {
1398 	case SIOCSIFCAP:
1399 		changed = ifp->if_capenable ^ ifr->ifr_reqcap;
1400 		if (changed & IFCAP_HWCSUM) {
1401 			if ((ifr->ifr_reqcap & changed) & IFCAP_HWCSUM)
1402 				ifp->if_capenable |= IFCAP_HWCSUM;
1403 			else
1404 				ifp->if_capenable &= ~IFCAP_HWCSUM;
1405 		}
1406 		error = 0;
1407 		break;
1408 	case SIOCSIFFLAGS:
1409 		CPSW_PORT_LOCK(sc);
1410 		if (ifp->if_flags & IFF_UP) {
1411 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1412 				changed = ifp->if_flags ^ sc->if_flags;
1413 				CPSW_DEBUGF(sc->swsc,
1414 				    ("SIOCSIFFLAGS: UP & RUNNING (changed=0x%x)",
1415 				    changed));
1416 				if (changed & IFF_PROMISC)
1417 					cpsw_set_promisc(sc,
1418 					    ifp->if_flags & IFF_PROMISC);
1419 				if (changed & IFF_ALLMULTI)
1420 					cpsw_set_allmulti(sc,
1421 					    ifp->if_flags & IFF_ALLMULTI);
1422 			} else {
1423 				CPSW_DEBUGF(sc->swsc,
1424 				    ("SIOCSIFFLAGS: starting up"));
1425 				cpswp_init_locked(sc);
1426 			}
1427 		} else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1428 			CPSW_DEBUGF(sc->swsc, ("SIOCSIFFLAGS: shutting down"));
1429 			cpswp_stop_locked(sc);
1430 		}
1431 
1432 		sc->if_flags = ifp->if_flags;
1433 		CPSW_PORT_UNLOCK(sc);
1434 		break;
1435 	case SIOCADDMULTI:
1436 		cpswp_ale_update_addresses(sc, 0);
1437 		break;
1438 	case SIOCDELMULTI:
1439 		/* Ugh.  DELMULTI doesn't provide the specific address
1440 		   being removed, so the best we can do is remove
1441 		   everything and rebuild it all. */
1442 		cpswp_ale_update_addresses(sc, 1);
1443 		break;
1444 	case SIOCGIFMEDIA:
1445 	case SIOCSIFMEDIA:
1446 		error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, command);
1447 		break;
1448 	default:
1449 		error = ether_ioctl(ifp, command, data);
1450 	}
1451 	return (error);
1452 }
1453 
1454 /*
1455  *
1456  * MIIBUS
1457  *
1458  */
1459 static int
1460 cpswp_miibus_ready(struct cpsw_softc *sc, uint32_t reg)
1461 {
1462 	uint32_t r, retries = CPSW_MIIBUS_RETRIES;
1463 
1464 	while (--retries) {
1465 		r = cpsw_read_4(sc, reg);
1466 		if ((r & MDIO_PHYACCESS_GO) == 0)
1467 			return (1);
1468 		DELAY(CPSW_MIIBUS_DELAY);
1469 	}
1470 
1471 	return (0);
1472 }
1473 
1474 static int
1475 cpswp_miibus_readreg(device_t dev, int phy, int reg)
1476 {
1477 	struct cpswp_softc *sc;
1478 	uint32_t cmd, r;
1479 
1480 	sc = device_get_softc(dev);
1481 	if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) {
1482 		device_printf(dev, "MDIO not ready to read\n");
1483 		return (0);
1484 	}
1485 
1486 	/* Set GO, reg, phy */
1487 	cmd = MDIO_PHYACCESS_GO | (reg & 0x1F) << 21 | (phy & 0x1F) << 16;
1488 	cpsw_write_4(sc->swsc, sc->phyaccess, cmd);
1489 
1490 	if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) {
1491 		device_printf(dev, "MDIO timed out during read\n");
1492 		return (0);
1493 	}
1494 
1495 	r = cpsw_read_4(sc->swsc, sc->phyaccess);
1496 	if ((r & MDIO_PHYACCESS_ACK) == 0) {
1497 		device_printf(dev, "Failed to read from PHY.\n");
1498 		r = 0;
1499 	}
1500 	return (r & 0xFFFF);
1501 }
1502 
1503 static int
1504 cpswp_miibus_writereg(device_t dev, int phy, int reg, int value)
1505 {
1506 	struct cpswp_softc *sc;
1507 	uint32_t cmd;
1508 
1509 	sc = device_get_softc(dev);
1510 	if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) {
1511 		device_printf(dev, "MDIO not ready to write\n");
1512 		return (0);
1513 	}
1514 
1515 	/* Set GO, WRITE, reg, phy, and value */
1516 	cmd = MDIO_PHYACCESS_GO | MDIO_PHYACCESS_WRITE |
1517 	    (reg & 0x1F) << 21 | (phy & 0x1F) << 16 | (value & 0xFFFF);
1518 	cpsw_write_4(sc->swsc, sc->phyaccess, cmd);
1519 
1520 	if (!cpswp_miibus_ready(sc->swsc, sc->phyaccess)) {
1521 		device_printf(dev, "MDIO timed out during write\n");
1522 		return (0);
1523 	}
1524 
1525 	return (0);
1526 }
1527 
1528 static void
1529 cpswp_miibus_statchg(device_t dev)
1530 {
1531 	struct cpswp_softc *sc;
1532 	uint32_t mac_control, reg;
1533 
1534 	sc = device_get_softc(dev);
1535 	CPSW_DEBUGF(sc->swsc, (""));
1536 
1537 	reg = CPSW_SL_MACCONTROL(sc->unit);
1538 	mac_control = cpsw_read_4(sc->swsc, reg);
1539 	mac_control &= ~(CPSW_SL_MACTL_GIG | CPSW_SL_MACTL_IFCTL_A |
1540 	    CPSW_SL_MACTL_IFCTL_B | CPSW_SL_MACTL_FULLDUPLEX);
1541 
1542 	switch(IFM_SUBTYPE(sc->mii->mii_media_active)) {
1543 	case IFM_1000_SX:
1544 	case IFM_1000_LX:
1545 	case IFM_1000_CX:
1546 	case IFM_1000_T:
1547 		mac_control |= CPSW_SL_MACTL_GIG;
1548 		break;
1549 
1550 	case IFM_100_TX:
1551 		mac_control |= CPSW_SL_MACTL_IFCTL_A;
1552 		break;
1553 	}
1554 	if (sc->mii->mii_media_active & IFM_FDX)
1555 		mac_control |= CPSW_SL_MACTL_FULLDUPLEX;
1556 
1557 	cpsw_write_4(sc->swsc, reg, mac_control);
1558 }
1559 
1560 /*
1561  *
1562  * Transmit/Receive Packets.
1563  *
1564  */
1565 static void
1566 cpsw_intr_rx(void *arg)
1567 {
1568 	struct cpsw_softc *sc;
1569 	struct ifnet *ifp;
1570 	struct mbuf *received, *next;
1571 
1572 	sc = (struct cpsw_softc *)arg;
1573 	CPSW_RX_LOCK(sc);
1574 	if (sc->rx.teardown) {
1575 		sc->rx.running = 0;
1576 		sc->rx.teardown = 0;
1577 		cpsw_write_cp(sc, &sc->rx, 0xfffffffc);
1578 	}
1579 	received = cpsw_rx_dequeue(sc);
1580 	cpsw_rx_enqueue(sc);
1581 	cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 1);
1582 	CPSW_RX_UNLOCK(sc);
1583 
1584 	while (received != NULL) {
1585 		next = received->m_nextpkt;
1586 		received->m_nextpkt = NULL;
1587 		ifp = received->m_pkthdr.rcvif;
1588 		(*ifp->if_input)(ifp, received);
1589 		if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1590 		received = next;
1591 	}
1592 }
1593 
1594 static struct mbuf *
1595 cpsw_rx_dequeue(struct cpsw_softc *sc)
1596 {
1597 	struct cpsw_cpdma_bd bd;
1598 	struct cpsw_slot *last, *slot;
1599 	struct cpswp_softc *psc;
1600 	struct mbuf *mb_head, *mb_tail;
1601 	int port, removed = 0;
1602 
1603 	last = NULL;
1604 	mb_head = mb_tail = NULL;
1605 
1606 	/* Pull completed packets off hardware RX queue. */
1607 	while ((slot = STAILQ_FIRST(&sc->rx.active)) != NULL) {
1608 		cpsw_cpdma_read_bd(sc, slot, &bd);
1609 
1610 		/*
1611 		 * Stop on packets still in use by hardware, but do not stop
1612 		 * on packets with the teardown complete flag, they will be
1613 		 * discarded later.
1614 		 */
1615 		if ((bd.flags & (CPDMA_BD_OWNER | CPDMA_BD_TDOWNCMPLT)) ==
1616 		    CPDMA_BD_OWNER)
1617 			break;
1618 
1619 		last = slot;
1620 		++removed;
1621 		STAILQ_REMOVE_HEAD(&sc->rx.active, next);
1622 		STAILQ_INSERT_TAIL(&sc->rx.avail, slot, next);
1623 
1624 		bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTREAD);
1625 		bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap);
1626 
1627 		if (bd.flags & CPDMA_BD_TDOWNCMPLT) {
1628 			CPSW_DEBUGF(sc, ("RX teardown is complete"));
1629 			m_freem(slot->mbuf);
1630 			slot->mbuf = NULL;
1631 			sc->rx.running = 0;
1632 			sc->rx.teardown = 0;
1633 			break;
1634 		}
1635 
1636 		port = (bd.flags & CPDMA_BD_PORT_MASK) - 1;
1637 		KASSERT(port >= 0 && port <= 1,
1638 		    ("patcket received with invalid port: %d", port));
1639 		psc = device_get_softc(sc->port[port].dev);
1640 
1641 		/* Set up mbuf */
1642 		/* TODO: track SOP/EOP bits to assemble a full mbuf
1643 		   out of received fragments. */
1644 		slot->mbuf->m_data += bd.bufoff;
1645 		slot->mbuf->m_len = bd.buflen;
1646 		if (bd.flags & CPDMA_BD_SOP) {
1647 			slot->mbuf->m_pkthdr.len = bd.pktlen;
1648 			slot->mbuf->m_pkthdr.rcvif = psc->ifp;
1649 			slot->mbuf->m_flags |= M_PKTHDR;
1650 		}
1651 		slot->mbuf->m_next = NULL;
1652 		slot->mbuf->m_nextpkt = NULL;
1653 		if (bd.flags & CPDMA_BD_PASS_CRC)
1654 			m_adj(slot->mbuf, -ETHER_CRC_LEN);
1655 
1656 		if ((psc->ifp->if_capenable & IFCAP_RXCSUM) != 0) {
1657 			/* check for valid CRC by looking into pkt_err[5:4] */
1658 			if ((bd.flags &
1659 			    (CPDMA_BD_SOP | CPDMA_BD_PKT_ERR_MASK)) ==
1660 			    CPDMA_BD_SOP) {
1661 				slot->mbuf->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1662 				slot->mbuf->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1663 				slot->mbuf->m_pkthdr.csum_data = 0xffff;
1664 			}
1665 		}
1666 
1667 		/* Add mbuf to packet list to be returned. */
1668 		if (mb_tail) {
1669 			mb_tail->m_nextpkt = slot->mbuf;
1670 		} else {
1671 			mb_head = slot->mbuf;
1672 		}
1673 		mb_tail = slot->mbuf;
1674 		slot->mbuf = NULL;
1675 		if (sc->rx_batch > 0 && sc->rx_batch == removed)
1676 			break;
1677 	}
1678 
1679 	if (removed != 0) {
1680 		cpsw_write_cp_slot(sc, &sc->rx, last);
1681 		sc->rx.queue_removes += removed;
1682 		sc->rx.avail_queue_len += removed;
1683 		sc->rx.active_queue_len -= removed;
1684 		if (sc->rx.avail_queue_len > sc->rx.max_avail_queue_len)
1685 			sc->rx.max_avail_queue_len = sc->rx.avail_queue_len;
1686 		CPSW_DEBUGF(sc, ("Removed %d received packet(s) from RX queue", removed));
1687 	}
1688 
1689 	return (mb_head);
1690 }
1691 
1692 static void
1693 cpsw_rx_enqueue(struct cpsw_softc *sc)
1694 {
1695 	bus_dma_segment_t seg[1];
1696 	struct cpsw_cpdma_bd bd;
1697 	struct cpsw_slot *first_new_slot, *last_old_slot, *next, *slot;
1698 	int error, nsegs, added = 0;
1699 	uint32_t flags;
1700 
1701 	/* Register new mbufs with hardware. */
1702 	first_new_slot = NULL;
1703 	last_old_slot = STAILQ_LAST(&sc->rx.active, cpsw_slot, next);
1704 	while ((slot = STAILQ_FIRST(&sc->rx.avail)) != NULL) {
1705 		if (first_new_slot == NULL)
1706 			first_new_slot = slot;
1707 		if (slot->mbuf == NULL) {
1708 			slot->mbuf = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1709 			if (slot->mbuf == NULL) {
1710 				device_printf(sc->dev,
1711 				    "Unable to fill RX queue\n");
1712 				break;
1713 			}
1714 			slot->mbuf->m_len =
1715 			    slot->mbuf->m_pkthdr.len =
1716 			    slot->mbuf->m_ext.ext_size;
1717 		}
1718 
1719 		error = bus_dmamap_load_mbuf_sg(sc->mbuf_dtag, slot->dmamap,
1720 		    slot->mbuf, seg, &nsegs, BUS_DMA_NOWAIT);
1721 
1722 		KASSERT(nsegs == 1, ("More than one segment (nsegs=%d)", nsegs));
1723 		KASSERT(error == 0, ("DMA error (error=%d)", error));
1724 		if (error != 0 || nsegs != 1) {
1725 			device_printf(sc->dev,
1726 			    "%s: Can't prep RX buf for DMA (nsegs=%d, error=%d)\n",
1727 			    __func__, nsegs, error);
1728 			bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap);
1729 			m_freem(slot->mbuf);
1730 			slot->mbuf = NULL;
1731 			break;
1732 		}
1733 
1734 		bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_PREREAD);
1735 
1736 		/* Create and submit new rx descriptor. */
1737 		if ((next = STAILQ_NEXT(slot, next)) != NULL)
1738 			bd.next = cpsw_cpdma_bd_paddr(sc, next);
1739 		else
1740 			bd.next = 0;
1741 		bd.bufptr = seg->ds_addr;
1742 		bd.bufoff = 0;
1743 		bd.buflen = MCLBYTES - 1;
1744 		bd.pktlen = bd.buflen;
1745 		bd.flags = CPDMA_BD_OWNER;
1746 		cpsw_cpdma_write_bd(sc, slot, &bd);
1747 		++added;
1748 
1749 		STAILQ_REMOVE_HEAD(&sc->rx.avail, next);
1750 		STAILQ_INSERT_TAIL(&sc->rx.active, slot, next);
1751 	}
1752 
1753 	if (added == 0 || first_new_slot == NULL)
1754 		return;
1755 
1756 	CPSW_DEBUGF(sc, ("Adding %d buffers to RX queue", added));
1757 
1758 	/* Link new entries to hardware RX queue. */
1759 	if (last_old_slot == NULL) {
1760 		/* Start a fresh queue. */
1761 		cpsw_write_hdp_slot(sc, &sc->rx, first_new_slot);
1762 	} else {
1763 		/* Add buffers to end of current queue. */
1764 		cpsw_cpdma_write_bd_next(sc, last_old_slot, first_new_slot);
1765 		/* If underrun, restart queue. */
1766 		if ((flags = cpsw_cpdma_read_bd_flags(sc, last_old_slot)) &
1767 		    CPDMA_BD_EOQ) {
1768 			flags &= ~CPDMA_BD_EOQ;
1769 			cpsw_cpdma_write_bd_flags(sc, last_old_slot, flags);
1770 			cpsw_write_hdp_slot(sc, &sc->rx, first_new_slot);
1771 			sc->rx.queue_restart++;
1772 		}
1773 	}
1774 	sc->rx.queue_adds += added;
1775 	sc->rx.avail_queue_len -= added;
1776 	sc->rx.active_queue_len += added;
1777 	cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), added);
1778 	if (sc->rx.active_queue_len > sc->rx.max_active_queue_len) {
1779 		sc->rx.max_active_queue_len = sc->rx.active_queue_len;
1780 	}
1781 }
1782 
1783 static void
1784 cpswp_start(struct ifnet *ifp)
1785 {
1786 	struct cpswp_softc *sc;
1787 
1788 	sc = ifp->if_softc;
1789 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
1790 	    sc->swsc->tx.running == 0) {
1791 		return;
1792 	}
1793 	CPSW_TX_LOCK(sc->swsc);
1794 	cpswp_tx_enqueue(sc);
1795 	cpsw_tx_dequeue(sc->swsc);
1796 	CPSW_TX_UNLOCK(sc->swsc);
1797 }
1798 
1799 static void
1800 cpsw_intr_tx(void *arg)
1801 {
1802 	struct cpsw_softc *sc;
1803 
1804 	sc = (struct cpsw_softc *)arg;
1805 	CPSW_TX_LOCK(sc);
1806 	if (cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)) == 0xfffffffc)
1807 		cpsw_write_cp(sc, &sc->tx, 0xfffffffc);
1808 	cpsw_tx_dequeue(sc);
1809 	cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 2);
1810 	CPSW_TX_UNLOCK(sc);
1811 }
1812 
1813 static void
1814 cpswp_tx_enqueue(struct cpswp_softc *sc)
1815 {
1816 	bus_dma_segment_t segs[CPSW_TXFRAGS];
1817 	struct cpsw_cpdma_bd bd;
1818 	struct cpsw_slot *first_new_slot, *last, *last_old_slot, *next, *slot;
1819 	struct mbuf *m0;
1820 	int error, nsegs, seg, added = 0, padlen;
1821 
1822 	/* Pull pending packets from IF queue and prep them for DMA. */
1823 	last = NULL;
1824 	first_new_slot = NULL;
1825 	last_old_slot = STAILQ_LAST(&sc->swsc->tx.active, cpsw_slot, next);
1826 	while ((slot = STAILQ_FIRST(&sc->swsc->tx.avail)) != NULL) {
1827 		IF_DEQUEUE(&sc->ifp->if_snd, m0);
1828 		if (m0 == NULL)
1829 			break;
1830 
1831 		slot->mbuf = m0;
1832 		padlen = ETHER_MIN_LEN - slot->mbuf->m_pkthdr.len;
1833 		if (padlen < 0)
1834 			padlen = 0;
1835 
1836 		/* Create mapping in DMA memory */
1837 		error = bus_dmamap_load_mbuf_sg(sc->swsc->mbuf_dtag,
1838 		    slot->dmamap, slot->mbuf, segs, &nsegs, BUS_DMA_NOWAIT);
1839 		/* If the packet is too fragmented, try to simplify. */
1840 		if (error == EFBIG ||
1841 		    (error == 0 &&
1842 		    nsegs + (padlen > 0 ? 1 : 0) > sc->swsc->tx.avail_queue_len)) {
1843 			bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap);
1844 			if (padlen > 0) /* May as well add padding. */
1845 				m_append(slot->mbuf, padlen,
1846 				    sc->swsc->null_mbuf->m_data);
1847 			m0 = m_defrag(slot->mbuf, M_NOWAIT);
1848 			if (m0 == NULL) {
1849 				device_printf(sc->dev,
1850 				    "Can't defragment packet; dropping\n");
1851 				m_freem(slot->mbuf);
1852 			} else {
1853 				CPSW_DEBUGF(sc->swsc,
1854 				    ("Requeueing defragmented packet"));
1855 				IF_PREPEND(&sc->ifp->if_snd, m0);
1856 			}
1857 			slot->mbuf = NULL;
1858 			continue;
1859 		}
1860 		if (error != 0) {
1861 			device_printf(sc->dev,
1862 			    "%s: Can't setup DMA (error=%d), dropping packet\n",
1863 			    __func__, error);
1864 			bus_dmamap_unload(sc->swsc->mbuf_dtag, slot->dmamap);
1865 			m_freem(slot->mbuf);
1866 			slot->mbuf = NULL;
1867 			break;
1868 		}
1869 
1870 		bus_dmamap_sync(sc->swsc->mbuf_dtag, slot->dmamap,
1871 				BUS_DMASYNC_PREWRITE);
1872 
1873 		CPSW_DEBUGF(sc->swsc,
1874 		    ("Queueing TX packet: %d segments + %d pad bytes",
1875 		    nsegs, padlen));
1876 
1877 		if (first_new_slot == NULL)
1878 			first_new_slot = slot;
1879 
1880 		/* Link from the previous descriptor. */
1881 		if (last != NULL)
1882 			cpsw_cpdma_write_bd_next(sc->swsc, last, slot);
1883 
1884 		slot->ifp = sc->ifp;
1885 
1886 		/* If there is only one segment, the for() loop
1887 		 * gets skipped and the single buffer gets set up
1888 		 * as both SOP and EOP. */
1889 		if (nsegs > 1) {
1890 			next = STAILQ_NEXT(slot, next);
1891 			bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next);
1892 		} else
1893 			bd.next = 0;
1894 		/* Start by setting up the first buffer. */
1895 		bd.bufptr = segs[0].ds_addr;
1896 		bd.bufoff = 0;
1897 		bd.buflen = segs[0].ds_len;
1898 		bd.pktlen = m_length(slot->mbuf, NULL) + padlen;
1899 		bd.flags =  CPDMA_BD_SOP | CPDMA_BD_OWNER;
1900 		if (sc->swsc->dualemac) {
1901 			bd.flags |= CPDMA_BD_TO_PORT;
1902 			bd.flags |= ((sc->unit + 1) & CPDMA_BD_PORT_MASK);
1903 		}
1904 		for (seg = 1; seg < nsegs; ++seg) {
1905 			/* Save the previous buffer (which isn't EOP) */
1906 			cpsw_cpdma_write_bd(sc->swsc, slot, &bd);
1907 			STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next);
1908 			STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next);
1909 			slot = STAILQ_FIRST(&sc->swsc->tx.avail);
1910 
1911 			/* Setup next buffer (which isn't SOP) */
1912 			if (nsegs > seg + 1) {
1913 				next = STAILQ_NEXT(slot, next);
1914 				bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next);
1915 			} else
1916 				bd.next = 0;
1917 			bd.bufptr = segs[seg].ds_addr;
1918 			bd.bufoff = 0;
1919 			bd.buflen = segs[seg].ds_len;
1920 			bd.pktlen = 0;
1921 			bd.flags = CPDMA_BD_OWNER;
1922 		}
1923 		/* Save the final buffer. */
1924 		if (padlen <= 0)
1925 			bd.flags |= CPDMA_BD_EOP;
1926 		else {
1927 			next = STAILQ_NEXT(slot, next);
1928 			bd.next = cpsw_cpdma_bd_paddr(sc->swsc, next);
1929 		}
1930 		cpsw_cpdma_write_bd(sc->swsc, slot, &bd);
1931 		STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next);
1932 		STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next);
1933 
1934 		if (padlen > 0) {
1935 			slot = STAILQ_FIRST(&sc->swsc->tx.avail);
1936 
1937 			/* Setup buffer of null pad bytes (definitely EOP). */
1938 			bd.next = 0;
1939 			bd.bufptr = sc->swsc->null_mbuf_paddr;
1940 			bd.bufoff = 0;
1941 			bd.buflen = padlen;
1942 			bd.pktlen = 0;
1943 			bd.flags = CPDMA_BD_EOP | CPDMA_BD_OWNER;
1944 			cpsw_cpdma_write_bd(sc->swsc, slot, &bd);
1945 			++nsegs;
1946 
1947 			STAILQ_REMOVE_HEAD(&sc->swsc->tx.avail, next);
1948 			STAILQ_INSERT_TAIL(&sc->swsc->tx.active, slot, next);
1949 		}
1950 
1951 		last = slot;
1952 
1953 		added += nsegs;
1954 		if (nsegs > sc->swsc->tx.longest_chain)
1955 			sc->swsc->tx.longest_chain = nsegs;
1956 
1957 		// TODO: Should we defer the BPF tap until
1958 		// after all packets are queued?
1959 		BPF_MTAP(sc->ifp, m0);
1960 	}
1961 
1962 	if (first_new_slot == NULL)
1963 		return;
1964 
1965 	/* Attach the list of new buffers to the hardware TX queue. */
1966 	if (last_old_slot != NULL &&
1967 	    (cpsw_cpdma_read_bd_flags(sc->swsc, last_old_slot) &
1968 	     CPDMA_BD_EOQ) == 0) {
1969 		/* Add buffers to end of current queue. */
1970 		cpsw_cpdma_write_bd_next(sc->swsc, last_old_slot,
1971 		    first_new_slot);
1972 	} else {
1973 		/* Start a fresh queue. */
1974 		cpsw_write_hdp_slot(sc->swsc, &sc->swsc->tx, first_new_slot);
1975 	}
1976 	sc->swsc->tx.queue_adds += added;
1977 	sc->swsc->tx.avail_queue_len -= added;
1978 	sc->swsc->tx.active_queue_len += added;
1979 	if (sc->swsc->tx.active_queue_len > sc->swsc->tx.max_active_queue_len) {
1980 		sc->swsc->tx.max_active_queue_len = sc->swsc->tx.active_queue_len;
1981 	}
1982 	CPSW_DEBUGF(sc->swsc, ("Queued %d TX packet(s)", added));
1983 }
1984 
1985 static int
1986 cpsw_tx_dequeue(struct cpsw_softc *sc)
1987 {
1988 	struct cpsw_slot *slot, *last_removed_slot = NULL;
1989 	struct cpsw_cpdma_bd bd;
1990 	uint32_t flags, removed = 0;
1991 
1992 	/* Pull completed buffers off the hardware TX queue. */
1993 	slot = STAILQ_FIRST(&sc->tx.active);
1994 	while (slot != NULL) {
1995 		flags = cpsw_cpdma_read_bd_flags(sc, slot);
1996 
1997 		/* TearDown complete is only marked on the SOP for the packet. */
1998 		if ((flags & (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) ==
1999 		    (CPDMA_BD_SOP | CPDMA_BD_TDOWNCMPLT)) {
2000 			sc->tx.teardown = 1;
2001 		}
2002 
2003 		if ((flags & CPDMA_BD_OWNER) != 0 && sc->tx.teardown == 0)
2004 			break; /* Hardware is still using this packet. */
2005 
2006 		bus_dmamap_sync(sc->mbuf_dtag, slot->dmamap, BUS_DMASYNC_POSTWRITE);
2007 		bus_dmamap_unload(sc->mbuf_dtag, slot->dmamap);
2008 		m_freem(slot->mbuf);
2009 		slot->mbuf = NULL;
2010 
2011 		if (slot->ifp) {
2012 			if (sc->tx.teardown == 0)
2013 				if_inc_counter(slot->ifp, IFCOUNTER_OPACKETS, 1);
2014 			else
2015 				if_inc_counter(slot->ifp, IFCOUNTER_OQDROPS, 1);
2016 		}
2017 
2018 		/* Dequeue any additional buffers used by this packet. */
2019 		while (slot != NULL && slot->mbuf == NULL) {
2020 			STAILQ_REMOVE_HEAD(&sc->tx.active, next);
2021 			STAILQ_INSERT_TAIL(&sc->tx.avail, slot, next);
2022 			++removed;
2023 			last_removed_slot = slot;
2024 			slot = STAILQ_FIRST(&sc->tx.active);
2025 		}
2026 
2027 		cpsw_write_cp_slot(sc, &sc->tx, last_removed_slot);
2028 
2029 		/* Restart the TX queue if necessary. */
2030 		cpsw_cpdma_read_bd(sc, last_removed_slot, &bd);
2031 		if (slot != NULL && bd.next != 0 && (bd.flags &
2032 		    (CPDMA_BD_EOP | CPDMA_BD_OWNER | CPDMA_BD_EOQ)) ==
2033 		    (CPDMA_BD_EOP | CPDMA_BD_EOQ)) {
2034 			cpsw_write_hdp_slot(sc, &sc->tx, slot);
2035 			sc->tx.queue_restart++;
2036 			break;
2037 		}
2038 	}
2039 
2040 	if (removed != 0) {
2041 		sc->tx.queue_removes += removed;
2042 		sc->tx.active_queue_len -= removed;
2043 		sc->tx.avail_queue_len += removed;
2044 		if (sc->tx.avail_queue_len > sc->tx.max_avail_queue_len)
2045 			sc->tx.max_avail_queue_len = sc->tx.avail_queue_len;
2046 		CPSW_DEBUGF(sc, ("TX removed %d completed packet(s)", removed));
2047 	}
2048 
2049 	if (sc->tx.teardown && STAILQ_EMPTY(&sc->tx.active)) {
2050 		CPSW_DEBUGF(sc, ("TX teardown is complete"));
2051 		sc->tx.teardown = 0;
2052 		sc->tx.running = 0;
2053 	}
2054 
2055 	return (removed);
2056 }
2057 
2058 /*
2059  *
2060  * Miscellaneous interrupts.
2061  *
2062  */
2063 
2064 static void
2065 cpsw_intr_rx_thresh(void *arg)
2066 {
2067 	struct cpsw_softc *sc;
2068 	struct ifnet *ifp;
2069 	struct mbuf *received, *next;
2070 
2071 	sc = (struct cpsw_softc *)arg;
2072 	CPSW_RX_LOCK(sc);
2073 	received = cpsw_rx_dequeue(sc);
2074 	cpsw_rx_enqueue(sc);
2075 	cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 0);
2076 	CPSW_RX_UNLOCK(sc);
2077 
2078 	while (received != NULL) {
2079 		next = received->m_nextpkt;
2080 		received->m_nextpkt = NULL;
2081 		ifp = received->m_pkthdr.rcvif;
2082 		(*ifp->if_input)(ifp, received);
2083 		if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
2084 		received = next;
2085 	}
2086 }
2087 
2088 static void
2089 cpsw_intr_misc_host_error(struct cpsw_softc *sc)
2090 {
2091 	uint32_t intstat;
2092 	uint32_t dmastat;
2093 	int txerr, rxerr, txchan, rxchan;
2094 
2095 	printf("\n\n");
2096 	device_printf(sc->dev,
2097 	    "HOST ERROR:  PROGRAMMING ERROR DETECTED BY HARDWARE\n");
2098 	printf("\n\n");
2099 	intstat = cpsw_read_4(sc, CPSW_CPDMA_DMA_INTSTAT_MASKED);
2100 	device_printf(sc->dev, "CPSW_CPDMA_DMA_INTSTAT_MASKED=0x%x\n", intstat);
2101 	dmastat = cpsw_read_4(sc, CPSW_CPDMA_DMASTATUS);
2102 	device_printf(sc->dev, "CPSW_CPDMA_DMASTATUS=0x%x\n", dmastat);
2103 
2104 	txerr = (dmastat >> 20) & 15;
2105 	txchan = (dmastat >> 16) & 7;
2106 	rxerr = (dmastat >> 12) & 15;
2107 	rxchan = (dmastat >> 8) & 7;
2108 
2109 	switch (txerr) {
2110 	case 0: break;
2111 	case 1:	printf("SOP error on TX channel %d\n", txchan);
2112 		break;
2113 	case 2:	printf("Ownership bit not set on SOP buffer on TX channel %d\n", txchan);
2114 		break;
2115 	case 3:	printf("Zero Next Buffer but not EOP on TX channel %d\n", txchan);
2116 		break;
2117 	case 4:	printf("Zero Buffer Pointer on TX channel %d\n", txchan);
2118 		break;
2119 	case 5:	printf("Zero Buffer Length on TX channel %d\n", txchan);
2120 		break;
2121 	case 6:	printf("Packet length error on TX channel %d\n", txchan);
2122 		break;
2123 	default: printf("Unknown error on TX channel %d\n", txchan);
2124 		break;
2125 	}
2126 
2127 	if (txerr != 0) {
2128 		printf("CPSW_CPDMA_TX%d_HDP=0x%x\n",
2129 		    txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(txchan)));
2130 		printf("CPSW_CPDMA_TX%d_CP=0x%x\n",
2131 		    txchan, cpsw_read_4(sc, CPSW_CPDMA_TX_CP(txchan)));
2132 		cpsw_dump_queue(sc, &sc->tx.active);
2133 	}
2134 
2135 	switch (rxerr) {
2136 	case 0: break;
2137 	case 2:	printf("Ownership bit not set on RX channel %d\n", rxchan);
2138 		break;
2139 	case 4:	printf("Zero Buffer Pointer on RX channel %d\n", rxchan);
2140 		break;
2141 	case 5:	printf("Zero Buffer Length on RX channel %d\n", rxchan);
2142 		break;
2143 	case 6:	printf("Buffer offset too big on RX channel %d\n", rxchan);
2144 		break;
2145 	default: printf("Unknown RX error on RX channel %d\n", rxchan);
2146 		break;
2147 	}
2148 
2149 	if (rxerr != 0) {
2150 		printf("CPSW_CPDMA_RX%d_HDP=0x%x\n",
2151 		    rxchan, cpsw_read_4(sc,CPSW_CPDMA_RX_HDP(rxchan)));
2152 		printf("CPSW_CPDMA_RX%d_CP=0x%x\n",
2153 		    rxchan, cpsw_read_4(sc, CPSW_CPDMA_RX_CP(rxchan)));
2154 		cpsw_dump_queue(sc, &sc->rx.active);
2155 	}
2156 
2157 	printf("\nALE Table\n");
2158 	cpsw_ale_dump_table(sc);
2159 
2160 	// XXX do something useful here??
2161 	panic("CPSW HOST ERROR INTERRUPT");
2162 
2163 	// Suppress this interrupt in the future.
2164 	cpsw_write_4(sc, CPSW_CPDMA_DMA_INTMASK_CLEAR, intstat);
2165 	printf("XXX HOST ERROR INTERRUPT SUPPRESSED\n");
2166 	// The watchdog will probably reset the controller
2167 	// in a little while.  It will probably fail again.
2168 }
2169 
2170 static void
2171 cpsw_intr_misc(void *arg)
2172 {
2173 	struct cpsw_softc *sc = arg;
2174 	uint32_t stat = cpsw_read_4(sc, CPSW_WR_C_MISC_STAT(0));
2175 
2176 	if (stat & CPSW_WR_C_MISC_EVNT_PEND)
2177 		CPSW_DEBUGF(sc, ("Time sync event interrupt unimplemented"));
2178 	if (stat & CPSW_WR_C_MISC_STAT_PEND)
2179 		cpsw_stats_collect(sc);
2180 	if (stat & CPSW_WR_C_MISC_HOST_PEND)
2181 		cpsw_intr_misc_host_error(sc);
2182 	if (stat & CPSW_WR_C_MISC_MDIOLINK) {
2183 		cpsw_write_4(sc, MDIOLINKINTMASKED,
2184 		    cpsw_read_4(sc, MDIOLINKINTMASKED));
2185 	}
2186 	if (stat & CPSW_WR_C_MISC_MDIOUSER) {
2187 		CPSW_DEBUGF(sc,
2188 		    ("MDIO operation completed interrupt unimplemented"));
2189 	}
2190 	cpsw_write_4(sc, CPSW_CPDMA_CPDMA_EOI_VECTOR, 3);
2191 }
2192 
2193 /*
2194  *
2195  * Periodic Checks and Watchdog.
2196  *
2197  */
2198 
2199 static void
2200 cpswp_tick(void *msc)
2201 {
2202 	struct cpswp_softc *sc = msc;
2203 
2204 	/* Check for media type change */
2205 	mii_tick(sc->mii);
2206 	if (sc->media_status != sc->mii->mii_media.ifm_media) {
2207 		printf("%s: media type changed (ifm_media=%x)\n", __func__,
2208 			sc->mii->mii_media.ifm_media);
2209 		cpswp_ifmedia_upd(sc->ifp);
2210 	}
2211 
2212 	/* Schedule another timeout one second from now */
2213 	callout_reset(&sc->mii_callout, hz, cpswp_tick, sc);
2214 }
2215 
2216 static void
2217 cpswp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2218 {
2219 	struct cpswp_softc *sc;
2220 	struct mii_data *mii;
2221 
2222 	sc = ifp->if_softc;
2223 	CPSW_DEBUGF(sc->swsc, (""));
2224 	CPSW_PORT_LOCK(sc);
2225 
2226 	mii = sc->mii;
2227 	mii_pollstat(mii);
2228 
2229 	ifmr->ifm_active = mii->mii_media_active;
2230 	ifmr->ifm_status = mii->mii_media_status;
2231 	CPSW_PORT_UNLOCK(sc);
2232 }
2233 
2234 static int
2235 cpswp_ifmedia_upd(struct ifnet *ifp)
2236 {
2237 	struct cpswp_softc *sc;
2238 
2239 	sc = ifp->if_softc;
2240 	CPSW_DEBUGF(sc->swsc, (""));
2241 	CPSW_PORT_LOCK(sc);
2242 	mii_mediachg(sc->mii);
2243 	sc->media_status = sc->mii->mii_media.ifm_media;
2244 	CPSW_PORT_UNLOCK(sc);
2245 
2246 	return (0);
2247 }
2248 
2249 static void
2250 cpsw_tx_watchdog_full_reset(struct cpsw_softc *sc)
2251 {
2252 	struct cpswp_softc *psc;
2253 	int i;
2254 
2255 	cpsw_debugf_head("CPSW watchdog");
2256 	device_printf(sc->dev, "watchdog timeout\n");
2257 	printf("CPSW_CPDMA_TX%d_HDP=0x%x\n", 0,
2258 	    cpsw_read_4(sc, CPSW_CPDMA_TX_HDP(0)));
2259 	printf("CPSW_CPDMA_TX%d_CP=0x%x\n", 0,
2260 	    cpsw_read_4(sc, CPSW_CPDMA_TX_CP(0)));
2261 	cpsw_dump_queue(sc, &sc->tx.active);
2262 	for (i = 0; i < CPSW_PORTS; i++) {
2263 		if (!sc->dualemac && i != sc->active_slave)
2264 			continue;
2265 		psc = device_get_softc(sc->port[i].dev);
2266 		CPSW_PORT_LOCK(psc);
2267 		cpswp_stop_locked(psc);
2268 		CPSW_PORT_UNLOCK(psc);
2269 	}
2270 }
2271 
2272 static void
2273 cpsw_tx_watchdog(void *msc)
2274 {
2275 	struct cpsw_softc *sc;
2276 
2277 	sc = msc;
2278 	CPSW_TX_LOCK(sc);
2279 	if (sc->tx.active_queue_len == 0 || !sc->tx.running) {
2280 		sc->watchdog.timer = 0; /* Nothing to do. */
2281 	} else if (sc->tx.queue_removes > sc->tx.queue_removes_at_last_tick) {
2282 		sc->watchdog.timer = 0;  /* Stuff done while we weren't looking. */
2283 	} else if (cpsw_tx_dequeue(sc) > 0) {
2284 		sc->watchdog.timer = 0;  /* We just did something. */
2285 	} else {
2286 		/* There was something to do but it didn't get done. */
2287 		++sc->watchdog.timer;
2288 		if (sc->watchdog.timer > 5) {
2289 			sc->watchdog.timer = 0;
2290 			++sc->watchdog.resets;
2291 			cpsw_tx_watchdog_full_reset(sc);
2292 		}
2293 	}
2294 	sc->tx.queue_removes_at_last_tick = sc->tx.queue_removes;
2295 	CPSW_TX_UNLOCK(sc);
2296 
2297 	/* Schedule another timeout one second from now */
2298 	callout_reset(&sc->watchdog.callout, hz, cpsw_tx_watchdog, sc);
2299 }
2300 
2301 /*
2302  *
2303  * ALE support routines.
2304  *
2305  */
2306 
2307 static void
2308 cpsw_ale_read_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry)
2309 {
2310 	cpsw_write_4(sc, CPSW_ALE_TBLCTL, idx & 1023);
2311 	ale_entry[0] = cpsw_read_4(sc, CPSW_ALE_TBLW0);
2312 	ale_entry[1] = cpsw_read_4(sc, CPSW_ALE_TBLW1);
2313 	ale_entry[2] = cpsw_read_4(sc, CPSW_ALE_TBLW2);
2314 }
2315 
2316 static void
2317 cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry)
2318 {
2319 	cpsw_write_4(sc, CPSW_ALE_TBLW0, ale_entry[0]);
2320 	cpsw_write_4(sc, CPSW_ALE_TBLW1, ale_entry[1]);
2321 	cpsw_write_4(sc, CPSW_ALE_TBLW2, ale_entry[2]);
2322 	cpsw_write_4(sc, CPSW_ALE_TBLCTL, 1 << 31 | (idx & 1023));
2323 }
2324 
2325 static void
2326 cpsw_ale_remove_all_mc_entries(struct cpsw_softc *sc)
2327 {
2328 	int i;
2329 	uint32_t ale_entry[3];
2330 
2331 	/* First four entries are link address and broadcast. */
2332 	for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) {
2333 		cpsw_ale_read_entry(sc, i, ale_entry);
2334 		if ((ALE_TYPE(ale_entry) == ALE_TYPE_ADDR ||
2335 		    ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR) &&
2336 		    ALE_MCAST(ale_entry)  == 1) { /* MCast link addr */
2337 			ale_entry[0] = ale_entry[1] = ale_entry[2] = 0;
2338 			cpsw_ale_write_entry(sc, i, ale_entry);
2339 		}
2340 	}
2341 }
2342 
2343 static int
2344 cpsw_ale_mc_entry_set(struct cpsw_softc *sc, uint8_t portmap, int vlan,
2345 	uint8_t *mac)
2346 {
2347 	int free_index = -1, matching_index = -1, i;
2348 	uint32_t ale_entry[3], ale_type;
2349 
2350 	/* Find a matching entry or a free entry. */
2351 	for (i = 10; i < CPSW_MAX_ALE_ENTRIES; i++) {
2352 		cpsw_ale_read_entry(sc, i, ale_entry);
2353 
2354 		/* Entry Type[61:60] is 0 for free entry */
2355 		if (free_index < 0 && ALE_TYPE(ale_entry) == 0)
2356 			free_index = i;
2357 
2358 		if ((((ale_entry[1] >> 8) & 0xFF) == mac[0]) &&
2359 		    (((ale_entry[1] >> 0) & 0xFF) == mac[1]) &&
2360 		    (((ale_entry[0] >>24) & 0xFF) == mac[2]) &&
2361 		    (((ale_entry[0] >>16) & 0xFF) == mac[3]) &&
2362 		    (((ale_entry[0] >> 8) & 0xFF) == mac[4]) &&
2363 		    (((ale_entry[0] >> 0) & 0xFF) == mac[5])) {
2364 			matching_index = i;
2365 			break;
2366 		}
2367 	}
2368 
2369 	if (matching_index < 0) {
2370 		if (free_index < 0)
2371 			return (ENOMEM);
2372 		i = free_index;
2373 	}
2374 
2375 	if (vlan != -1)
2376 		ale_type = ALE_TYPE_VLAN_ADDR << 28 | vlan << 16;
2377 	else
2378 		ale_type = ALE_TYPE_ADDR << 28;
2379 
2380 	/* Set MAC address */
2381 	ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
2382 	ale_entry[1] = mac[0] << 8 | mac[1];
2383 
2384 	/* Entry type[61:60] and Mcast fwd state[63:62] is fw(3). */
2385 	ale_entry[1] |= ALE_MCAST_FWD | ale_type;
2386 
2387 	/* Set portmask [68:66] */
2388 	ale_entry[2] = (portmap & 7) << 2;
2389 
2390 	cpsw_ale_write_entry(sc, i, ale_entry);
2391 
2392 	return 0;
2393 }
2394 
2395 static void
2396 cpsw_ale_dump_table(struct cpsw_softc *sc) {
2397 	int i;
2398 	uint32_t ale_entry[3];
2399 	for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) {
2400 		cpsw_ale_read_entry(sc, i, ale_entry);
2401 		switch (ALE_TYPE(ale_entry)) {
2402 		case ALE_TYPE_VLAN:
2403 			printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2],
2404 				ale_entry[1], ale_entry[0]);
2405 			printf("type: %u ", ALE_TYPE(ale_entry));
2406 			printf("vlan: %u ", ALE_VLAN(ale_entry));
2407 			printf("untag: %u ", ALE_VLAN_UNTAG(ale_entry));
2408 			printf("reg flood: %u ", ALE_VLAN_REGFLOOD(ale_entry));
2409 			printf("unreg flood: %u ", ALE_VLAN_UNREGFLOOD(ale_entry));
2410 			printf("members: %u ", ALE_VLAN_MEMBERS(ale_entry));
2411 			printf("\n");
2412 			break;
2413 		case ALE_TYPE_ADDR:
2414 		case ALE_TYPE_VLAN_ADDR:
2415 			printf("ALE[%4u] %08x %08x %08x ", i, ale_entry[2],
2416 				ale_entry[1], ale_entry[0]);
2417 			printf("type: %u ", ALE_TYPE(ale_entry));
2418 			printf("mac: %02x:%02x:%02x:%02x:%02x:%02x ",
2419 				(ale_entry[1] >> 8) & 0xFF,
2420 				(ale_entry[1] >> 0) & 0xFF,
2421 				(ale_entry[0] >>24) & 0xFF,
2422 				(ale_entry[0] >>16) & 0xFF,
2423 				(ale_entry[0] >> 8) & 0xFF,
2424 				(ale_entry[0] >> 0) & 0xFF);
2425 			printf(ALE_MCAST(ale_entry) ? "mcast " : "ucast ");
2426 			if (ALE_TYPE(ale_entry) == ALE_TYPE_VLAN_ADDR)
2427 				printf("vlan: %u ", ALE_VLAN(ale_entry));
2428 			printf("port: %u ", ALE_PORTS(ale_entry));
2429 			printf("\n");
2430 			break;
2431 		}
2432 	}
2433 	printf("\n");
2434 }
2435 
2436 static int
2437 cpswp_ale_update_addresses(struct cpswp_softc *sc, int purge)
2438 {
2439 	uint8_t *mac;
2440 	uint32_t ale_entry[3], ale_type, portmask;
2441 	struct ifmultiaddr *ifma;
2442 
2443 	if (sc->swsc->dualemac) {
2444 		ale_type = ALE_TYPE_VLAN_ADDR << 28 | sc->vlan << 16;
2445 		portmask = 1 << (sc->unit + 1) | 1 << 0;
2446 	} else {
2447 		ale_type = ALE_TYPE_ADDR << 28;
2448 		portmask = 7;
2449 	}
2450 
2451 	/*
2452 	 * Route incoming packets for our MAC address to Port 0 (host).
2453 	 * For simplicity, keep this entry at table index 0 for port 1 and
2454 	 * at index 2 for port 2 in the ALE.
2455 	 */
2456         if_addr_rlock(sc->ifp);
2457 	mac = LLADDR((struct sockaddr_dl *)sc->ifp->if_addr->ifa_addr);
2458 	ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
2459 	ale_entry[1] = ale_type | mac[0] << 8 | mac[1]; /* addr entry + mac */
2460 	ale_entry[2] = 0; /* port = 0 */
2461 	cpsw_ale_write_entry(sc->swsc, 0 + 2 * sc->unit, ale_entry);
2462 
2463 	/* Set outgoing MAC Address for slave port. */
2464 	cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_HI(sc->unit + 1),
2465 	    mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]);
2466 	cpsw_write_4(sc->swsc, CPSW_PORT_P_SA_LO(sc->unit + 1),
2467 	    mac[5] << 8 | mac[4]);
2468         if_addr_runlock(sc->ifp);
2469 
2470 	/* Keep the broadcast address at table entry 1 (or 3). */
2471 	ale_entry[0] = 0xffffffff; /* Lower 32 bits of MAC */
2472 	/* ALE_MCAST_FWD, Addr type, upper 16 bits of Mac */
2473 	ale_entry[1] = ALE_MCAST_FWD | ale_type | 0xffff;
2474 	ale_entry[2] = portmask << 2;
2475 	cpsw_ale_write_entry(sc->swsc, 1 + 2 * sc->unit, ale_entry);
2476 
2477 	/* SIOCDELMULTI doesn't specify the particular address
2478 	   being removed, so we have to remove all and rebuild. */
2479 	if (purge)
2480 		cpsw_ale_remove_all_mc_entries(sc->swsc);
2481 
2482         /* Set other multicast addrs desired. */
2483         if_maddr_rlock(sc->ifp);
2484         TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
2485                 if (ifma->ifma_addr->sa_family != AF_LINK)
2486                         continue;
2487 		cpsw_ale_mc_entry_set(sc->swsc, portmask, sc->vlan,
2488 		    LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
2489         }
2490         if_maddr_runlock(sc->ifp);
2491 
2492 	return (0);
2493 }
2494 
2495 static int
2496 cpsw_ale_update_vlan_table(struct cpsw_softc *sc, int vlan, int ports,
2497 	int untag, int mcregflood, int mcunregflood)
2498 {
2499 	int free_index, i, matching_index;
2500 	uint32_t ale_entry[3];
2501 
2502 	free_index = matching_index = -1;
2503 	/* Find a matching entry or a free entry. */
2504 	for (i = 5; i < CPSW_MAX_ALE_ENTRIES; i++) {
2505 		cpsw_ale_read_entry(sc, i, ale_entry);
2506 
2507 		/* Entry Type[61:60] is 0 for free entry */
2508 		if (free_index < 0 && ALE_TYPE(ale_entry) == 0)
2509 			free_index = i;
2510 
2511 		if (ALE_VLAN(ale_entry) == vlan) {
2512 			matching_index = i;
2513 			break;
2514 		}
2515 	}
2516 
2517 	if (matching_index < 0) {
2518 		if (free_index < 0)
2519 			return (-1);
2520 		i = free_index;
2521 	}
2522 
2523 	ale_entry[0] = (untag & 7) << 24 | (mcregflood & 7) << 16 |
2524 	    (mcunregflood & 7) << 8 | (ports & 7);
2525 	ale_entry[1] = ALE_TYPE_VLAN << 28 | vlan << 16;
2526 	ale_entry[2] = 0;
2527 	cpsw_ale_write_entry(sc, i, ale_entry);
2528 
2529 	return (0);
2530 }
2531 
2532 /*
2533  *
2534  * Statistics and Sysctls.
2535  *
2536  */
2537 
2538 #if 0
2539 static void
2540 cpsw_stats_dump(struct cpsw_softc *sc)
2541 {
2542 	int i;
2543 	uint32_t r;
2544 
2545 	for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) {
2546 		r = cpsw_read_4(sc, CPSW_STATS_OFFSET +
2547 		    cpsw_stat_sysctls[i].reg);
2548 		CPSW_DEBUGF(sc, ("%s: %ju + %u = %ju", cpsw_stat_sysctls[i].oid,
2549 		    (intmax_t)sc->shadow_stats[i], r,
2550 		    (intmax_t)sc->shadow_stats[i] + r));
2551 	}
2552 }
2553 #endif
2554 
2555 static void
2556 cpsw_stats_collect(struct cpsw_softc *sc)
2557 {
2558 	int i;
2559 	uint32_t r;
2560 
2561 	CPSW_DEBUGF(sc, ("Controller shadow statistics updated."));
2562 
2563 	for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) {
2564 		r = cpsw_read_4(sc, CPSW_STATS_OFFSET +
2565 		    cpsw_stat_sysctls[i].reg);
2566 		sc->shadow_stats[i] += r;
2567 		cpsw_write_4(sc, CPSW_STATS_OFFSET + cpsw_stat_sysctls[i].reg,
2568 		    r);
2569 	}
2570 }
2571 
2572 static int
2573 cpsw_stats_sysctl(SYSCTL_HANDLER_ARGS)
2574 {
2575 	struct cpsw_softc *sc;
2576 	struct cpsw_stat *stat;
2577 	uint64_t result;
2578 
2579 	sc = (struct cpsw_softc *)arg1;
2580 	stat = &cpsw_stat_sysctls[oidp->oid_number];
2581 	result = sc->shadow_stats[oidp->oid_number];
2582 	result += cpsw_read_4(sc, CPSW_STATS_OFFSET + stat->reg);
2583 	return (sysctl_handle_64(oidp, &result, 0, req));
2584 }
2585 
2586 static int
2587 cpsw_stat_attached(SYSCTL_HANDLER_ARGS)
2588 {
2589 	struct cpsw_softc *sc;
2590 	struct bintime t;
2591 	unsigned result;
2592 
2593 	sc = (struct cpsw_softc *)arg1;
2594 	getbinuptime(&t);
2595 	bintime_sub(&t, &sc->attach_uptime);
2596 	result = t.sec;
2597 	return (sysctl_handle_int(oidp, &result, 0, req));
2598 }
2599 
2600 static int
2601 cpsw_intr_coalesce(SYSCTL_HANDLER_ARGS)
2602 {
2603 	int error;
2604 	struct cpsw_softc *sc;
2605 	uint32_t ctrl, intr_per_ms;
2606 
2607 	sc = (struct cpsw_softc *)arg1;
2608 	error = sysctl_handle_int(oidp, &sc->coal_us, 0, req);
2609 	if (error != 0 || req->newptr == NULL)
2610 		return (error);
2611 
2612 	ctrl = cpsw_read_4(sc, CPSW_WR_INT_CONTROL);
2613 	ctrl &= ~(CPSW_WR_INT_PACE_EN | CPSW_WR_INT_PRESCALE_MASK);
2614 	if (sc->coal_us == 0) {
2615 		/* Disable the interrupt pace hardware. */
2616 		cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl);
2617 		cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), 0);
2618 		cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), 0);
2619 		return (0);
2620 	}
2621 
2622 	if (sc->coal_us > CPSW_WR_C_IMAX_US_MAX)
2623 		sc->coal_us = CPSW_WR_C_IMAX_US_MAX;
2624 	if (sc->coal_us < CPSW_WR_C_IMAX_US_MIN)
2625 		sc->coal_us = CPSW_WR_C_IMAX_US_MIN;
2626 	intr_per_ms = 1000 / sc->coal_us;
2627 	/* Just to make sure... */
2628 	if (intr_per_ms > CPSW_WR_C_IMAX_MAX)
2629 		intr_per_ms = CPSW_WR_C_IMAX_MAX;
2630 	if (intr_per_ms < CPSW_WR_C_IMAX_MIN)
2631 		intr_per_ms = CPSW_WR_C_IMAX_MIN;
2632 
2633 	/* Set the prescale to produce 4us pulses from the 125 Mhz clock. */
2634 	ctrl |= (125 * 4) & CPSW_WR_INT_PRESCALE_MASK;
2635 
2636 	/* Enable the interrupt pace hardware. */
2637 	cpsw_write_4(sc, CPSW_WR_C_RX_IMAX(0), intr_per_ms);
2638 	cpsw_write_4(sc, CPSW_WR_C_TX_IMAX(0), intr_per_ms);
2639 	ctrl |= CPSW_WR_INT_C0_RX_PULSE | CPSW_WR_INT_C0_TX_PULSE;
2640 	cpsw_write_4(sc, CPSW_WR_INT_CONTROL, ctrl);
2641 
2642 	return (0);
2643 }
2644 
2645 static int
2646 cpsw_stat_uptime(SYSCTL_HANDLER_ARGS)
2647 {
2648 	struct cpsw_softc *swsc;
2649 	struct cpswp_softc *sc;
2650 	struct bintime t;
2651 	unsigned result;
2652 
2653 	swsc = arg1;
2654 	sc = device_get_softc(swsc->port[arg2].dev);
2655 	if (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) {
2656 		getbinuptime(&t);
2657 		bintime_sub(&t, &sc->init_uptime);
2658 		result = t.sec;
2659 	} else
2660 		result = 0;
2661 	return (sysctl_handle_int(oidp, &result, 0, req));
2662 }
2663 
2664 static void
2665 cpsw_add_queue_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node,
2666 	struct cpsw_queue *queue)
2667 {
2668 	struct sysctl_oid_list *parent;
2669 
2670 	parent = SYSCTL_CHILDREN(node);
2671 	SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "totalBuffers",
2672 	    CTLFLAG_RD, &queue->queue_slots, 0,
2673 	    "Total buffers currently assigned to this queue");
2674 	SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "activeBuffers",
2675 	    CTLFLAG_RD, &queue->active_queue_len, 0,
2676 	    "Buffers currently registered with hardware controller");
2677 	SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxActiveBuffers",
2678 	    CTLFLAG_RD, &queue->max_active_queue_len, 0,
2679 	    "Max value of activeBuffers since last driver reset");
2680 	SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "availBuffers",
2681 	    CTLFLAG_RD, &queue->avail_queue_len, 0,
2682 	    "Buffers allocated to this queue but not currently "
2683 	    "registered with hardware controller");
2684 	SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "maxAvailBuffers",
2685 	    CTLFLAG_RD, &queue->max_avail_queue_len, 0,
2686 	    "Max value of availBuffers since last driver reset");
2687 	SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalEnqueued",
2688 	    CTLFLAG_RD, &queue->queue_adds, 0,
2689 	    "Total buffers added to queue");
2690 	SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "totalDequeued",
2691 	    CTLFLAG_RD, &queue->queue_removes, 0,
2692 	    "Total buffers removed from queue");
2693 	SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "queueRestart",
2694 	    CTLFLAG_RD, &queue->queue_restart, 0,
2695 	    "Total times the queue has been restarted");
2696 	SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, "longestChain",
2697 	    CTLFLAG_RD, &queue->longest_chain, 0,
2698 	    "Max buffers used for a single packet");
2699 }
2700 
2701 static void
2702 cpsw_add_watchdog_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *node,
2703 	struct cpsw_softc *sc)
2704 {
2705 	struct sysctl_oid_list *parent;
2706 
2707 	parent = SYSCTL_CHILDREN(node);
2708 	SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "resets",
2709 	    CTLFLAG_RD, &sc->watchdog.resets, 0,
2710 	    "Total number of watchdog resets");
2711 }
2712 
2713 static void
2714 cpsw_add_sysctls(struct cpsw_softc *sc)
2715 {
2716 	struct sysctl_ctx_list *ctx;
2717 	struct sysctl_oid *stats_node, *queue_node, *node;
2718 	struct sysctl_oid_list *parent, *stats_parent, *queue_parent;
2719 	struct sysctl_oid_list *ports_parent, *port_parent;
2720 	char port[16];
2721 	int i;
2722 
2723 	ctx = device_get_sysctl_ctx(sc->dev);
2724 	parent = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
2725 
2726 	SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "debug",
2727 	    CTLFLAG_RW, &sc->debug, 0, "Enable switch debug messages");
2728 
2729 	SYSCTL_ADD_INT(ctx, parent, OID_AUTO, "rx_batch",
2730 	    CTLFLAG_RW, &sc->rx_batch, 0, "Set the rx batch size");
2731 
2732 	SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "attachedSecs",
2733 	    CTLTYPE_UINT | CTLFLAG_RD, sc, 0, cpsw_stat_attached, "IU",
2734 	    "Time since driver attach");
2735 
2736 	SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, "intr_coalesce_us",
2737 	    CTLTYPE_UINT | CTLFLAG_RW, sc, 0, cpsw_intr_coalesce, "IU",
2738 	    "minimum time between interrupts");
2739 
2740 	node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "ports",
2741 	    CTLFLAG_RD, NULL, "CPSW Ports Statistics");
2742 	ports_parent = SYSCTL_CHILDREN(node);
2743 	for (i = 0; i < CPSW_PORTS; i++) {
2744 		if (!sc->dualemac && i != sc->active_slave)
2745 			continue;
2746 		port[0] = '0' + i;
2747 		port[1] = '\0';
2748 		node = SYSCTL_ADD_NODE(ctx, ports_parent, OID_AUTO,
2749 		    port, CTLFLAG_RD, NULL, "CPSW Port Statistics");
2750 		port_parent = SYSCTL_CHILDREN(node);
2751 		SYSCTL_ADD_PROC(ctx, port_parent, OID_AUTO, "uptime",
2752 		    CTLTYPE_UINT | CTLFLAG_RD, sc, i,
2753 		    cpsw_stat_uptime, "IU", "Seconds since driver init");
2754 	}
2755 
2756 	stats_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats",
2757 				     CTLFLAG_RD, NULL, "CPSW Statistics");
2758 	stats_parent = SYSCTL_CHILDREN(stats_node);
2759 	for (i = 0; i < CPSW_SYSCTL_COUNT; ++i) {
2760 		SYSCTL_ADD_PROC(ctx, stats_parent, i,
2761 				cpsw_stat_sysctls[i].oid,
2762 				CTLTYPE_U64 | CTLFLAG_RD, sc, 0,
2763 				cpsw_stats_sysctl, "IU",
2764 				cpsw_stat_sysctls[i].oid);
2765 	}
2766 
2767 	queue_node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "queue",
2768 	    CTLFLAG_RD, NULL, "CPSW Queue Statistics");
2769 	queue_parent = SYSCTL_CHILDREN(queue_node);
2770 
2771 	node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "tx",
2772 	    CTLFLAG_RD, NULL, "TX Queue Statistics");
2773 	cpsw_add_queue_sysctls(ctx, node, &sc->tx);
2774 
2775 	node = SYSCTL_ADD_NODE(ctx, queue_parent, OID_AUTO, "rx",
2776 	    CTLFLAG_RD, NULL, "RX Queue Statistics");
2777 	cpsw_add_queue_sysctls(ctx, node, &sc->rx);
2778 
2779 	node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "watchdog",
2780 	    CTLFLAG_RD, NULL, "Watchdog Statistics");
2781 	cpsw_add_watchdog_sysctls(ctx, node, sc);
2782 }
2783 
2784 #ifdef CPSW_ETHERSWITCH
2785 static etherswitch_info_t etherswitch_info = {
2786 	.es_nports =		CPSW_PORTS + 1,
2787 	.es_nvlangroups =	CPSW_VLANS,
2788 	.es_name =		"TI Common Platform Ethernet Switch (CPSW)",
2789 	.es_vlan_caps =		ETHERSWITCH_VLAN_DOT1Q,
2790 };
2791 
2792 static etherswitch_info_t *
2793 cpsw_getinfo(device_t dev)
2794 {
2795 	return (&etherswitch_info);
2796 }
2797 
2798 static int
2799 cpsw_getport(device_t dev, etherswitch_port_t *p)
2800 {
2801 	int err;
2802 	struct cpsw_softc *sc;
2803 	struct cpswp_softc *psc;
2804 	struct ifmediareq *ifmr;
2805 	uint32_t reg;
2806 
2807 	if (p->es_port < 0 || p->es_port > CPSW_PORTS)
2808 		return (ENXIO);
2809 
2810 	err = 0;
2811 	sc = device_get_softc(dev);
2812 	if (p->es_port == CPSW_CPU_PORT) {
2813 		p->es_flags |= ETHERSWITCH_PORT_CPU;
2814  		ifmr = &p->es_ifmr;
2815 		ifmr->ifm_current = ifmr->ifm_active =
2816 		    IFM_ETHER | IFM_1000_T | IFM_FDX;
2817 		ifmr->ifm_mask = 0;
2818 		ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID;
2819 		ifmr->ifm_count = 0;
2820 	} else {
2821 		psc = device_get_softc(sc->port[p->es_port - 1].dev);
2822 		err = ifmedia_ioctl(psc->ifp, &p->es_ifr,
2823 		    &psc->mii->mii_media, SIOCGIFMEDIA);
2824 	}
2825 	reg = cpsw_read_4(sc, CPSW_PORT_P_VLAN(p->es_port));
2826 	p->es_pvid = reg & ETHERSWITCH_VID_MASK;
2827 
2828 	reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port));
2829 	if (reg & ALE_PORTCTL_DROP_UNTAGGED)
2830 		p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED;
2831 	if (reg & ALE_PORTCTL_INGRESS)
2832 		p->es_flags |= ETHERSWITCH_PORT_INGRESS;
2833 
2834 	return (err);
2835 }
2836 
2837 static int
2838 cpsw_setport(device_t dev, etherswitch_port_t *p)
2839 {
2840 	struct cpsw_softc *sc;
2841 	struct cpswp_softc *psc;
2842 	struct ifmedia *ifm;
2843 	uint32_t reg;
2844 
2845 	if (p->es_port < 0 || p->es_port > CPSW_PORTS)
2846 		return (ENXIO);
2847 
2848 	sc = device_get_softc(dev);
2849 	if (p->es_pvid != 0) {
2850 		cpsw_write_4(sc, CPSW_PORT_P_VLAN(p->es_port),
2851 		    p->es_pvid & ETHERSWITCH_VID_MASK);
2852 	}
2853 
2854 	reg = cpsw_read_4(sc, CPSW_ALE_PORTCTL(p->es_port));
2855 	if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED)
2856 		reg |= ALE_PORTCTL_DROP_UNTAGGED;
2857 	else
2858 		reg &= ~ALE_PORTCTL_DROP_UNTAGGED;
2859 	if (p->es_flags & ETHERSWITCH_PORT_INGRESS)
2860 		reg |= ALE_PORTCTL_INGRESS;
2861 	else
2862 		reg &= ~ALE_PORTCTL_INGRESS;
2863 	cpsw_write_4(sc, CPSW_ALE_PORTCTL(p->es_port), reg);
2864 
2865 	/* CPU port does not allow media settings. */
2866 	if (p->es_port == CPSW_CPU_PORT)
2867 		return (0);
2868 
2869 	psc = device_get_softc(sc->port[p->es_port - 1].dev);
2870 	ifm = &psc->mii->mii_media;
2871 
2872 	return (ifmedia_ioctl(psc->ifp, &p->es_ifr, ifm, SIOCSIFMEDIA));
2873 }
2874 
2875 static int
2876 cpsw_getconf(device_t dev, etherswitch_conf_t *conf)
2877 {
2878 
2879 	/* Return the VLAN mode. */
2880 	conf->cmd = ETHERSWITCH_CONF_VLAN_MODE;
2881 	conf->vlan_mode = ETHERSWITCH_VLAN_DOT1Q;
2882 
2883 	return (0);
2884 }
2885 
2886 static int
2887 cpsw_getvgroup(device_t dev, etherswitch_vlangroup_t *vg)
2888 {
2889 	int i, vid;
2890 	uint32_t ale_entry[3];
2891 	struct cpsw_softc *sc;
2892 
2893 	sc = device_get_softc(dev);
2894 
2895 	if (vg->es_vlangroup >= CPSW_VLANS)
2896 		return (EINVAL);
2897 
2898 	vg->es_vid = 0;
2899 	vid = cpsw_vgroups[vg->es_vlangroup].vid;
2900 	if (vid == -1)
2901 		return (0);
2902 
2903 	for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) {
2904 		cpsw_ale_read_entry(sc, i, ale_entry);
2905 		if (ALE_TYPE(ale_entry) != ALE_TYPE_VLAN)
2906 			continue;
2907 		if (vid != ALE_VLAN(ale_entry))
2908 			continue;
2909 
2910 		vg->es_fid = 0;
2911 		vg->es_vid = ALE_VLAN(ale_entry) | ETHERSWITCH_VID_VALID;
2912 		vg->es_member_ports = ALE_VLAN_MEMBERS(ale_entry);
2913 		vg->es_untagged_ports = ALE_VLAN_UNTAG(ale_entry);
2914 	}
2915 
2916 	return (0);
2917 }
2918 
2919 static void
2920 cpsw_remove_vlan(struct cpsw_softc *sc, int vlan)
2921 {
2922 	int i;
2923 	uint32_t ale_entry[3];
2924 
2925 	for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) {
2926 		cpsw_ale_read_entry(sc, i, ale_entry);
2927 		if (ALE_TYPE(ale_entry) != ALE_TYPE_VLAN)
2928 			continue;
2929 		if (vlan != ALE_VLAN(ale_entry))
2930 			continue;
2931 		ale_entry[0] = ale_entry[1] = ale_entry[2] = 0;
2932 		cpsw_ale_write_entry(sc, i, ale_entry);
2933 		break;
2934 	}
2935 }
2936 
2937 static int
2938 cpsw_setvgroup(device_t dev, etherswitch_vlangroup_t *vg)
2939 {
2940 	int i;
2941 	struct cpsw_softc *sc;
2942 
2943 	sc = device_get_softc(dev);
2944 
2945 	for (i = 0; i < CPSW_VLANS; i++) {
2946 		/* Is this Vlan ID in use by another vlangroup ? */
2947 		if (vg->es_vlangroup != i && cpsw_vgroups[i].vid == vg->es_vid)
2948 			return (EINVAL);
2949 	}
2950 
2951 	if (vg->es_vid == 0) {
2952 		if (cpsw_vgroups[vg->es_vlangroup].vid == -1)
2953 			return (0);
2954 		cpsw_remove_vlan(sc, cpsw_vgroups[vg->es_vlangroup].vid);
2955 		cpsw_vgroups[vg->es_vlangroup].vid = -1;
2956 		vg->es_untagged_ports = 0;
2957 		vg->es_member_ports = 0;
2958 		vg->es_vid = 0;
2959 		return (0);
2960 	}
2961 
2962 	vg->es_vid &= ETHERSWITCH_VID_MASK;
2963 	vg->es_member_ports &= CPSW_PORTS_MASK;
2964 	vg->es_untagged_ports &= CPSW_PORTS_MASK;
2965 
2966 	if (cpsw_vgroups[vg->es_vlangroup].vid != -1 &&
2967 	    cpsw_vgroups[vg->es_vlangroup].vid != vg->es_vid)
2968 		return (EINVAL);
2969 
2970 	cpsw_vgroups[vg->es_vlangroup].vid = vg->es_vid;
2971 	cpsw_ale_update_vlan_table(sc, vg->es_vid, vg->es_member_ports,
2972 	    vg->es_untagged_ports, vg->es_member_ports, 0);
2973 
2974 	return (0);
2975 }
2976 
2977 static int
2978 cpsw_readreg(device_t dev, int addr)
2979 {
2980 
2981 	/* Not supported. */
2982 	return (0);
2983 }
2984 
2985 static int
2986 cpsw_writereg(device_t dev, int addr, int value)
2987 {
2988 
2989 	/* Not supported. */
2990 	return (0);
2991 }
2992 
2993 static int
2994 cpsw_readphy(device_t dev, int phy, int reg)
2995 {
2996 
2997 	/* Not supported. */
2998 	return (0);
2999 }
3000 
3001 static int
3002 cpsw_writephy(device_t dev, int phy, int reg, int data)
3003 {
3004 
3005 	/* Not supported. */
3006 	return (0);
3007 }
3008 #endif
3009