xref: /freebsd/sys/arm/ti/clk/ti_gate_clock.c (revision ed549cb0c53f8438c52593ce811f6fcc812248e9)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se>
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD$
28  */
29 
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 #include <sys/param.h>
34 #include <sys/conf.h>
35 #include <sys/bus.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/systm.h>
39 #include <sys/libkern.h>
40 
41 #include <machine/bus.h>
42 #include <dev/fdt/simplebus.h>
43 
44 #include <dev/extres/clk/clk_gate.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
47 
48 #include "clock_common.h"
49 
50 #define DEBUG_GATE	0
51 
52 #if DEBUG_GATE
53 #define DPRINTF(dev, msg...) device_printf(dev, msg)
54 #else
55 #define DPRINTF(dev, msg...)
56 #endif
57 
58 /*
59  * Devicetree description
60  * Documentation/devicetree/bindings/clock/ti/gate.txt
61  */
62 
63 struct ti_gate_softc {
64 	device_t		sc_dev;
65 	bool			attach_done;
66 	uint8_t			sc_type;
67 
68 	struct clk_gate_def	gate_def;
69 	struct clock_cell_info  clock_cell;
70 	struct clkdom		*clkdom;
71 };
72 
73 static int ti_gate_probe(device_t dev);
74 static int ti_gate_attach(device_t dev);
75 static int ti_gate_detach(device_t dev);
76 
77 #define TI_GATE_CLOCK			7
78 #define TI_WAIT_GATE_CLOCK		6
79 #define TI_DSS_GATE_CLOCK		5
80 #define TI_AM35XX_GATE_CLOCK		4
81 #define TI_CLKDM_GATE_CLOCK		3
82 #define TI_HSDIV_GATE_CLOCK		2
83 #define TI_COMPOSITE_NO_WAIT_GATE_CLOCK	1
84 #define TI_GATE_END			0
85 
86 static struct ofw_compat_data compat_data[] = {
87 	{ "ti,gate-clock",			TI_GATE_CLOCK },
88 	{ "ti,wait-gate-clock",			TI_WAIT_GATE_CLOCK },
89 	{ "ti,dss-gate-clock",			TI_DSS_GATE_CLOCK },
90 	{ "ti,am35xx-gate-clock",		TI_AM35XX_GATE_CLOCK },
91 	{ "ti,clkdm-gate-clock",		TI_CLKDM_GATE_CLOCK },
92 	{ "ti,hsdiv-gate-cloc",			TI_HSDIV_GATE_CLOCK },
93 	{ "ti,composite-no-wait-gate-clock",	TI_COMPOSITE_NO_WAIT_GATE_CLOCK },
94 	{ NULL,					TI_GATE_END }
95 };
96 
97 static int
98 ti_gate_probe(device_t dev)
99 {
100 	if (!ofw_bus_status_okay(dev))
101 		return (ENXIO);
102 
103 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
104 		return (ENXIO);
105 
106 	device_set_desc(dev, "TI Gate Clock");
107 
108 	return (BUS_PROBE_DEFAULT);
109 }
110 
111 static int
112 register_clk(struct ti_gate_softc *sc) {
113 	int err;
114 	sc->clkdom = clkdom_create(sc->sc_dev);
115 	if (sc->clkdom == NULL) {
116 		DPRINTF(sc->sc_dev, "Failed to create clkdom\n");
117 		return ENXIO;
118 	}
119 
120 	err = clknode_gate_register(sc->clkdom, &sc->gate_def);
121 	if (err) {
122 		DPRINTF(sc->sc_dev, "clknode_gate_register failed %x\n", err);
123 		return ENXIO;
124 	}
125 
126 	err = clkdom_finit(sc->clkdom);
127 	if (err) {
128 		DPRINTF(sc->sc_dev, "Clk domain finit fails %x.\n", err);
129 		return ENXIO;
130 	}
131 
132 	return (0);
133 }
134 
135 static int
136 ti_gate_attach(device_t dev)
137 {
138 	struct ti_gate_softc *sc;
139 	phandle_t node;
140 	int err;
141 	cell_t value;
142 
143 	sc = device_get_softc(dev);
144 	sc->sc_dev = dev;
145 	node = ofw_bus_get_node(dev);
146 
147 	/* Get the compatible type */
148 	sc->sc_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
149 
150 	/* Get the content of reg properties */
151 	if (sc->sc_type != TI_CLKDM_GATE_CLOCK) {
152 		OF_getencprop(node, "reg", &value, sizeof(value));
153 		sc->gate_def.offset = value;
154 	}
155 #if DEBUG_GATE
156 	else {
157 		DPRINTF(sc->sc_dev, "no reg (TI_CLKDM_GATE_CLOCK)\n");
158 	}
159 #endif
160 
161 	if (OF_hasprop(node, "ti,bit-shift")) {
162 		OF_getencprop(node, "ti,bit-shift", &value, sizeof(value));
163 		sc->gate_def.shift = value;
164 		DPRINTF(sc->sc_dev, "ti,bit-shift => shift %x\n", sc->gate_def.shift);
165 	}
166 	if (OF_hasprop(node, "ti,set-bit-to-disable")) {
167 		sc->gate_def.on_value = 0;
168 		sc->gate_def.off_value = 1;
169 		DPRINTF(sc->sc_dev,
170 			"on_value = 0, off_value = 1 (ti,set-bit-to-disable)\n");
171 	} else {
172 		sc->gate_def.on_value = 1;
173 		sc->gate_def.off_value = 0;
174 		DPRINTF(sc->sc_dev, "on_value = 1, off_value = 0\n");
175 	}
176 
177 	sc->gate_def.gate_flags = 0x0;
178 
179 	read_clock_cells(sc->sc_dev, &sc->clock_cell);
180 
181 	create_clkdef(sc->sc_dev, &sc->clock_cell, &sc->gate_def.clkdef);
182 
183 	/* Calculate mask */
184 	sc->gate_def.mask = (1 << fls(sc->clock_cell.num_real_clocks)) - 1;
185 	DPRINTF(sc->sc_dev, "num_real_clocks %x gate_def.mask %x\n",
186 		sc->clock_cell.num_real_clocks, sc->gate_def.mask);
187 
188 	err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->gate_def.clkdef);
189 
190 	if (err) {
191 		/* free_clkdef will be called in ti_gate_new_pass */
192 		DPRINTF(sc->sc_dev, "find_parent_clock_names failed\n");
193 		return (bus_generic_attach(sc->sc_dev));
194 	}
195 
196 	err = register_clk(sc);
197 
198 	if (err) {
199 		/* free_clkdef will be called in ti_gate_new_pass */
200 		DPRINTF(sc->sc_dev, "register_clk failed\n");
201 		return (bus_generic_attach(sc->sc_dev));
202 	}
203 
204 	sc->attach_done = true;
205 
206 	free_clkdef(&sc->gate_def.clkdef);
207 
208 	return (bus_generic_attach(sc->sc_dev));
209 }
210 
211 static int
212 ti_gate_detach(device_t dev)
213 {
214 	return (EBUSY);
215 }
216 
217 static void
218 ti_gate_new_pass(device_t dev) {
219 	struct ti_gate_softc *sc;
220 	int err;
221 
222 	sc = device_get_softc(dev);
223 
224 	if (sc->attach_done) {
225 		return;
226 	}
227 
228 	err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->gate_def.clkdef);
229 	if (err) {
230 		/* free_clkdef will be called in later call to ti_gate_new_pass */
231 		DPRINTF(sc->sc_dev, "new_pass find_parent_clock_names failed\n");
232 		return;
233 	}
234 
235 	err = register_clk(sc);
236 	if (err) {
237 		/* free_clkdef will be called in later call to ti_gate_new_pass */
238 		DPRINTF(sc->sc_dev, "new_pass register_clk failed\n");
239 		return;
240 	}
241 
242 	sc->attach_done = true;
243 
244 	free_clkdef(&sc->gate_def.clkdef);
245 }
246 
247 static device_method_t ti_gate_methods[] = {
248 	/* Device interface */
249 	DEVMETHOD(device_probe,		ti_gate_probe),
250 	DEVMETHOD(device_attach,	ti_gate_attach),
251 	DEVMETHOD(device_detach,	ti_gate_detach),
252 
253 	/* Bus interface */
254 	DEVMETHOD(bus_new_pass,		ti_gate_new_pass),
255 
256 	DEVMETHOD_END
257 };
258 
259 DEFINE_CLASS_0(ti_gate, ti_gate_driver, ti_gate_methods,
260 	sizeof(struct ti_gate_softc));
261 
262 EARLY_DRIVER_MODULE(ti_gate, simplebus, ti_gate_driver, 0, 0,
263     BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
264 MODULE_VERSION(ti_gate, 1);
265