1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/conf.h> 33 #include <sys/bus.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/systm.h> 37 #include <sys/libkern.h> 38 39 #include <machine/bus.h> 40 #include <dev/fdt/simplebus.h> 41 42 #include <dev/extres/clk/clk_gate.h> 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 46 #include "clock_common.h" 47 48 #define DEBUG_GATE 0 49 50 #if DEBUG_GATE 51 #define DPRINTF(dev, msg...) device_printf(dev, msg) 52 #else 53 #define DPRINTF(dev, msg...) 54 #endif 55 56 /* 57 * Devicetree description 58 * Documentation/devicetree/bindings/clock/ti/gate.txt 59 */ 60 61 struct ti_gate_softc { 62 device_t sc_dev; 63 bool attach_done; 64 uint8_t sc_type; 65 66 struct clk_gate_def gate_def; 67 struct clock_cell_info clock_cell; 68 struct clkdom *clkdom; 69 }; 70 71 static int ti_gate_probe(device_t dev); 72 static int ti_gate_attach(device_t dev); 73 static int ti_gate_detach(device_t dev); 74 75 #define TI_GATE_CLOCK 7 76 #define TI_WAIT_GATE_CLOCK 6 77 #define TI_DSS_GATE_CLOCK 5 78 #define TI_AM35XX_GATE_CLOCK 4 79 #define TI_CLKDM_GATE_CLOCK 3 80 #define TI_HSDIV_GATE_CLOCK 2 81 #define TI_COMPOSITE_NO_WAIT_GATE_CLOCK 1 82 #define TI_GATE_END 0 83 84 static struct ofw_compat_data compat_data[] = { 85 { "ti,gate-clock", TI_GATE_CLOCK }, 86 { "ti,wait-gate-clock", TI_WAIT_GATE_CLOCK }, 87 { "ti,dss-gate-clock", TI_DSS_GATE_CLOCK }, 88 { "ti,am35xx-gate-clock", TI_AM35XX_GATE_CLOCK }, 89 { "ti,clkdm-gate-clock", TI_CLKDM_GATE_CLOCK }, 90 { "ti,hsdiv-gate-cloc", TI_HSDIV_GATE_CLOCK }, 91 { "ti,composite-no-wait-gate-clock", TI_COMPOSITE_NO_WAIT_GATE_CLOCK }, 92 { NULL, TI_GATE_END } 93 }; 94 95 static int 96 ti_gate_probe(device_t dev) 97 { 98 if (!ofw_bus_status_okay(dev)) 99 return (ENXIO); 100 101 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 102 return (ENXIO); 103 104 device_set_desc(dev, "TI Gate Clock"); 105 106 return (BUS_PROBE_DEFAULT); 107 } 108 109 static int 110 register_clk(struct ti_gate_softc *sc) { 111 int err; 112 sc->clkdom = clkdom_create(sc->sc_dev); 113 if (sc->clkdom == NULL) { 114 DPRINTF(sc->sc_dev, "Failed to create clkdom\n"); 115 return ENXIO; 116 } 117 118 err = clknode_gate_register(sc->clkdom, &sc->gate_def); 119 if (err) { 120 DPRINTF(sc->sc_dev, "clknode_gate_register failed %x\n", err); 121 return ENXIO; 122 } 123 124 err = clkdom_finit(sc->clkdom); 125 if (err) { 126 DPRINTF(sc->sc_dev, "Clk domain finit fails %x.\n", err); 127 return ENXIO; 128 } 129 130 return (0); 131 } 132 133 static int 134 ti_gate_attach(device_t dev) 135 { 136 struct ti_gate_softc *sc; 137 phandle_t node; 138 int err; 139 cell_t value; 140 141 sc = device_get_softc(dev); 142 sc->sc_dev = dev; 143 node = ofw_bus_get_node(dev); 144 145 /* Get the compatible type */ 146 sc->sc_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 147 148 /* Get the content of reg properties */ 149 if (sc->sc_type != TI_CLKDM_GATE_CLOCK) { 150 OF_getencprop(node, "reg", &value, sizeof(value)); 151 sc->gate_def.offset = value; 152 } 153 #if DEBUG_GATE 154 else { 155 DPRINTF(sc->sc_dev, "no reg (TI_CLKDM_GATE_CLOCK)\n"); 156 } 157 #endif 158 159 if (OF_hasprop(node, "ti,bit-shift")) { 160 OF_getencprop(node, "ti,bit-shift", &value, sizeof(value)); 161 sc->gate_def.shift = value; 162 DPRINTF(sc->sc_dev, "ti,bit-shift => shift %x\n", sc->gate_def.shift); 163 } 164 if (OF_hasprop(node, "ti,set-bit-to-disable")) { 165 sc->gate_def.on_value = 0; 166 sc->gate_def.off_value = 1; 167 DPRINTF(sc->sc_dev, 168 "on_value = 0, off_value = 1 (ti,set-bit-to-disable)\n"); 169 } else { 170 sc->gate_def.on_value = 1; 171 sc->gate_def.off_value = 0; 172 DPRINTF(sc->sc_dev, "on_value = 1, off_value = 0\n"); 173 } 174 175 sc->gate_def.gate_flags = 0x0; 176 177 read_clock_cells(sc->sc_dev, &sc->clock_cell); 178 179 create_clkdef(sc->sc_dev, &sc->clock_cell, &sc->gate_def.clkdef); 180 181 /* Calculate mask */ 182 sc->gate_def.mask = (1 << fls(sc->clock_cell.num_real_clocks)) - 1; 183 DPRINTF(sc->sc_dev, "num_real_clocks %x gate_def.mask %x\n", 184 sc->clock_cell.num_real_clocks, sc->gate_def.mask); 185 186 err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->gate_def.clkdef); 187 188 if (err) { 189 /* free_clkdef will be called in ti_gate_new_pass */ 190 DPRINTF(sc->sc_dev, "find_parent_clock_names failed\n"); 191 return (bus_generic_attach(sc->sc_dev)); 192 } 193 194 err = register_clk(sc); 195 196 if (err) { 197 /* free_clkdef will be called in ti_gate_new_pass */ 198 DPRINTF(sc->sc_dev, "register_clk failed\n"); 199 return (bus_generic_attach(sc->sc_dev)); 200 } 201 202 sc->attach_done = true; 203 204 free_clkdef(&sc->gate_def.clkdef); 205 206 return (bus_generic_attach(sc->sc_dev)); 207 } 208 209 static int 210 ti_gate_detach(device_t dev) 211 { 212 return (EBUSY); 213 } 214 215 static void 216 ti_gate_new_pass(device_t dev) { 217 struct ti_gate_softc *sc; 218 int err; 219 220 sc = device_get_softc(dev); 221 222 if (sc->attach_done) { 223 return; 224 } 225 226 err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->gate_def.clkdef); 227 if (err) { 228 /* free_clkdef will be called in later call to ti_gate_new_pass */ 229 DPRINTF(sc->sc_dev, "new_pass find_parent_clock_names failed\n"); 230 return; 231 } 232 233 err = register_clk(sc); 234 if (err) { 235 /* free_clkdef will be called in later call to ti_gate_new_pass */ 236 DPRINTF(sc->sc_dev, "new_pass register_clk failed\n"); 237 return; 238 } 239 240 sc->attach_done = true; 241 242 free_clkdef(&sc->gate_def.clkdef); 243 } 244 245 static device_method_t ti_gate_methods[] = { 246 /* Device interface */ 247 DEVMETHOD(device_probe, ti_gate_probe), 248 DEVMETHOD(device_attach, ti_gate_attach), 249 DEVMETHOD(device_detach, ti_gate_detach), 250 251 /* Bus interface */ 252 DEVMETHOD(bus_new_pass, ti_gate_new_pass), 253 254 DEVMETHOD_END 255 }; 256 257 DEFINE_CLASS_0(ti_gate, ti_gate_driver, ti_gate_methods, 258 sizeof(struct ti_gate_softc)); 259 260 EARLY_DRIVER_MODULE(ti_gate, simplebus, ti_gate_driver, 0, 0, 261 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 262 MODULE_VERSION(ti_gate, 1); 263