1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/conf.h> 31 #include <sys/bus.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/systm.h> 35 #include <sys/libkern.h> 36 37 #include <machine/bus.h> 38 #include <dev/fdt/simplebus.h> 39 40 #include <dev/extres/clk/clk_div.h> 41 #include <dev/ofw/ofw_bus.h> 42 #include <dev/ofw/ofw_bus_subr.h> 43 44 #include <arm/ti/clk/ti_clk_dpll.h> 45 #include "clock_common.h" 46 47 #if 0 48 #define DPRINTF(dev, msg...) device_printf(dev, msg) 49 #else 50 #define DPRINTF(dev, msg...) 51 #endif 52 53 /* 54 * Devicetree description 55 * Documentation/devicetree/bindings/clock/ti/dpll.txt 56 */ 57 58 struct ti_dpll_softc { 59 device_t dev; 60 uint8_t dpll_type; 61 62 bool attach_done; 63 struct ti_clk_dpll_def dpll_def; 64 65 struct clock_cell_info clock_cell; 66 struct clkdom *clkdom; 67 }; 68 69 static int ti_dpll_probe(device_t dev); 70 static int ti_dpll_attach(device_t dev); 71 static int ti_dpll_detach(device_t dev); 72 73 #define TI_OMAP3_DPLL_CLOCK 17 74 #define TI_OMAP3_DPLL_CORE_CLOCK 16 75 #define TI_OMAP3_DPLL_PER_CLOCK 15 76 #define TI_OMAP3_DPLL_PER_J_TYPE_CLOCK 14 77 #define TI_OMAP4_DPLL_CLOCK 13 78 #define TI_OMAP4_DPLL_X2_CLOCK 12 79 #define TI_OMAP4_DPLL_CORE_CLOCK 11 80 #define TI_OMAP4_DPLL_M4XEN_CLOCK 10 81 #define TI_OMAP4_DPLL_J_TYPE_CLOCK 9 82 #define TI_OMAP5_MPU_DPLL_CLOCK 8 83 #define TI_AM3_DPLL_NO_GATE_CLOCK 7 84 #define TI_AM3_DPLL_J_TYPE_CLOCK 6 85 #define TI_AM3_DPLL_NO_GATE_J_TYPE_CLOCK 5 86 #define TI_AM3_DPLL_CLOCK 4 87 #define TI_AM3_DPLL_CORE_CLOCK 3 88 #define TI_AM3_DPLL_X2_CLOCK 2 89 #define TI_OMAP2_DPLL_CORE_CLOCK 1 90 #define TI_DPLL_END 0 91 92 static struct ofw_compat_data compat_data[] = { 93 { "ti,omap3-dpll-clock", TI_OMAP3_DPLL_CLOCK }, 94 { "ti,omap3-dpll-core-clock", TI_OMAP3_DPLL_CORE_CLOCK }, 95 { "ti,omap3-dpll-per-clock", TI_OMAP3_DPLL_PER_CLOCK }, 96 { "ti,omap3-dpll-per-j-type-clock",TI_OMAP3_DPLL_PER_J_TYPE_CLOCK }, 97 { "ti,omap4-dpll-clock", TI_OMAP4_DPLL_CLOCK }, 98 { "ti,omap4-dpll-x2-clock", TI_OMAP4_DPLL_X2_CLOCK }, 99 { "ti,omap4-dpll-core-clock", TI_OMAP4_DPLL_CORE_CLOCK }, 100 { "ti,omap4-dpll-m4xen-clock", TI_OMAP4_DPLL_M4XEN_CLOCK }, 101 { "ti,omap4-dpll-j-type-clock", TI_OMAP4_DPLL_J_TYPE_CLOCK }, 102 { "ti,omap5-mpu-dpll-clock", TI_OMAP5_MPU_DPLL_CLOCK }, 103 { "ti,am3-dpll-no-gate-clock", TI_AM3_DPLL_NO_GATE_CLOCK }, 104 { "ti,am3-dpll-j-type-clock", TI_AM3_DPLL_J_TYPE_CLOCK }, 105 { "ti,am3-dpll-no-gate-j-type-clock",TI_AM3_DPLL_NO_GATE_J_TYPE_CLOCK }, 106 { "ti,am3-dpll-clock", TI_AM3_DPLL_CLOCK }, 107 { "ti,am3-dpll-core-clock", TI_AM3_DPLL_CORE_CLOCK }, 108 { "ti,am3-dpll-x2-clock", TI_AM3_DPLL_X2_CLOCK }, 109 { "ti,omap2-dpll-core-clock", TI_OMAP2_DPLL_CORE_CLOCK }, 110 { NULL, TI_DPLL_END } 111 }; 112 113 static int 114 register_clk(struct ti_dpll_softc *sc) { 115 int err; 116 117 sc->clkdom = clkdom_create(sc->dev); 118 if (sc->clkdom == NULL) { 119 DPRINTF(sc->dev, "Failed to create clkdom\n"); 120 return (ENXIO); 121 } 122 123 err = ti_clknode_dpll_register(sc->clkdom, &sc->dpll_def); 124 if (err) { 125 DPRINTF(sc->dev, 126 "ti_clknode_dpll_register failed %x\n", err); 127 return (ENXIO); 128 } 129 130 err = clkdom_finit(sc->clkdom); 131 if (err) { 132 DPRINTF(sc->dev, "Clk domain finit fails %x.\n", err); 133 return (ENXIO); 134 } 135 136 return (0); 137 } 138 139 static int 140 ti_dpll_probe(device_t dev) 141 { 142 if (!ofw_bus_status_okay(dev)) 143 return (ENXIO); 144 145 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 146 return (ENXIO); 147 148 device_set_desc(dev, "TI DPLL Clock"); 149 150 return (BUS_PROBE_DEFAULT); 151 } 152 153 static int 154 parse_dpll_reg(struct ti_dpll_softc *sc) { 155 ssize_t numbytes_regs; 156 uint32_t num_regs; 157 phandle_t node; 158 cell_t reg_cells[4]; 159 160 if (sc->dpll_type == TI_AM3_DPLL_X2_CLOCK || 161 sc->dpll_type == TI_OMAP4_DPLL_X2_CLOCK) { 162 sc->dpll_def.ti_clksel_mult.value = 2; 163 sc->dpll_def.ti_clksel_mult.flags = TI_CLK_FACTOR_FIXED; 164 165 sc->dpll_def.ti_clksel_div.value = 1; 166 sc->dpll_def.ti_clksel_div.flags = TI_CLK_FACTOR_FIXED; 167 return (0); 168 } 169 170 node = ofw_bus_get_node(sc->dev); 171 172 numbytes_regs = OF_getproplen(node, "reg"); 173 num_regs = numbytes_regs / sizeof(cell_t); 174 175 /* Sanity check */ 176 if (num_regs > 4) 177 return (ENXIO); 178 179 OF_getencprop(node, "reg", reg_cells, numbytes_regs); 180 181 switch (sc->dpll_type) { 182 case TI_AM3_DPLL_NO_GATE_CLOCK: 183 case TI_AM3_DPLL_J_TYPE_CLOCK: 184 case TI_AM3_DPLL_NO_GATE_J_TYPE_CLOCK: 185 case TI_AM3_DPLL_CLOCK: 186 case TI_AM3_DPLL_CORE_CLOCK: 187 case TI_AM3_DPLL_X2_CLOCK: 188 if (num_regs != 3) 189 return (ENXIO); 190 sc->dpll_def.ti_clkmode_offset = reg_cells[0]; 191 sc->dpll_def.ti_idlest_offset = reg_cells[1]; 192 sc->dpll_def.ti_clksel_offset = reg_cells[2]; 193 break; 194 195 case TI_OMAP2_DPLL_CORE_CLOCK: 196 if (num_regs != 2) 197 return (ENXIO); 198 sc->dpll_def.ti_clkmode_offset = reg_cells[0]; 199 sc->dpll_def.ti_clksel_offset = reg_cells[1]; 200 break; 201 202 default: 203 sc->dpll_def.ti_clkmode_offset = reg_cells[0]; 204 sc->dpll_def.ti_idlest_offset = reg_cells[1]; 205 sc->dpll_def.ti_clksel_offset = reg_cells[2]; 206 sc->dpll_def.ti_autoidle_offset = reg_cells[3]; 207 break; 208 } 209 210 /* AM335x */ 211 if (sc->dpll_def.ti_clksel_offset == CM_CLKSEL_DPLL_PERIPH) { 212 sc->dpll_def.ti_clksel_mult.shift = 8; 213 sc->dpll_def.ti_clksel_mult.mask = 0x000FFF00; 214 sc->dpll_def.ti_clksel_mult.width = 12; 215 sc->dpll_def.ti_clksel_mult.value = 0; 216 sc->dpll_def.ti_clksel_mult.min_value = 2; 217 sc->dpll_def.ti_clksel_mult.max_value = 4095; 218 sc->dpll_def.ti_clksel_mult.flags = TI_CLK_FACTOR_ZERO_BASED | 219 TI_CLK_FACTOR_MIN_VALUE | 220 TI_CLK_FACTOR_MAX_VALUE; 221 222 sc->dpll_def.ti_clksel_div.shift = 0; 223 sc->dpll_def.ti_clksel_div.mask = 0x000000FF; 224 sc->dpll_def.ti_clksel_div.width = 8; 225 sc->dpll_def.ti_clksel_div.value = 0; 226 sc->dpll_def.ti_clksel_div.min_value = 0; 227 sc->dpll_def.ti_clksel_div.max_value = 255; 228 sc->dpll_def.ti_clksel_div.flags = TI_CLK_FACTOR_MIN_VALUE | 229 TI_CLK_FACTOR_MAX_VALUE; 230 } else { 231 sc->dpll_def.ti_clksel_mult.shift = 8; 232 sc->dpll_def.ti_clksel_mult.mask = 0x0007FF00; 233 sc->dpll_def.ti_clksel_mult.width = 11; 234 sc->dpll_def.ti_clksel_mult.value = 0; 235 sc->dpll_def.ti_clksel_mult.min_value = 2; 236 sc->dpll_def.ti_clksel_mult.max_value = 2047; 237 sc->dpll_def.ti_clksel_mult.flags = TI_CLK_FACTOR_ZERO_BASED | 238 TI_CLK_FACTOR_MIN_VALUE | 239 TI_CLK_FACTOR_MAX_VALUE; 240 241 sc->dpll_def.ti_clksel_div.shift = 0; 242 sc->dpll_def.ti_clksel_div.mask = 0x0000007F; 243 sc->dpll_def.ti_clksel_div.width = 7; 244 sc->dpll_def.ti_clksel_div.value = 0; 245 sc->dpll_def.ti_clksel_div.min_value = 0; 246 sc->dpll_def.ti_clksel_div.max_value = 127; 247 sc->dpll_def.ti_clksel_div.flags = TI_CLK_FACTOR_MIN_VALUE | 248 TI_CLK_FACTOR_MAX_VALUE; 249 } 250 DPRINTF(sc->dev, "clkmode %x idlest %x clksel %x autoidle %x\n", 251 sc->dpll_def.ti_clkmode_offset, sc->dpll_def.ti_idlest_offset, 252 sc->dpll_def.ti_clksel_offset, 253 sc->dpll_def.ti_autoidle_offset); 254 255 return (0); 256 } 257 static int 258 ti_dpll_attach(device_t dev) 259 { 260 struct ti_dpll_softc *sc; 261 phandle_t node; 262 int err; 263 264 sc = device_get_softc(dev); 265 sc->dev = dev; 266 267 sc->dpll_type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 268 node = ofw_bus_get_node(dev); 269 270 /* Grab the content of reg properties */ 271 parse_dpll_reg(sc); 272 273 /* default flags (OMAP4&AM335x) not present in the dts at moment */ 274 sc->dpll_def.ti_clkmode_flags = MN_BYPASS_MODE_FLAG | LOCK_MODE_FLAG; 275 276 if (OF_hasprop(node, "ti,low-power-stop")) { 277 sc->dpll_def.ti_clkmode_flags |= LOW_POWER_STOP_MODE_FLAG; 278 } 279 if (OF_hasprop(node, "ti,low-power-bypass")) { 280 sc->dpll_def.ti_clkmode_flags |= IDLE_BYPASS_LOW_POWER_MODE_FLAG; 281 } 282 if (OF_hasprop(node, "ti,lock")) { 283 sc->dpll_def.ti_clkmode_flags |= LOCK_MODE_FLAG; 284 } 285 286 read_clock_cells(sc->dev, &sc->clock_cell); 287 288 create_clkdef(sc->dev, &sc->clock_cell, &sc->dpll_def.clkdef); 289 290 err = find_parent_clock_names(sc->dev, &sc->clock_cell, 291 &sc->dpll_def.clkdef); 292 293 if (err) { 294 /* free_clkdef will be called in ti_dpll_new_pass */ 295 DPRINTF(sc->dev, "find_parent_clock_names failed\n"); 296 return (bus_generic_attach(sc->dev)); 297 } 298 299 err = register_clk(sc); 300 301 if (err) { 302 /* free_clkdef will be called in ti_dpll_new_pass */ 303 DPRINTF(sc->dev, "register_clk failed\n"); 304 return (bus_generic_attach(sc->dev)); 305 } 306 307 sc->attach_done = true; 308 309 free_clkdef(&sc->dpll_def.clkdef); 310 311 return (bus_generic_attach(sc->dev)); 312 } 313 314 static int 315 ti_dpll_detach(device_t dev) 316 { 317 return (EBUSY); 318 } 319 320 static void 321 ti_dpll_new_pass(device_t dev) 322 { 323 struct ti_dpll_softc *sc; 324 int err; 325 326 sc = device_get_softc(dev); 327 328 if (sc->attach_done) { 329 return; 330 } 331 332 err = find_parent_clock_names(sc->dev, &sc->clock_cell, 333 &sc->dpll_def.clkdef); 334 if (err) { 335 /* free_clkdef will be called in a later call to ti_dpll_new_pass */ 336 DPRINTF(sc->dev, 337 "new_pass find_parent_clock_names failed\n"); 338 return; 339 } 340 341 err = register_clk(sc); 342 if (err) { 343 /* free_clkdef will be called in a later call to ti_dpll_new_pass */ 344 DPRINTF(sc->dev, "new_pass register_clk failed\n"); 345 return; 346 } 347 348 sc->attach_done = true; 349 free_clkdef(&sc->dpll_def.clkdef); 350 } 351 352 static device_method_t ti_dpll_methods[] = { 353 /* Device interface */ 354 DEVMETHOD(device_probe, ti_dpll_probe), 355 DEVMETHOD(device_attach, ti_dpll_attach), 356 DEVMETHOD(device_detach, ti_dpll_detach), 357 358 /* Bus interface */ 359 DEVMETHOD(bus_new_pass, ti_dpll_new_pass), 360 361 DEVMETHOD_END 362 }; 363 364 DEFINE_CLASS_0(ti_dpll, ti_dpll_driver, ti_dpll_methods, 365 sizeof(struct ti_dpll_softc)); 366 367 EARLY_DRIVER_MODULE(ti_dpll, simplebus, ti_dpll_driver, 0, 0, 368 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 369 MODULE_VERSION(ti_dpll, 1); 370