1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/conf.h> 31 #include <sys/bus.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/systm.h> 35 #include <sys/libkern.h> 36 37 #include <machine/bus.h> 38 #include <dev/fdt/simplebus.h> 39 40 #include <dev/extres/clk/clk_div.h> 41 #include <dev/ofw/ofw_bus.h> 42 #include <dev/ofw/ofw_bus_subr.h> 43 44 #include "clock_common.h" 45 46 #if 0 47 #define DPRINTF(dev, msg...) device_printf(dev, msg) 48 #else 49 #define DPRINTF(dev, msg...) 50 #endif 51 52 /* 53 * Devicetree description 54 * Documentation/devicetree/bindings/clock/ti/divider.txt 55 */ 56 57 struct ti_divider_softc { 58 device_t sc_dev; 59 bool attach_done; 60 struct clk_div_def div_def; 61 62 struct clock_cell_info clock_cell; 63 struct clkdom *clkdom; 64 }; 65 66 static int ti_divider_probe(device_t dev); 67 static int ti_divider_attach(device_t dev); 68 static int ti_divider_detach(device_t dev); 69 70 #define TI_DIVIDER_CLOCK 2 71 #define TI_COMPOSITE_DIVIDER_CLOCK 1 72 #define TI_DIVIDER_END 0 73 74 static struct ofw_compat_data compat_data[] = { 75 { "ti,divider-clock", TI_DIVIDER_CLOCK }, 76 { "ti,composite-divider-clock", TI_COMPOSITE_DIVIDER_CLOCK }, 77 { NULL, TI_DIVIDER_END } 78 }; 79 80 static int 81 register_clk(struct ti_divider_softc *sc) { 82 int err; 83 84 sc->clkdom = clkdom_create(sc->sc_dev); 85 if (sc->clkdom == NULL) { 86 DPRINTF(sc->sc_dev, "Failed to create clkdom\n"); 87 return (ENXIO); 88 } 89 90 err = clknode_div_register(sc->clkdom, &sc->div_def); 91 if (err) { 92 DPRINTF(sc->sc_dev, "clknode_div_register failed %x\n", err); 93 return (ENXIO); 94 } 95 96 err = clkdom_finit(sc->clkdom); 97 if (err) { 98 DPRINTF(sc->sc_dev, "Clk domain finit fails %x.\n", err); 99 return (ENXIO); 100 } 101 102 return (0); 103 } 104 105 static int 106 ti_divider_probe(device_t dev) 107 { 108 if (!ofw_bus_status_okay(dev)) 109 return (ENXIO); 110 111 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 112 return (ENXIO); 113 114 device_set_desc(dev, "TI Divider Clock"); 115 116 return (BUS_PROBE_DEFAULT); 117 } 118 119 static int 120 ti_divider_attach(device_t dev) 121 { 122 struct ti_divider_softc *sc; 123 phandle_t node; 124 int err; 125 cell_t value; 126 uint32_t ti_max_div; 127 128 sc = device_get_softc(dev); 129 sc->sc_dev = dev; 130 node = ofw_bus_get_node(dev); 131 132 /* Grab the content of reg properties */ 133 OF_getencprop(node, "reg", &value, sizeof(value)); 134 sc->div_def.offset = value; 135 136 if (OF_hasprop(node, "ti,bit-shift")) { 137 OF_getencprop(node, "ti,bit-shift", &value, sizeof(value)); 138 sc->div_def.i_shift = value; 139 } 140 141 if (OF_hasprop(node, "ti,index-starts-at-one")) { 142 sc->div_def.div_flags = CLK_DIV_ZERO_BASED; 143 } 144 145 if (OF_hasprop(node, "ti,index-power-of-two")) { 146 /* FIXME: later */ 147 device_printf(sc->sc_dev, "ti,index-power-of-two - Not implemented\n"); 148 /* remember to update i_width a few lines below */ 149 } 150 if (OF_hasprop(node, "ti,max-div")) { 151 OF_getencprop(node, "ti,max-div", &value, sizeof(value)); 152 ti_max_div = value; 153 } 154 155 if (OF_hasprop(node, "clock-output-names")) 156 device_printf(sc->sc_dev, "clock-output-names\n"); 157 if (OF_hasprop(node, "ti,dividers")) 158 device_printf(sc->sc_dev, "ti,dividers\n"); 159 if (OF_hasprop(node, "ti,min-div")) 160 device_printf(sc->sc_dev, "ti,min-div - Not implemented\n"); 161 162 if (OF_hasprop(node, "ti,autoidle-shift")) 163 device_printf(sc->sc_dev, "ti,autoidle-shift - Not implemented\n"); 164 if (OF_hasprop(node, "ti,set-rate-parent")) 165 device_printf(sc->sc_dev, "ti,set-rate-parent - Not implemented\n"); 166 if (OF_hasprop(node, "ti,latch-bit")) 167 device_printf(sc->sc_dev, "ti,latch-bit - Not implemented\n"); 168 169 /* Figure out the width from ti_max_div */ 170 if (sc->div_def.div_flags) 171 sc->div_def.i_width = fls(ti_max_div-1); 172 else 173 sc->div_def.i_width = fls(ti_max_div); 174 175 DPRINTF(sc->sc_dev, "div_def.i_width %x\n", sc->div_def.i_width); 176 177 read_clock_cells(sc->sc_dev, &sc->clock_cell); 178 179 create_clkdef(sc->sc_dev, &sc->clock_cell, &sc->div_def.clkdef); 180 181 err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->div_def.clkdef); 182 183 if (err) { 184 /* free_clkdef will be called in ti_divider_new_pass */ 185 DPRINTF(sc->sc_dev, "find_parent_clock_names failed\n"); 186 return (bus_generic_attach(sc->sc_dev)); 187 } 188 189 err = register_clk(sc); 190 191 if (err) { 192 /* free_clkdef will be called in ti_divider_new_pass */ 193 DPRINTF(sc->sc_dev, "register_clk failed\n"); 194 return (bus_generic_attach(sc->sc_dev)); 195 } 196 197 sc->attach_done = true; 198 199 free_clkdef(&sc->div_def.clkdef); 200 201 return (bus_generic_attach(sc->sc_dev)); 202 } 203 204 static int 205 ti_divider_detach(device_t dev) 206 { 207 return (EBUSY); 208 } 209 210 static void 211 ti_divider_new_pass(device_t dev) 212 { 213 struct ti_divider_softc *sc; 214 int err; 215 216 sc = device_get_softc(dev); 217 218 if (sc->attach_done) { 219 return; 220 } 221 222 err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->div_def.clkdef); 223 if (err) { 224 /* free_clkdef will be called in a later call to ti_divider_new_pass */ 225 DPRINTF(sc->sc_dev, "new_pass find_parent_clock_names failed\n"); 226 return; 227 } 228 229 err = register_clk(sc); 230 if (err) { 231 /* free_clkdef will be called in a later call to ti_divider_new_pass */ 232 DPRINTF(sc->sc_dev, "new_pass register_clk failed\n"); 233 return; 234 } 235 236 sc->attach_done = true; 237 238 free_clkdef(&sc->div_def.clkdef); 239 } 240 241 static device_method_t ti_divider_methods[] = { 242 /* Device interface */ 243 DEVMETHOD(device_probe, ti_divider_probe), 244 DEVMETHOD(device_attach, ti_divider_attach), 245 DEVMETHOD(device_detach, ti_divider_detach), 246 247 /* Bus interface */ 248 DEVMETHOD(bus_new_pass, ti_divider_new_pass), 249 250 DEVMETHOD_END 251 }; 252 253 DEFINE_CLASS_0(ti_divider, ti_divider_driver, ti_divider_methods, 254 sizeof(struct ti_divider_softc)); 255 256 EARLY_DRIVER_MODULE(ti_divider, simplebus, ti_divider_driver, 0, 0, 257 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 258 MODULE_VERSION(ti_divider, 1); 259