1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright 2016 Michal Meloun <mmel@FreeBSD.org> 5 * 6 * Copyright (c) 2020 Oskar Holmlund <oskar.holmlund@ohdata.se> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/fbio.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 #include <sys/resource.h> 41 #include <machine/bus.h> 42 #include <vm/vm.h> 43 #include <vm/vm_extern.h> 44 #include <vm/vm_kern.h> 45 #include <vm/pmap.h> 46 47 #include <dev/fdt/simplebus.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <arm/ti/clk/ti_clk_clkctrl.h> 53 #include <arm/ti/ti_omap4_cm.h> 54 #include <arm/ti/ti_cpuid.h> 55 56 #if 0 57 #define DPRINTF(dev, msg...) device_printf(dev, msg) 58 #else 59 #define DPRINTF(dev, msg...) 60 #endif 61 62 #define L4LS_CLKCTRL_38 2 63 #define L4_WKUP_CLKCTRL_0 1 64 #define NO_SPECIAL_REG 0 65 66 /* Documentation/devicetree/bindings/clock/ti-clkctrl.txt */ 67 68 #define TI_CLKCTRL_L4_WKUP 5 69 #define TI_CLKCTRL_L4_SECURE 4 70 #define TI_CLKCTRL_L4_PER 3 71 #define TI_CLKCTRL_L4_CFG 2 72 #define TI_CLKCTRL 1 73 #define TI_CLKCTRL_END 0 74 75 static struct ofw_compat_data compat_data[] = { 76 { "ti,clkctrl-l4-wkup", TI_CLKCTRL_L4_WKUP }, 77 { "ti,clkctrl-l4-secure", TI_CLKCTRL_L4_SECURE }, 78 { "ti,clkctrl-l4-per", TI_CLKCTRL_L4_PER }, 79 { "ti,clkctrl-l4-cfg", TI_CLKCTRL_L4_CFG }, 80 { "ti,clkctrl", TI_CLKCTRL }, 81 { NULL, TI_CLKCTRL_END } 82 }; 83 84 struct ti_clkctrl_softc { 85 device_t dev; 86 87 struct clkdom *clkdom; 88 }; 89 90 static int ti_clkctrl_probe(device_t dev); 91 static int ti_clkctrl_attach(device_t dev); 92 static int ti_clkctrl_detach(device_t dev); 93 int clkctrl_ofw_map(struct clkdom *clkdom, uint32_t ncells, 94 phandle_t *cells, struct clknode **clk); 95 static int 96 create_clkctrl(struct ti_clkctrl_softc *sc, cell_t *reg, uint32_t index, uint32_t reg_offset, 97 uint64_t parent_offset, const char *org_name, bool special_gdbclk_reg); 98 99 static int 100 ti_clkctrl_probe(device_t dev) 101 { 102 if (!ofw_bus_status_okay(dev)) 103 return (ENXIO); 104 105 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 106 return (ENXIO); 107 108 device_set_desc(dev, "TI clkctrl"); 109 110 return (BUS_PROBE_DEFAULT); 111 } 112 113 static int 114 ti_clkctrl_attach(device_t dev) 115 { 116 struct ti_clkctrl_softc *sc; 117 phandle_t node; 118 cell_t *reg; 119 ssize_t numbytes_reg; 120 int num_reg, err, ti_clock_cells; 121 uint32_t index, reg_offset, reg_address; 122 const char *org_name; 123 uint64_t parent_offset; 124 uint8_t special_reg = NO_SPECIAL_REG; 125 126 sc = device_get_softc(dev); 127 sc->dev = dev; 128 node = ofw_bus_get_node(dev); 129 130 /* Sanity check */ 131 err = OF_searchencprop(node, "#clock-cells", 132 &ti_clock_cells, sizeof(ti_clock_cells)); 133 if (err == -1) { 134 device_printf(sc->dev, "Failed to get #clock-cells\n"); 135 return (ENXIO); 136 } 137 138 if (ti_clock_cells != 2) { 139 device_printf(sc->dev, "clock cells(%d) != 2\n", 140 ti_clock_cells); 141 return (ENXIO); 142 } 143 144 /* Grab the content of reg properties */ 145 numbytes_reg = OF_getproplen(node, "reg"); 146 if (numbytes_reg == 0) { 147 device_printf(sc->dev, "reg property empty - check your devicetree\n"); 148 return (ENXIO); 149 } 150 num_reg = numbytes_reg / sizeof(cell_t); 151 152 reg = malloc(numbytes_reg, M_DEVBUF, M_WAITOK); 153 OF_getencprop(node, "reg", reg, numbytes_reg); 154 155 /* Create clock domain */ 156 sc->clkdom = clkdom_create(sc->dev); 157 if (sc->clkdom == NULL) { 158 free(reg, M_DEVBUF); 159 DPRINTF(sc->dev, "Failed to create clkdom\n"); 160 return (ENXIO); 161 } 162 clkdom_set_ofw_mapper(sc->clkdom, clkctrl_ofw_map); 163 164 /* Create clock nodes */ 165 /* name */ 166 clk_parse_ofw_clk_name(sc->dev, node, &org_name); 167 168 /* Get parent range */ 169 parent_offset = ti_omap4_cm_get_simplebus_base_host(device_get_parent(dev)); 170 171 /* Check if this is a clkctrl with special registers like gpio */ 172 switch (ti_chip()) { 173 #ifdef SOC_OMAP4 174 case CHIP_OMAP_4: 175 /* FIXME: Todo */ 176 break; 177 178 #endif /* SOC_OMAP4 */ 179 #ifdef SOC_TI_AM335X 180 /* Checkout TRM 8.1.12.1.29 - 8.1.12.31 and 8.1.12.2.3 181 * and the DTS. 182 */ 183 case CHIP_AM335X: 184 if (strcmp(org_name, "l4ls-clkctrl@38") == 0) 185 special_reg = L4LS_CLKCTRL_38; 186 else if (strcmp(org_name, "l4-wkup-clkctrl@0") == 0) 187 special_reg = L4_WKUP_CLKCTRL_0; 188 break; 189 #endif /* SOC_TI_AM335X */ 190 default: 191 break; 192 } 193 194 /* reg property has a pair of (base address, length) */ 195 for (index = 0; index < num_reg; index += 2) { 196 for (reg_offset = 0; reg_offset < reg[index+1]; reg_offset += sizeof(cell_t)) { 197 err = create_clkctrl(sc, reg, index, reg_offset, parent_offset, 198 org_name, false); 199 if (err) 200 goto cleanup; 201 202 /* Create special clkctrl for GDBCLK in GPIO registers */ 203 switch (special_reg) { 204 case NO_SPECIAL_REG: 205 break; 206 case L4LS_CLKCTRL_38: 207 reg_address = reg[index] + reg_offset-reg[0]; 208 if (reg_address == 0x74 || 209 reg_address == 0x78 || 210 reg_address == 0x7C) 211 { 212 err = create_clkctrl(sc, reg, index, reg_offset, 213 parent_offset, org_name, true); 214 if (err) 215 goto cleanup; 216 } 217 break; 218 case L4_WKUP_CLKCTRL_0: 219 reg_address = reg[index] + reg_offset - reg[0]; 220 if (reg_address == 0x8) 221 { 222 err = create_clkctrl(sc, reg, index, reg_offset, 223 parent_offset, org_name, true); 224 if (err) 225 goto cleanup; 226 } 227 break; 228 } /* switch (special_reg) */ 229 } /* inner for */ 230 } /* for */ 231 232 err = clkdom_finit(sc->clkdom); 233 if (err) { 234 DPRINTF(sc->dev, "Clk domain finit fails %x.\n", err); 235 err = ENXIO; 236 goto cleanup; 237 } 238 239 cleanup: 240 OF_prop_free(__DECONST(char *, org_name)); 241 242 free(reg, M_DEVBUF); 243 244 if (err) 245 return (err); 246 247 return (bus_generic_attach(dev)); 248 } 249 250 static int 251 ti_clkctrl_detach(device_t dev) 252 { 253 return (EBUSY); 254 } 255 256 /* modified version of default mapper from clk.c */ 257 int 258 clkctrl_ofw_map(struct clkdom *clkdom, uint32_t ncells, 259 phandle_t *cells, struct clknode **clk) { 260 if (ncells == 0) 261 *clk = clknode_find_by_id(clkdom, 1); 262 else if (ncells == 1) 263 *clk = clknode_find_by_id(clkdom, cells[0]); 264 else if (ncells == 2) { 265 /* To avoid collision with other IDs just add one. 266 * All other registers has an offset of 4 from each other. 267 */ 268 if (cells[1]) 269 *clk = clknode_find_by_id(clkdom, cells[0]+1); 270 else 271 *clk = clknode_find_by_id(clkdom, cells[0]); 272 } 273 else 274 return (ERANGE); 275 276 if (*clk == NULL) 277 return (ENXIO); 278 279 return (0); 280 } 281 282 static int 283 create_clkctrl(struct ti_clkctrl_softc *sc, cell_t *reg, uint32_t index, uint32_t reg_offset, 284 uint64_t parent_offset, const char *org_name, bool special_gdbclk_reg) { 285 struct ti_clk_clkctrl_def def; 286 char *name; 287 size_t name_len; 288 int err; 289 290 name_len = strlen(org_name) + 1 + 5; /* 5 = _xxxx */ 291 name = malloc(name_len, M_OFWPROP, M_WAITOK); 292 293 /* 294 * Check out XX_CLKCTRL-INDEX(offset)-macro dance in 295 * sys/gnu/dts/dts/include/dt-bindings/clock/am3.h 296 * sys/gnu/dts/dts/include/dt-bindings/clock/am4.h 297 * sys/gnu/dts/dts/include/dt-bindings/clock/dra7.h 298 * reg[0] are in practice the same as the offset described in the dts. 299 */ 300 /* special_gdbclk_reg are 0 or 1 */ 301 def.clkdef.id = reg[index] + reg_offset - reg[0] + special_gdbclk_reg; 302 def.register_offset = parent_offset + reg[index] + reg_offset; 303 304 /* Indicate this clkctrl is special and dont use IDLEST/MODULEMODE */ 305 def.gdbclk = special_gdbclk_reg; 306 307 /* Make up an uniq name in the namespace for each clkctrl */ 308 snprintf(name, name_len, "%s_%x", 309 org_name, def.clkdef.id); 310 def.clkdef.name = (const char *) name; 311 312 DPRINTF(sc->dev, "ti_clkctrl_attach: reg[%d]: %s %x\n", 313 index, def.clkdef.name, def.clkdef.id); 314 315 /* No parent name */ 316 def.clkdef.parent_cnt = 0; 317 318 /* set flags */ 319 def.clkdef.flags = 0x0; 320 321 /* Register the clkctrl */ 322 err = ti_clknode_clkctrl_register(sc->clkdom, &def); 323 if (err) { 324 DPRINTF(sc->dev, 325 "ti_clknode_clkctrl_register[%d:%d] failed %x\n", 326 index, reg_offset, err); 327 err = ENXIO; 328 } 329 OF_prop_free(name); 330 return (err); 331 } 332 333 static device_method_t ti_clkctrl_methods[] = { 334 /* Device interface */ 335 DEVMETHOD(device_probe, ti_clkctrl_probe), 336 DEVMETHOD(device_attach, ti_clkctrl_attach), 337 DEVMETHOD(device_detach, ti_clkctrl_detach), 338 339 DEVMETHOD_END 340 }; 341 342 DEFINE_CLASS_0(ti_clkctrl, ti_clkctrl_driver, ti_clkctrl_methods, 343 sizeof(struct ti_clkctrl_softc)); 344 345 EARLY_DRIVER_MODULE(ti_clkctrl, simplebus, ti_clkctrl_driver, 0, 0, 346 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 347 348 MODULE_VERSION(ti_clkctrl, 1); 349